intel_dp.c 126 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Keith Packard <keithp@keithp.com>
  25. *
  26. */
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include <linux/export.h>
  30. #include <linux/notifier.h>
  31. #include <linux/reboot.h>
  32. #include <drm/drmP.h>
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_crtc_helper.h>
  35. #include <drm/drm_edid.h>
  36. #include "intel_drv.h"
  37. #include <drm/i915_drm.h>
  38. #include "i915_drv.h"
  39. #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
  40. struct dp_link_dpll {
  41. int link_bw;
  42. struct dpll dpll;
  43. };
  44. static const struct dp_link_dpll gen4_dpll[] = {
  45. { DP_LINK_BW_1_62,
  46. { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  47. { DP_LINK_BW_2_7,
  48. { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  49. };
  50. static const struct dp_link_dpll pch_dpll[] = {
  51. { DP_LINK_BW_1_62,
  52. { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  53. { DP_LINK_BW_2_7,
  54. { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  55. };
  56. static const struct dp_link_dpll vlv_dpll[] = {
  57. { DP_LINK_BW_1_62,
  58. { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  59. { DP_LINK_BW_2_7,
  60. { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  61. };
  62. /*
  63. * CHV supports eDP 1.4 that have more link rates.
  64. * Below only provides the fixed rate but exclude variable rate.
  65. */
  66. static const struct dp_link_dpll chv_dpll[] = {
  67. /*
  68. * CHV requires to program fractional division for m2.
  69. * m2 is stored in fixed point format using formula below
  70. * (m2_int << 22) | m2_fraction
  71. */
  72. { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
  73. { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  74. { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
  75. { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  76. { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
  77. { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  78. };
  79. /**
  80. * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  81. * @intel_dp: DP struct
  82. *
  83. * If a CPU or PCH DP output is attached to an eDP panel, this function
  84. * will return true, and false otherwise.
  85. */
  86. static bool is_edp(struct intel_dp *intel_dp)
  87. {
  88. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  89. return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  90. }
  91. static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  92. {
  93. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  94. return intel_dig_port->base.base.dev;
  95. }
  96. static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  97. {
  98. return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  99. }
  100. static void intel_dp_link_down(struct intel_dp *intel_dp);
  101. static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
  102. static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
  103. static int
  104. intel_dp_max_link_bw(struct intel_dp *intel_dp)
  105. {
  106. int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
  107. struct drm_device *dev = intel_dp->attached_connector->base.dev;
  108. switch (max_link_bw) {
  109. case DP_LINK_BW_1_62:
  110. case DP_LINK_BW_2_7:
  111. break;
  112. case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
  113. if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
  114. INTEL_INFO(dev)->gen >= 8) &&
  115. intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
  116. max_link_bw = DP_LINK_BW_5_4;
  117. else
  118. max_link_bw = DP_LINK_BW_2_7;
  119. break;
  120. default:
  121. WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
  122. max_link_bw);
  123. max_link_bw = DP_LINK_BW_1_62;
  124. break;
  125. }
  126. return max_link_bw;
  127. }
  128. static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
  129. {
  130. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  131. struct drm_device *dev = intel_dig_port->base.base.dev;
  132. u8 source_max, sink_max;
  133. source_max = 4;
  134. if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
  135. (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
  136. source_max = 2;
  137. sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
  138. return min(source_max, sink_max);
  139. }
  140. /*
  141. * The units on the numbers in the next two are... bizarre. Examples will
  142. * make it clearer; this one parallels an example in the eDP spec.
  143. *
  144. * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
  145. *
  146. * 270000 * 1 * 8 / 10 == 216000
  147. *
  148. * The actual data capacity of that configuration is 2.16Gbit/s, so the
  149. * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
  150. * or equivalently, kilopixels per second - so for 1680x1050R it'd be
  151. * 119000. At 18bpp that's 2142000 kilobits per second.
  152. *
  153. * Thus the strange-looking division by 10 in intel_dp_link_required, to
  154. * get the result in decakilobits instead of kilobits.
  155. */
  156. static int
  157. intel_dp_link_required(int pixel_clock, int bpp)
  158. {
  159. return (pixel_clock * bpp + 9) / 10;
  160. }
  161. static int
  162. intel_dp_max_data_rate(int max_link_clock, int max_lanes)
  163. {
  164. return (max_link_clock * max_lanes * 8) / 10;
  165. }
  166. static enum drm_mode_status
  167. intel_dp_mode_valid(struct drm_connector *connector,
  168. struct drm_display_mode *mode)
  169. {
  170. struct intel_dp *intel_dp = intel_attached_dp(connector);
  171. struct intel_connector *intel_connector = to_intel_connector(connector);
  172. struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
  173. int target_clock = mode->clock;
  174. int max_rate, mode_rate, max_lanes, max_link_clock;
  175. if (is_edp(intel_dp) && fixed_mode) {
  176. if (mode->hdisplay > fixed_mode->hdisplay)
  177. return MODE_PANEL;
  178. if (mode->vdisplay > fixed_mode->vdisplay)
  179. return MODE_PANEL;
  180. target_clock = fixed_mode->clock;
  181. }
  182. max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
  183. max_lanes = intel_dp_max_lane_count(intel_dp);
  184. max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
  185. mode_rate = intel_dp_link_required(target_clock, 18);
  186. if (mode_rate > max_rate)
  187. return MODE_CLOCK_HIGH;
  188. if (mode->clock < 10000)
  189. return MODE_CLOCK_LOW;
  190. if (mode->flags & DRM_MODE_FLAG_DBLCLK)
  191. return MODE_H_ILLEGAL;
  192. return MODE_OK;
  193. }
  194. static uint32_t
  195. pack_aux(uint8_t *src, int src_bytes)
  196. {
  197. int i;
  198. uint32_t v = 0;
  199. if (src_bytes > 4)
  200. src_bytes = 4;
  201. for (i = 0; i < src_bytes; i++)
  202. v |= ((uint32_t) src[i]) << ((3-i) * 8);
  203. return v;
  204. }
  205. static void
  206. unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
  207. {
  208. int i;
  209. if (dst_bytes > 4)
  210. dst_bytes = 4;
  211. for (i = 0; i < dst_bytes; i++)
  212. dst[i] = src >> ((3-i) * 8);
  213. }
  214. /* hrawclock is 1/4 the FSB frequency */
  215. static int
  216. intel_hrawclk(struct drm_device *dev)
  217. {
  218. struct drm_i915_private *dev_priv = dev->dev_private;
  219. uint32_t clkcfg;
  220. /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
  221. if (IS_VALLEYVIEW(dev))
  222. return 200;
  223. clkcfg = I915_READ(CLKCFG);
  224. switch (clkcfg & CLKCFG_FSB_MASK) {
  225. case CLKCFG_FSB_400:
  226. return 100;
  227. case CLKCFG_FSB_533:
  228. return 133;
  229. case CLKCFG_FSB_667:
  230. return 166;
  231. case CLKCFG_FSB_800:
  232. return 200;
  233. case CLKCFG_FSB_1067:
  234. return 266;
  235. case CLKCFG_FSB_1333:
  236. return 333;
  237. /* these two are just a guess; one of them might be right */
  238. case CLKCFG_FSB_1600:
  239. case CLKCFG_FSB_1600_ALT:
  240. return 400;
  241. default:
  242. return 133;
  243. }
  244. }
  245. static void
  246. intel_dp_init_panel_power_sequencer(struct drm_device *dev,
  247. struct intel_dp *intel_dp,
  248. struct edp_power_seq *out);
  249. static void
  250. intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
  251. struct intel_dp *intel_dp,
  252. struct edp_power_seq *out);
  253. static enum pipe
  254. vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
  255. {
  256. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  257. struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
  258. struct drm_device *dev = intel_dig_port->base.base.dev;
  259. struct drm_i915_private *dev_priv = dev->dev_private;
  260. enum port port = intel_dig_port->port;
  261. enum pipe pipe;
  262. /* modeset should have pipe */
  263. if (crtc)
  264. return to_intel_crtc(crtc)->pipe;
  265. /* init time, try to find a pipe with this port selected */
  266. for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
  267. u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
  268. PANEL_PORT_SELECT_MASK;
  269. if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
  270. return pipe;
  271. if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
  272. return pipe;
  273. }
  274. /* shrug */
  275. return PIPE_A;
  276. }
  277. static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
  278. {
  279. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  280. if (HAS_PCH_SPLIT(dev))
  281. return PCH_PP_CONTROL;
  282. else
  283. return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
  284. }
  285. static u32 _pp_stat_reg(struct intel_dp *intel_dp)
  286. {
  287. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  288. if (HAS_PCH_SPLIT(dev))
  289. return PCH_PP_STATUS;
  290. else
  291. return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
  292. }
  293. /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
  294. This function only applicable when panel PM state is not to be tracked */
  295. static int edp_notify_handler(struct notifier_block *this, unsigned long code,
  296. void *unused)
  297. {
  298. struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
  299. edp_notifier);
  300. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  301. struct drm_i915_private *dev_priv = dev->dev_private;
  302. u32 pp_div;
  303. u32 pp_ctrl_reg, pp_div_reg;
  304. enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
  305. if (!is_edp(intel_dp) || code != SYS_RESTART)
  306. return 0;
  307. if (IS_VALLEYVIEW(dev)) {
  308. pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
  309. pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
  310. pp_div = I915_READ(pp_div_reg);
  311. pp_div &= PP_REFERENCE_DIVIDER_MASK;
  312. /* 0x1F write to PP_DIV_REG sets max cycle delay */
  313. I915_WRITE(pp_div_reg, pp_div | 0x1F);
  314. I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
  315. msleep(intel_dp->panel_power_cycle_delay);
  316. }
  317. return 0;
  318. }
  319. static bool edp_have_panel_power(struct intel_dp *intel_dp)
  320. {
  321. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  322. struct drm_i915_private *dev_priv = dev->dev_private;
  323. return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
  324. }
  325. static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
  326. {
  327. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  328. struct drm_i915_private *dev_priv = dev->dev_private;
  329. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  330. struct intel_encoder *intel_encoder = &intel_dig_port->base;
  331. enum intel_display_power_domain power_domain;
  332. power_domain = intel_display_port_power_domain(intel_encoder);
  333. return intel_display_power_enabled(dev_priv, power_domain) &&
  334. (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
  335. }
  336. static void
  337. intel_dp_check_edp(struct intel_dp *intel_dp)
  338. {
  339. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  340. struct drm_i915_private *dev_priv = dev->dev_private;
  341. if (!is_edp(intel_dp))
  342. return;
  343. if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
  344. WARN(1, "eDP powered off while attempting aux channel communication.\n");
  345. DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
  346. I915_READ(_pp_stat_reg(intel_dp)),
  347. I915_READ(_pp_ctrl_reg(intel_dp)));
  348. }
  349. }
  350. static uint32_t
  351. intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
  352. {
  353. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  354. struct drm_device *dev = intel_dig_port->base.base.dev;
  355. struct drm_i915_private *dev_priv = dev->dev_private;
  356. uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
  357. uint32_t status;
  358. bool done;
  359. #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
  360. if (has_aux_irq)
  361. done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
  362. msecs_to_jiffies_timeout(10));
  363. else
  364. done = wait_for_atomic(C, 10) == 0;
  365. if (!done)
  366. DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
  367. has_aux_irq);
  368. #undef C
  369. return status;
  370. }
  371. static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
  372. {
  373. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  374. struct drm_device *dev = intel_dig_port->base.base.dev;
  375. /*
  376. * The clock divider is based off the hrawclk, and would like to run at
  377. * 2MHz. So, take the hrawclk value and divide by 2 and use that
  378. */
  379. return index ? 0 : intel_hrawclk(dev) / 2;
  380. }
  381. static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
  382. {
  383. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  384. struct drm_device *dev = intel_dig_port->base.base.dev;
  385. if (index)
  386. return 0;
  387. if (intel_dig_port->port == PORT_A) {
  388. if (IS_GEN6(dev) || IS_GEN7(dev))
  389. return 200; /* SNB & IVB eDP input clock at 400Mhz */
  390. else
  391. return 225; /* eDP input clock at 450Mhz */
  392. } else {
  393. return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
  394. }
  395. }
  396. static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
  397. {
  398. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  399. struct drm_device *dev = intel_dig_port->base.base.dev;
  400. struct drm_i915_private *dev_priv = dev->dev_private;
  401. if (intel_dig_port->port == PORT_A) {
  402. if (index)
  403. return 0;
  404. return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
  405. } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
  406. /* Workaround for non-ULT HSW */
  407. switch (index) {
  408. case 0: return 63;
  409. case 1: return 72;
  410. default: return 0;
  411. }
  412. } else {
  413. return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
  414. }
  415. }
  416. static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
  417. {
  418. return index ? 0 : 100;
  419. }
  420. static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
  421. bool has_aux_irq,
  422. int send_bytes,
  423. uint32_t aux_clock_divider)
  424. {
  425. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  426. struct drm_device *dev = intel_dig_port->base.base.dev;
  427. uint32_t precharge, timeout;
  428. if (IS_GEN6(dev))
  429. precharge = 3;
  430. else
  431. precharge = 5;
  432. if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
  433. timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
  434. else
  435. timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
  436. return DP_AUX_CH_CTL_SEND_BUSY |
  437. DP_AUX_CH_CTL_DONE |
  438. (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
  439. DP_AUX_CH_CTL_TIME_OUT_ERROR |
  440. timeout |
  441. DP_AUX_CH_CTL_RECEIVE_ERROR |
  442. (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
  443. (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
  444. (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
  445. }
  446. static int
  447. intel_dp_aux_ch(struct intel_dp *intel_dp,
  448. uint8_t *send, int send_bytes,
  449. uint8_t *recv, int recv_size)
  450. {
  451. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  452. struct drm_device *dev = intel_dig_port->base.base.dev;
  453. struct drm_i915_private *dev_priv = dev->dev_private;
  454. uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
  455. uint32_t ch_data = ch_ctl + 4;
  456. uint32_t aux_clock_divider;
  457. int i, ret, recv_bytes;
  458. uint32_t status;
  459. int try, clock = 0;
  460. bool has_aux_irq = HAS_AUX_IRQ(dev);
  461. bool vdd;
  462. vdd = _edp_panel_vdd_on(intel_dp);
  463. /* dp aux is extremely sensitive to irq latency, hence request the
  464. * lowest possible wakeup latency and so prevent the cpu from going into
  465. * deep sleep states.
  466. */
  467. pm_qos_update_request(&dev_priv->pm_qos, 0);
  468. intel_dp_check_edp(intel_dp);
  469. intel_aux_display_runtime_get(dev_priv);
  470. /* Try to wait for any previous AUX channel activity */
  471. for (try = 0; try < 3; try++) {
  472. status = I915_READ_NOTRACE(ch_ctl);
  473. if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
  474. break;
  475. msleep(1);
  476. }
  477. if (try == 3) {
  478. WARN(1, "dp_aux_ch not started status 0x%08x\n",
  479. I915_READ(ch_ctl));
  480. ret = -EBUSY;
  481. goto out;
  482. }
  483. /* Only 5 data registers! */
  484. if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
  485. ret = -E2BIG;
  486. goto out;
  487. }
  488. while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
  489. u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
  490. has_aux_irq,
  491. send_bytes,
  492. aux_clock_divider);
  493. /* Must try at least 3 times according to DP spec */
  494. for (try = 0; try < 5; try++) {
  495. /* Load the send data into the aux channel data registers */
  496. for (i = 0; i < send_bytes; i += 4)
  497. I915_WRITE(ch_data + i,
  498. pack_aux(send + i, send_bytes - i));
  499. /* Send the command and wait for it to complete */
  500. I915_WRITE(ch_ctl, send_ctl);
  501. status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
  502. /* Clear done status and any errors */
  503. I915_WRITE(ch_ctl,
  504. status |
  505. DP_AUX_CH_CTL_DONE |
  506. DP_AUX_CH_CTL_TIME_OUT_ERROR |
  507. DP_AUX_CH_CTL_RECEIVE_ERROR);
  508. if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
  509. DP_AUX_CH_CTL_RECEIVE_ERROR))
  510. continue;
  511. if (status & DP_AUX_CH_CTL_DONE)
  512. break;
  513. }
  514. if (status & DP_AUX_CH_CTL_DONE)
  515. break;
  516. }
  517. if ((status & DP_AUX_CH_CTL_DONE) == 0) {
  518. DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
  519. ret = -EBUSY;
  520. goto out;
  521. }
  522. /* Check for timeout or receive error.
  523. * Timeouts occur when the sink is not connected
  524. */
  525. if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
  526. DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
  527. ret = -EIO;
  528. goto out;
  529. }
  530. /* Timeouts occur when the device isn't connected, so they're
  531. * "normal" -- don't fill the kernel log with these */
  532. if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
  533. DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
  534. ret = -ETIMEDOUT;
  535. goto out;
  536. }
  537. /* Unload any bytes sent back from the other side */
  538. recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
  539. DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
  540. if (recv_bytes > recv_size)
  541. recv_bytes = recv_size;
  542. for (i = 0; i < recv_bytes; i += 4)
  543. unpack_aux(I915_READ(ch_data + i),
  544. recv + i, recv_bytes - i);
  545. ret = recv_bytes;
  546. out:
  547. pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
  548. intel_aux_display_runtime_put(dev_priv);
  549. if (vdd)
  550. edp_panel_vdd_off(intel_dp, false);
  551. return ret;
  552. }
  553. #define BARE_ADDRESS_SIZE 3
  554. #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
  555. static ssize_t
  556. intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
  557. {
  558. struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
  559. uint8_t txbuf[20], rxbuf[20];
  560. size_t txsize, rxsize;
  561. int ret;
  562. txbuf[0] = msg->request << 4;
  563. txbuf[1] = msg->address >> 8;
  564. txbuf[2] = msg->address & 0xff;
  565. txbuf[3] = msg->size - 1;
  566. switch (msg->request & ~DP_AUX_I2C_MOT) {
  567. case DP_AUX_NATIVE_WRITE:
  568. case DP_AUX_I2C_WRITE:
  569. txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
  570. rxsize = 1;
  571. if (WARN_ON(txsize > 20))
  572. return -E2BIG;
  573. memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
  574. ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
  575. if (ret > 0) {
  576. msg->reply = rxbuf[0] >> 4;
  577. /* Return payload size. */
  578. ret = msg->size;
  579. }
  580. break;
  581. case DP_AUX_NATIVE_READ:
  582. case DP_AUX_I2C_READ:
  583. txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
  584. rxsize = msg->size + 1;
  585. if (WARN_ON(rxsize > 20))
  586. return -E2BIG;
  587. ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
  588. if (ret > 0) {
  589. msg->reply = rxbuf[0] >> 4;
  590. /*
  591. * Assume happy day, and copy the data. The caller is
  592. * expected to check msg->reply before touching it.
  593. *
  594. * Return payload size.
  595. */
  596. ret--;
  597. memcpy(msg->buffer, rxbuf + 1, ret);
  598. }
  599. break;
  600. default:
  601. ret = -EINVAL;
  602. break;
  603. }
  604. return ret;
  605. }
  606. static void
  607. intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
  608. {
  609. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  610. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  611. enum port port = intel_dig_port->port;
  612. const char *name = NULL;
  613. int ret;
  614. switch (port) {
  615. case PORT_A:
  616. intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
  617. name = "DPDDC-A";
  618. break;
  619. case PORT_B:
  620. intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
  621. name = "DPDDC-B";
  622. break;
  623. case PORT_C:
  624. intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
  625. name = "DPDDC-C";
  626. break;
  627. case PORT_D:
  628. intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
  629. name = "DPDDC-D";
  630. break;
  631. default:
  632. BUG();
  633. }
  634. if (!HAS_DDI(dev))
  635. intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
  636. intel_dp->aux.name = name;
  637. intel_dp->aux.dev = dev->dev;
  638. intel_dp->aux.transfer = intel_dp_aux_transfer;
  639. DRM_DEBUG_KMS("registering %s bus for %s\n", name,
  640. connector->base.kdev->kobj.name);
  641. ret = drm_dp_aux_register(&intel_dp->aux);
  642. if (ret < 0) {
  643. DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
  644. name, ret);
  645. return;
  646. }
  647. ret = sysfs_create_link(&connector->base.kdev->kobj,
  648. &intel_dp->aux.ddc.dev.kobj,
  649. intel_dp->aux.ddc.dev.kobj.name);
  650. if (ret < 0) {
  651. DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
  652. drm_dp_aux_unregister(&intel_dp->aux);
  653. }
  654. }
  655. static void
  656. intel_dp_connector_unregister(struct intel_connector *intel_connector)
  657. {
  658. struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
  659. sysfs_remove_link(&intel_connector->base.kdev->kobj,
  660. intel_dp->aux.ddc.dev.kobj.name);
  661. intel_connector_unregister(intel_connector);
  662. }
  663. static void
  664. intel_dp_set_clock(struct intel_encoder *encoder,
  665. struct intel_crtc_config *pipe_config, int link_bw)
  666. {
  667. struct drm_device *dev = encoder->base.dev;
  668. const struct dp_link_dpll *divisor = NULL;
  669. int i, count = 0;
  670. if (IS_G4X(dev)) {
  671. divisor = gen4_dpll;
  672. count = ARRAY_SIZE(gen4_dpll);
  673. } else if (IS_HASWELL(dev)) {
  674. /* Haswell has special-purpose DP DDI clocks. */
  675. } else if (HAS_PCH_SPLIT(dev)) {
  676. divisor = pch_dpll;
  677. count = ARRAY_SIZE(pch_dpll);
  678. } else if (IS_CHERRYVIEW(dev)) {
  679. divisor = chv_dpll;
  680. count = ARRAY_SIZE(chv_dpll);
  681. } else if (IS_VALLEYVIEW(dev)) {
  682. divisor = vlv_dpll;
  683. count = ARRAY_SIZE(vlv_dpll);
  684. }
  685. if (divisor && count) {
  686. for (i = 0; i < count; i++) {
  687. if (link_bw == divisor[i].link_bw) {
  688. pipe_config->dpll = divisor[i].dpll;
  689. pipe_config->clock_set = true;
  690. break;
  691. }
  692. }
  693. }
  694. }
  695. static void
  696. intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
  697. {
  698. struct drm_device *dev = crtc->base.dev;
  699. struct drm_i915_private *dev_priv = dev->dev_private;
  700. enum transcoder transcoder = crtc->config.cpu_transcoder;
  701. I915_WRITE(PIPE_DATA_M2(transcoder),
  702. TU_SIZE(m_n->tu) | m_n->gmch_m);
  703. I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
  704. I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
  705. I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
  706. }
  707. bool
  708. intel_dp_compute_config(struct intel_encoder *encoder,
  709. struct intel_crtc_config *pipe_config)
  710. {
  711. struct drm_device *dev = encoder->base.dev;
  712. struct drm_i915_private *dev_priv = dev->dev_private;
  713. struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  714. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  715. enum port port = dp_to_dig_port(intel_dp)->port;
  716. struct intel_crtc *intel_crtc = encoder->new_crtc;
  717. struct intel_connector *intel_connector = intel_dp->attached_connector;
  718. int lane_count, clock;
  719. int min_lane_count = 1;
  720. int max_lane_count = intel_dp_max_lane_count(intel_dp);
  721. /* Conveniently, the link BW constants become indices with a shift...*/
  722. int min_clock = 0;
  723. int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
  724. int bpp, mode_rate;
  725. static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
  726. int link_avail, link_clock;
  727. if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
  728. pipe_config->has_pch_encoder = true;
  729. pipe_config->has_dp_encoder = true;
  730. pipe_config->has_audio = intel_dp->has_audio;
  731. if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
  732. intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
  733. adjusted_mode);
  734. if (!HAS_PCH_SPLIT(dev))
  735. intel_gmch_panel_fitting(intel_crtc, pipe_config,
  736. intel_connector->panel.fitting_mode);
  737. else
  738. intel_pch_panel_fitting(intel_crtc, pipe_config,
  739. intel_connector->panel.fitting_mode);
  740. }
  741. if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
  742. return false;
  743. DRM_DEBUG_KMS("DP link computation with max lane count %i "
  744. "max bw %02x pixel clock %iKHz\n",
  745. max_lane_count, bws[max_clock],
  746. adjusted_mode->crtc_clock);
  747. /* Walk through all bpp values. Luckily they're all nicely spaced with 2
  748. * bpc in between. */
  749. bpp = pipe_config->pipe_bpp;
  750. if (is_edp(intel_dp)) {
  751. if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
  752. DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
  753. dev_priv->vbt.edp_bpp);
  754. bpp = dev_priv->vbt.edp_bpp;
  755. }
  756. if (IS_BROADWELL(dev)) {
  757. /* Yes, it's an ugly hack. */
  758. min_lane_count = max_lane_count;
  759. DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
  760. min_lane_count);
  761. } else if (dev_priv->vbt.edp_lanes) {
  762. min_lane_count = min(dev_priv->vbt.edp_lanes,
  763. max_lane_count);
  764. DRM_DEBUG_KMS("using min %u lanes per VBT\n",
  765. min_lane_count);
  766. }
  767. if (dev_priv->vbt.edp_rate) {
  768. min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
  769. DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
  770. bws[min_clock]);
  771. }
  772. }
  773. for (; bpp >= 6*3; bpp -= 2*3) {
  774. mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
  775. bpp);
  776. for (clock = min_clock; clock <= max_clock; clock++) {
  777. for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
  778. link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
  779. link_avail = intel_dp_max_data_rate(link_clock,
  780. lane_count);
  781. if (mode_rate <= link_avail) {
  782. goto found;
  783. }
  784. }
  785. }
  786. }
  787. return false;
  788. found:
  789. if (intel_dp->color_range_auto) {
  790. /*
  791. * See:
  792. * CEA-861-E - 5.1 Default Encoding Parameters
  793. * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
  794. */
  795. if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
  796. intel_dp->color_range = DP_COLOR_RANGE_16_235;
  797. else
  798. intel_dp->color_range = 0;
  799. }
  800. if (intel_dp->color_range)
  801. pipe_config->limited_color_range = true;
  802. intel_dp->link_bw = bws[clock];
  803. intel_dp->lane_count = lane_count;
  804. pipe_config->pipe_bpp = bpp;
  805. pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
  806. DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
  807. intel_dp->link_bw, intel_dp->lane_count,
  808. pipe_config->port_clock, bpp);
  809. DRM_DEBUG_KMS("DP link bw required %i available %i\n",
  810. mode_rate, link_avail);
  811. intel_link_compute_m_n(bpp, lane_count,
  812. adjusted_mode->crtc_clock,
  813. pipe_config->port_clock,
  814. &pipe_config->dp_m_n);
  815. if (intel_connector->panel.downclock_mode != NULL &&
  816. intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
  817. intel_link_compute_m_n(bpp, lane_count,
  818. intel_connector->panel.downclock_mode->clock,
  819. pipe_config->port_clock,
  820. &pipe_config->dp_m2_n2);
  821. }
  822. intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
  823. return true;
  824. }
  825. static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
  826. {
  827. struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
  828. struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
  829. struct drm_device *dev = crtc->base.dev;
  830. struct drm_i915_private *dev_priv = dev->dev_private;
  831. u32 dpa_ctl;
  832. DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
  833. dpa_ctl = I915_READ(DP_A);
  834. dpa_ctl &= ~DP_PLL_FREQ_MASK;
  835. if (crtc->config.port_clock == 162000) {
  836. /* For a long time we've carried around a ILK-DevA w/a for the
  837. * 160MHz clock. If we're really unlucky, it's still required.
  838. */
  839. DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
  840. dpa_ctl |= DP_PLL_FREQ_160MHZ;
  841. intel_dp->DP |= DP_PLL_FREQ_160MHZ;
  842. } else {
  843. dpa_ctl |= DP_PLL_FREQ_270MHZ;
  844. intel_dp->DP |= DP_PLL_FREQ_270MHZ;
  845. }
  846. I915_WRITE(DP_A, dpa_ctl);
  847. POSTING_READ(DP_A);
  848. udelay(500);
  849. }
  850. static void intel_dp_prepare(struct intel_encoder *encoder)
  851. {
  852. struct drm_device *dev = encoder->base.dev;
  853. struct drm_i915_private *dev_priv = dev->dev_private;
  854. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  855. enum port port = dp_to_dig_port(intel_dp)->port;
  856. struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  857. struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
  858. /*
  859. * There are four kinds of DP registers:
  860. *
  861. * IBX PCH
  862. * SNB CPU
  863. * IVB CPU
  864. * CPT PCH
  865. *
  866. * IBX PCH and CPU are the same for almost everything,
  867. * except that the CPU DP PLL is configured in this
  868. * register
  869. *
  870. * CPT PCH is quite different, having many bits moved
  871. * to the TRANS_DP_CTL register instead. That
  872. * configuration happens (oddly) in ironlake_pch_enable
  873. */
  874. /* Preserve the BIOS-computed detected bit. This is
  875. * supposed to be read-only.
  876. */
  877. intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
  878. /* Handle DP bits in common between all three register formats */
  879. intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
  880. intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
  881. if (crtc->config.has_audio) {
  882. DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
  883. pipe_name(crtc->pipe));
  884. intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
  885. intel_write_eld(&encoder->base, adjusted_mode);
  886. }
  887. /* Split out the IBX/CPU vs CPT settings */
  888. if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
  889. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  890. intel_dp->DP |= DP_SYNC_HS_HIGH;
  891. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  892. intel_dp->DP |= DP_SYNC_VS_HIGH;
  893. intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
  894. if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
  895. intel_dp->DP |= DP_ENHANCED_FRAMING;
  896. intel_dp->DP |= crtc->pipe << 29;
  897. } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
  898. if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
  899. intel_dp->DP |= intel_dp->color_range;
  900. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  901. intel_dp->DP |= DP_SYNC_HS_HIGH;
  902. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  903. intel_dp->DP |= DP_SYNC_VS_HIGH;
  904. intel_dp->DP |= DP_LINK_TRAIN_OFF;
  905. if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
  906. intel_dp->DP |= DP_ENHANCED_FRAMING;
  907. if (!IS_CHERRYVIEW(dev)) {
  908. if (crtc->pipe == 1)
  909. intel_dp->DP |= DP_PIPEB_SELECT;
  910. } else {
  911. intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
  912. }
  913. } else {
  914. intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
  915. }
  916. }
  917. #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
  918. #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
  919. #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
  920. #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
  921. #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
  922. #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
  923. static void wait_panel_status(struct intel_dp *intel_dp,
  924. u32 mask,
  925. u32 value)
  926. {
  927. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  928. struct drm_i915_private *dev_priv = dev->dev_private;
  929. u32 pp_stat_reg, pp_ctrl_reg;
  930. pp_stat_reg = _pp_stat_reg(intel_dp);
  931. pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
  932. DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
  933. mask, value,
  934. I915_READ(pp_stat_reg),
  935. I915_READ(pp_ctrl_reg));
  936. if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
  937. DRM_ERROR("Panel status timeout: status %08x control %08x\n",
  938. I915_READ(pp_stat_reg),
  939. I915_READ(pp_ctrl_reg));
  940. }
  941. DRM_DEBUG_KMS("Wait complete\n");
  942. }
  943. static void wait_panel_on(struct intel_dp *intel_dp)
  944. {
  945. DRM_DEBUG_KMS("Wait for panel power on\n");
  946. wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
  947. }
  948. static void wait_panel_off(struct intel_dp *intel_dp)
  949. {
  950. DRM_DEBUG_KMS("Wait for panel power off time\n");
  951. wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
  952. }
  953. static void wait_panel_power_cycle(struct intel_dp *intel_dp)
  954. {
  955. DRM_DEBUG_KMS("Wait for panel power cycle\n");
  956. /* When we disable the VDD override bit last we have to do the manual
  957. * wait. */
  958. wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
  959. intel_dp->panel_power_cycle_delay);
  960. wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
  961. }
  962. static void wait_backlight_on(struct intel_dp *intel_dp)
  963. {
  964. wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
  965. intel_dp->backlight_on_delay);
  966. }
  967. static void edp_wait_backlight_off(struct intel_dp *intel_dp)
  968. {
  969. wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
  970. intel_dp->backlight_off_delay);
  971. }
  972. /* Read the current pp_control value, unlocking the register if it
  973. * is locked
  974. */
  975. static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
  976. {
  977. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  978. struct drm_i915_private *dev_priv = dev->dev_private;
  979. u32 control;
  980. control = I915_READ(_pp_ctrl_reg(intel_dp));
  981. control &= ~PANEL_UNLOCK_MASK;
  982. control |= PANEL_UNLOCK_REGS;
  983. return control;
  984. }
  985. static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
  986. {
  987. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  988. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  989. struct intel_encoder *intel_encoder = &intel_dig_port->base;
  990. struct drm_i915_private *dev_priv = dev->dev_private;
  991. enum intel_display_power_domain power_domain;
  992. u32 pp;
  993. u32 pp_stat_reg, pp_ctrl_reg;
  994. bool need_to_disable = !intel_dp->want_panel_vdd;
  995. if (!is_edp(intel_dp))
  996. return false;
  997. intel_dp->want_panel_vdd = true;
  998. if (edp_have_panel_vdd(intel_dp))
  999. return need_to_disable;
  1000. power_domain = intel_display_port_power_domain(intel_encoder);
  1001. intel_display_power_get(dev_priv, power_domain);
  1002. DRM_DEBUG_KMS("Turning eDP VDD on\n");
  1003. if (!edp_have_panel_power(intel_dp))
  1004. wait_panel_power_cycle(intel_dp);
  1005. pp = ironlake_get_pp_control(intel_dp);
  1006. pp |= EDP_FORCE_VDD;
  1007. pp_stat_reg = _pp_stat_reg(intel_dp);
  1008. pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
  1009. I915_WRITE(pp_ctrl_reg, pp);
  1010. POSTING_READ(pp_ctrl_reg);
  1011. DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
  1012. I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
  1013. /*
  1014. * If the panel wasn't on, delay before accessing aux channel
  1015. */
  1016. if (!edp_have_panel_power(intel_dp)) {
  1017. DRM_DEBUG_KMS("eDP was not running\n");
  1018. msleep(intel_dp->panel_power_up_delay);
  1019. }
  1020. return need_to_disable;
  1021. }
  1022. void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
  1023. {
  1024. if (is_edp(intel_dp)) {
  1025. bool vdd = _edp_panel_vdd_on(intel_dp);
  1026. WARN(!vdd, "eDP VDD already requested on\n");
  1027. }
  1028. }
  1029. static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
  1030. {
  1031. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1032. struct drm_i915_private *dev_priv = dev->dev_private;
  1033. u32 pp;
  1034. u32 pp_stat_reg, pp_ctrl_reg;
  1035. WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
  1036. if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
  1037. struct intel_digital_port *intel_dig_port =
  1038. dp_to_dig_port(intel_dp);
  1039. struct intel_encoder *intel_encoder = &intel_dig_port->base;
  1040. enum intel_display_power_domain power_domain;
  1041. DRM_DEBUG_KMS("Turning eDP VDD off\n");
  1042. pp = ironlake_get_pp_control(intel_dp);
  1043. pp &= ~EDP_FORCE_VDD;
  1044. pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
  1045. pp_stat_reg = _pp_stat_reg(intel_dp);
  1046. I915_WRITE(pp_ctrl_reg, pp);
  1047. POSTING_READ(pp_ctrl_reg);
  1048. /* Make sure sequencer is idle before allowing subsequent activity */
  1049. DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
  1050. I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
  1051. if ((pp & POWER_TARGET_ON) == 0)
  1052. intel_dp->last_power_cycle = jiffies;
  1053. power_domain = intel_display_port_power_domain(intel_encoder);
  1054. intel_display_power_put(dev_priv, power_domain);
  1055. }
  1056. }
  1057. static void edp_panel_vdd_work(struct work_struct *__work)
  1058. {
  1059. struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
  1060. struct intel_dp, panel_vdd_work);
  1061. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1062. drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
  1063. edp_panel_vdd_off_sync(intel_dp);
  1064. drm_modeset_unlock(&dev->mode_config.connection_mutex);
  1065. }
  1066. static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
  1067. {
  1068. if (!is_edp(intel_dp))
  1069. return;
  1070. WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
  1071. intel_dp->want_panel_vdd = false;
  1072. if (sync) {
  1073. edp_panel_vdd_off_sync(intel_dp);
  1074. } else {
  1075. /*
  1076. * Queue the timer to fire a long
  1077. * time from now (relative to the power down delay)
  1078. * to keep the panel power up across a sequence of operations
  1079. */
  1080. schedule_delayed_work(&intel_dp->panel_vdd_work,
  1081. msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
  1082. }
  1083. }
  1084. void intel_edp_panel_on(struct intel_dp *intel_dp)
  1085. {
  1086. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1087. struct drm_i915_private *dev_priv = dev->dev_private;
  1088. u32 pp;
  1089. u32 pp_ctrl_reg;
  1090. if (!is_edp(intel_dp))
  1091. return;
  1092. DRM_DEBUG_KMS("Turn eDP power on\n");
  1093. if (edp_have_panel_power(intel_dp)) {
  1094. DRM_DEBUG_KMS("eDP power already on\n");
  1095. return;
  1096. }
  1097. wait_panel_power_cycle(intel_dp);
  1098. pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
  1099. pp = ironlake_get_pp_control(intel_dp);
  1100. if (IS_GEN5(dev)) {
  1101. /* ILK workaround: disable reset around power sequence */
  1102. pp &= ~PANEL_POWER_RESET;
  1103. I915_WRITE(pp_ctrl_reg, pp);
  1104. POSTING_READ(pp_ctrl_reg);
  1105. }
  1106. pp |= POWER_TARGET_ON;
  1107. if (!IS_GEN5(dev))
  1108. pp |= PANEL_POWER_RESET;
  1109. I915_WRITE(pp_ctrl_reg, pp);
  1110. POSTING_READ(pp_ctrl_reg);
  1111. wait_panel_on(intel_dp);
  1112. intel_dp->last_power_on = jiffies;
  1113. if (IS_GEN5(dev)) {
  1114. pp |= PANEL_POWER_RESET; /* restore panel reset bit */
  1115. I915_WRITE(pp_ctrl_reg, pp);
  1116. POSTING_READ(pp_ctrl_reg);
  1117. }
  1118. }
  1119. void intel_edp_panel_off(struct intel_dp *intel_dp)
  1120. {
  1121. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1122. struct intel_encoder *intel_encoder = &intel_dig_port->base;
  1123. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1124. struct drm_i915_private *dev_priv = dev->dev_private;
  1125. enum intel_display_power_domain power_domain;
  1126. u32 pp;
  1127. u32 pp_ctrl_reg;
  1128. if (!is_edp(intel_dp))
  1129. return;
  1130. DRM_DEBUG_KMS("Turn eDP power off\n");
  1131. edp_wait_backlight_off(intel_dp);
  1132. WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
  1133. pp = ironlake_get_pp_control(intel_dp);
  1134. /* We need to switch off panel power _and_ force vdd, for otherwise some
  1135. * panels get very unhappy and cease to work. */
  1136. pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
  1137. EDP_BLC_ENABLE);
  1138. pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
  1139. intel_dp->want_panel_vdd = false;
  1140. I915_WRITE(pp_ctrl_reg, pp);
  1141. POSTING_READ(pp_ctrl_reg);
  1142. intel_dp->last_power_cycle = jiffies;
  1143. wait_panel_off(intel_dp);
  1144. /* We got a reference when we enabled the VDD. */
  1145. power_domain = intel_display_port_power_domain(intel_encoder);
  1146. intel_display_power_put(dev_priv, power_domain);
  1147. }
  1148. void intel_edp_backlight_on(struct intel_dp *intel_dp)
  1149. {
  1150. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1151. struct drm_device *dev = intel_dig_port->base.base.dev;
  1152. struct drm_i915_private *dev_priv = dev->dev_private;
  1153. u32 pp;
  1154. u32 pp_ctrl_reg;
  1155. if (!is_edp(intel_dp))
  1156. return;
  1157. DRM_DEBUG_KMS("\n");
  1158. /*
  1159. * If we enable the backlight right away following a panel power
  1160. * on, we may see slight flicker as the panel syncs with the eDP
  1161. * link. So delay a bit to make sure the image is solid before
  1162. * allowing it to appear.
  1163. */
  1164. wait_backlight_on(intel_dp);
  1165. pp = ironlake_get_pp_control(intel_dp);
  1166. pp |= EDP_BLC_ENABLE;
  1167. pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
  1168. I915_WRITE(pp_ctrl_reg, pp);
  1169. POSTING_READ(pp_ctrl_reg);
  1170. intel_panel_enable_backlight(intel_dp->attached_connector);
  1171. }
  1172. void intel_edp_backlight_off(struct intel_dp *intel_dp)
  1173. {
  1174. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1175. struct drm_i915_private *dev_priv = dev->dev_private;
  1176. u32 pp;
  1177. u32 pp_ctrl_reg;
  1178. if (!is_edp(intel_dp))
  1179. return;
  1180. intel_panel_disable_backlight(intel_dp->attached_connector);
  1181. DRM_DEBUG_KMS("\n");
  1182. pp = ironlake_get_pp_control(intel_dp);
  1183. pp &= ~EDP_BLC_ENABLE;
  1184. pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
  1185. I915_WRITE(pp_ctrl_reg, pp);
  1186. POSTING_READ(pp_ctrl_reg);
  1187. intel_dp->last_backlight_off = jiffies;
  1188. }
  1189. static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
  1190. {
  1191. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1192. struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
  1193. struct drm_device *dev = crtc->dev;
  1194. struct drm_i915_private *dev_priv = dev->dev_private;
  1195. u32 dpa_ctl;
  1196. assert_pipe_disabled(dev_priv,
  1197. to_intel_crtc(crtc)->pipe);
  1198. DRM_DEBUG_KMS("\n");
  1199. dpa_ctl = I915_READ(DP_A);
  1200. WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
  1201. WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
  1202. /* We don't adjust intel_dp->DP while tearing down the link, to
  1203. * facilitate link retraining (e.g. after hotplug). Hence clear all
  1204. * enable bits here to ensure that we don't enable too much. */
  1205. intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
  1206. intel_dp->DP |= DP_PLL_ENABLE;
  1207. I915_WRITE(DP_A, intel_dp->DP);
  1208. POSTING_READ(DP_A);
  1209. udelay(200);
  1210. }
  1211. static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
  1212. {
  1213. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1214. struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
  1215. struct drm_device *dev = crtc->dev;
  1216. struct drm_i915_private *dev_priv = dev->dev_private;
  1217. u32 dpa_ctl;
  1218. assert_pipe_disabled(dev_priv,
  1219. to_intel_crtc(crtc)->pipe);
  1220. dpa_ctl = I915_READ(DP_A);
  1221. WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
  1222. "dp pll off, should be on\n");
  1223. WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
  1224. /* We can't rely on the value tracked for the DP register in
  1225. * intel_dp->DP because link_down must not change that (otherwise link
  1226. * re-training will fail. */
  1227. dpa_ctl &= ~DP_PLL_ENABLE;
  1228. I915_WRITE(DP_A, dpa_ctl);
  1229. POSTING_READ(DP_A);
  1230. udelay(200);
  1231. }
  1232. /* If the sink supports it, try to set the power state appropriately */
  1233. void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
  1234. {
  1235. int ret, i;
  1236. /* Should have a valid DPCD by this point */
  1237. if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
  1238. return;
  1239. if (mode != DRM_MODE_DPMS_ON) {
  1240. ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
  1241. DP_SET_POWER_D3);
  1242. if (ret != 1)
  1243. DRM_DEBUG_DRIVER("failed to write sink power state\n");
  1244. } else {
  1245. /*
  1246. * When turning on, we need to retry for 1ms to give the sink
  1247. * time to wake up.
  1248. */
  1249. for (i = 0; i < 3; i++) {
  1250. ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
  1251. DP_SET_POWER_D0);
  1252. if (ret == 1)
  1253. break;
  1254. msleep(1);
  1255. }
  1256. }
  1257. }
  1258. static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
  1259. enum pipe *pipe)
  1260. {
  1261. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1262. enum port port = dp_to_dig_port(intel_dp)->port;
  1263. struct drm_device *dev = encoder->base.dev;
  1264. struct drm_i915_private *dev_priv = dev->dev_private;
  1265. enum intel_display_power_domain power_domain;
  1266. u32 tmp;
  1267. power_domain = intel_display_port_power_domain(encoder);
  1268. if (!intel_display_power_enabled(dev_priv, power_domain))
  1269. return false;
  1270. tmp = I915_READ(intel_dp->output_reg);
  1271. if (!(tmp & DP_PORT_EN))
  1272. return false;
  1273. if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
  1274. *pipe = PORT_TO_PIPE_CPT(tmp);
  1275. } else if (IS_CHERRYVIEW(dev)) {
  1276. *pipe = DP_PORT_TO_PIPE_CHV(tmp);
  1277. } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
  1278. *pipe = PORT_TO_PIPE(tmp);
  1279. } else {
  1280. u32 trans_sel;
  1281. u32 trans_dp;
  1282. int i;
  1283. switch (intel_dp->output_reg) {
  1284. case PCH_DP_B:
  1285. trans_sel = TRANS_DP_PORT_SEL_B;
  1286. break;
  1287. case PCH_DP_C:
  1288. trans_sel = TRANS_DP_PORT_SEL_C;
  1289. break;
  1290. case PCH_DP_D:
  1291. trans_sel = TRANS_DP_PORT_SEL_D;
  1292. break;
  1293. default:
  1294. return true;
  1295. }
  1296. for_each_pipe(i) {
  1297. trans_dp = I915_READ(TRANS_DP_CTL(i));
  1298. if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
  1299. *pipe = i;
  1300. return true;
  1301. }
  1302. }
  1303. DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
  1304. intel_dp->output_reg);
  1305. }
  1306. return true;
  1307. }
  1308. static void intel_dp_get_config(struct intel_encoder *encoder,
  1309. struct intel_crtc_config *pipe_config)
  1310. {
  1311. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1312. u32 tmp, flags = 0;
  1313. struct drm_device *dev = encoder->base.dev;
  1314. struct drm_i915_private *dev_priv = dev->dev_private;
  1315. enum port port = dp_to_dig_port(intel_dp)->port;
  1316. struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  1317. int dotclock;
  1318. tmp = I915_READ(intel_dp->output_reg);
  1319. if (tmp & DP_AUDIO_OUTPUT_ENABLE)
  1320. pipe_config->has_audio = true;
  1321. if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
  1322. if (tmp & DP_SYNC_HS_HIGH)
  1323. flags |= DRM_MODE_FLAG_PHSYNC;
  1324. else
  1325. flags |= DRM_MODE_FLAG_NHSYNC;
  1326. if (tmp & DP_SYNC_VS_HIGH)
  1327. flags |= DRM_MODE_FLAG_PVSYNC;
  1328. else
  1329. flags |= DRM_MODE_FLAG_NVSYNC;
  1330. } else {
  1331. tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
  1332. if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
  1333. flags |= DRM_MODE_FLAG_PHSYNC;
  1334. else
  1335. flags |= DRM_MODE_FLAG_NHSYNC;
  1336. if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
  1337. flags |= DRM_MODE_FLAG_PVSYNC;
  1338. else
  1339. flags |= DRM_MODE_FLAG_NVSYNC;
  1340. }
  1341. pipe_config->adjusted_mode.flags |= flags;
  1342. pipe_config->has_dp_encoder = true;
  1343. intel_dp_get_m_n(crtc, pipe_config);
  1344. if (port == PORT_A) {
  1345. if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
  1346. pipe_config->port_clock = 162000;
  1347. else
  1348. pipe_config->port_clock = 270000;
  1349. }
  1350. dotclock = intel_dotclock_calculate(pipe_config->port_clock,
  1351. &pipe_config->dp_m_n);
  1352. if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
  1353. ironlake_check_encoder_dotclock(pipe_config, dotclock);
  1354. pipe_config->adjusted_mode.crtc_clock = dotclock;
  1355. if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
  1356. pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
  1357. /*
  1358. * This is a big fat ugly hack.
  1359. *
  1360. * Some machines in UEFI boot mode provide us a VBT that has 18
  1361. * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
  1362. * unknown we fail to light up. Yet the same BIOS boots up with
  1363. * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
  1364. * max, not what it tells us to use.
  1365. *
  1366. * Note: This will still be broken if the eDP panel is not lit
  1367. * up by the BIOS, and thus we can't get the mode at module
  1368. * load.
  1369. */
  1370. DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
  1371. pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
  1372. dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
  1373. }
  1374. }
  1375. static bool is_edp_psr(struct drm_device *dev)
  1376. {
  1377. struct drm_i915_private *dev_priv = dev->dev_private;
  1378. return dev_priv->psr.sink_support;
  1379. }
  1380. static bool intel_edp_is_psr_enabled(struct drm_device *dev)
  1381. {
  1382. struct drm_i915_private *dev_priv = dev->dev_private;
  1383. if (!HAS_PSR(dev))
  1384. return false;
  1385. return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
  1386. }
  1387. static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
  1388. struct edp_vsc_psr *vsc_psr)
  1389. {
  1390. struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
  1391. struct drm_device *dev = dig_port->base.base.dev;
  1392. struct drm_i915_private *dev_priv = dev->dev_private;
  1393. struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
  1394. u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
  1395. u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
  1396. uint32_t *data = (uint32_t *) vsc_psr;
  1397. unsigned int i;
  1398. /* As per BSPec (Pipe Video Data Island Packet), we need to disable
  1399. the video DIP being updated before program video DIP data buffer
  1400. registers for DIP being updated. */
  1401. I915_WRITE(ctl_reg, 0);
  1402. POSTING_READ(ctl_reg);
  1403. for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
  1404. if (i < sizeof(struct edp_vsc_psr))
  1405. I915_WRITE(data_reg + i, *data++);
  1406. else
  1407. I915_WRITE(data_reg + i, 0);
  1408. }
  1409. I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
  1410. POSTING_READ(ctl_reg);
  1411. }
  1412. static void intel_edp_psr_setup(struct intel_dp *intel_dp)
  1413. {
  1414. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1415. struct drm_i915_private *dev_priv = dev->dev_private;
  1416. struct edp_vsc_psr psr_vsc;
  1417. if (intel_dp->psr_setup_done)
  1418. return;
  1419. /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
  1420. memset(&psr_vsc, 0, sizeof(psr_vsc));
  1421. psr_vsc.sdp_header.HB0 = 0;
  1422. psr_vsc.sdp_header.HB1 = 0x7;
  1423. psr_vsc.sdp_header.HB2 = 0x2;
  1424. psr_vsc.sdp_header.HB3 = 0x8;
  1425. intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
  1426. /* Avoid continuous PSR exit by masking memup and hpd */
  1427. I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
  1428. EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
  1429. intel_dp->psr_setup_done = true;
  1430. }
  1431. static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
  1432. {
  1433. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1434. struct drm_i915_private *dev_priv = dev->dev_private;
  1435. uint32_t aux_clock_divider;
  1436. int precharge = 0x3;
  1437. int msg_size = 5; /* Header(4) + Message(1) */
  1438. aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
  1439. /* Enable PSR in sink */
  1440. if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
  1441. drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
  1442. DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
  1443. else
  1444. drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
  1445. DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
  1446. /* Setup AUX registers */
  1447. I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
  1448. I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
  1449. I915_WRITE(EDP_PSR_AUX_CTL(dev),
  1450. DP_AUX_CH_CTL_TIME_OUT_400us |
  1451. (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
  1452. (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
  1453. (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
  1454. }
  1455. static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
  1456. {
  1457. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1458. struct drm_i915_private *dev_priv = dev->dev_private;
  1459. uint32_t max_sleep_time = 0x1f;
  1460. uint32_t idle_frames = 1;
  1461. uint32_t val = 0x0;
  1462. const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
  1463. if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
  1464. val |= EDP_PSR_LINK_STANDBY;
  1465. val |= EDP_PSR_TP2_TP3_TIME_0us;
  1466. val |= EDP_PSR_TP1_TIME_0us;
  1467. val |= EDP_PSR_SKIP_AUX_EXIT;
  1468. } else
  1469. val |= EDP_PSR_LINK_DISABLE;
  1470. I915_WRITE(EDP_PSR_CTL(dev), val |
  1471. (IS_BROADWELL(dev) ? 0 : link_entry_time) |
  1472. max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
  1473. idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
  1474. EDP_PSR_ENABLE);
  1475. }
  1476. static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
  1477. {
  1478. struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
  1479. struct drm_device *dev = dig_port->base.base.dev;
  1480. struct drm_i915_private *dev_priv = dev->dev_private;
  1481. struct drm_crtc *crtc = dig_port->base.base.crtc;
  1482. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1483. struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
  1484. struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
  1485. dev_priv->psr.source_ok = false;
  1486. if (!HAS_PSR(dev)) {
  1487. DRM_DEBUG_KMS("PSR not supported on this platform\n");
  1488. return false;
  1489. }
  1490. if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
  1491. (dig_port->port != PORT_A)) {
  1492. DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
  1493. return false;
  1494. }
  1495. if (!i915.enable_psr) {
  1496. DRM_DEBUG_KMS("PSR disable by flag\n");
  1497. return false;
  1498. }
  1499. crtc = dig_port->base.base.crtc;
  1500. if (crtc == NULL) {
  1501. DRM_DEBUG_KMS("crtc not active for PSR\n");
  1502. return false;
  1503. }
  1504. intel_crtc = to_intel_crtc(crtc);
  1505. if (!intel_crtc_active(crtc)) {
  1506. DRM_DEBUG_KMS("crtc not active for PSR\n");
  1507. return false;
  1508. }
  1509. obj = to_intel_framebuffer(crtc->primary->fb)->obj;
  1510. if (obj->tiling_mode != I915_TILING_X ||
  1511. obj->fence_reg == I915_FENCE_REG_NONE) {
  1512. DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
  1513. return false;
  1514. }
  1515. if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
  1516. DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
  1517. return false;
  1518. }
  1519. if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
  1520. S3D_ENABLE) {
  1521. DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
  1522. return false;
  1523. }
  1524. if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
  1525. DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
  1526. return false;
  1527. }
  1528. dev_priv->psr.source_ok = true;
  1529. return true;
  1530. }
  1531. static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
  1532. {
  1533. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1534. if (!intel_edp_psr_match_conditions(intel_dp) ||
  1535. intel_edp_is_psr_enabled(dev))
  1536. return;
  1537. /* Setup PSR once */
  1538. intel_edp_psr_setup(intel_dp);
  1539. /* Enable PSR on the panel */
  1540. intel_edp_psr_enable_sink(intel_dp);
  1541. /* Enable PSR on the host */
  1542. intel_edp_psr_enable_source(intel_dp);
  1543. }
  1544. void intel_edp_psr_enable(struct intel_dp *intel_dp)
  1545. {
  1546. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1547. if (intel_edp_psr_match_conditions(intel_dp) &&
  1548. !intel_edp_is_psr_enabled(dev))
  1549. intel_edp_psr_do_enable(intel_dp);
  1550. }
  1551. void intel_edp_psr_disable(struct intel_dp *intel_dp)
  1552. {
  1553. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1554. struct drm_i915_private *dev_priv = dev->dev_private;
  1555. if (!intel_edp_is_psr_enabled(dev))
  1556. return;
  1557. I915_WRITE(EDP_PSR_CTL(dev),
  1558. I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
  1559. /* Wait till PSR is idle */
  1560. if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
  1561. EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
  1562. DRM_ERROR("Timed out waiting for PSR Idle State\n");
  1563. }
  1564. void intel_edp_psr_update(struct drm_device *dev)
  1565. {
  1566. struct intel_encoder *encoder;
  1567. struct intel_dp *intel_dp = NULL;
  1568. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
  1569. if (encoder->type == INTEL_OUTPUT_EDP) {
  1570. intel_dp = enc_to_intel_dp(&encoder->base);
  1571. if (!is_edp_psr(dev))
  1572. return;
  1573. if (!intel_edp_psr_match_conditions(intel_dp))
  1574. intel_edp_psr_disable(intel_dp);
  1575. else
  1576. if (!intel_edp_is_psr_enabled(dev))
  1577. intel_edp_psr_do_enable(intel_dp);
  1578. }
  1579. }
  1580. static void intel_disable_dp(struct intel_encoder *encoder)
  1581. {
  1582. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1583. enum port port = dp_to_dig_port(intel_dp)->port;
  1584. struct drm_device *dev = encoder->base.dev;
  1585. /* Make sure the panel is off before trying to change the mode. But also
  1586. * ensure that we have vdd while we switch off the panel. */
  1587. intel_edp_panel_vdd_on(intel_dp);
  1588. intel_edp_backlight_off(intel_dp);
  1589. intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
  1590. intel_edp_panel_off(intel_dp);
  1591. /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
  1592. if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
  1593. intel_dp_link_down(intel_dp);
  1594. }
  1595. static void g4x_post_disable_dp(struct intel_encoder *encoder)
  1596. {
  1597. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1598. enum port port = dp_to_dig_port(intel_dp)->port;
  1599. if (port != PORT_A)
  1600. return;
  1601. intel_dp_link_down(intel_dp);
  1602. ironlake_edp_pll_off(intel_dp);
  1603. }
  1604. static void vlv_post_disable_dp(struct intel_encoder *encoder)
  1605. {
  1606. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1607. intel_dp_link_down(intel_dp);
  1608. }
  1609. static void chv_post_disable_dp(struct intel_encoder *encoder)
  1610. {
  1611. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1612. struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
  1613. struct drm_device *dev = encoder->base.dev;
  1614. struct drm_i915_private *dev_priv = dev->dev_private;
  1615. struct intel_crtc *intel_crtc =
  1616. to_intel_crtc(encoder->base.crtc);
  1617. enum dpio_channel ch = vlv_dport_to_channel(dport);
  1618. enum pipe pipe = intel_crtc->pipe;
  1619. u32 val;
  1620. intel_dp_link_down(intel_dp);
  1621. mutex_lock(&dev_priv->dpio_lock);
  1622. /* Propagate soft reset to data lane reset */
  1623. val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
  1624. val |= CHV_PCS_REQ_SOFTRESET_EN;
  1625. vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
  1626. val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
  1627. val |= CHV_PCS_REQ_SOFTRESET_EN;
  1628. vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
  1629. val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
  1630. val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
  1631. vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
  1632. val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
  1633. val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
  1634. vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
  1635. mutex_unlock(&dev_priv->dpio_lock);
  1636. }
  1637. static void intel_enable_dp(struct intel_encoder *encoder)
  1638. {
  1639. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1640. struct drm_device *dev = encoder->base.dev;
  1641. struct drm_i915_private *dev_priv = dev->dev_private;
  1642. uint32_t dp_reg = I915_READ(intel_dp->output_reg);
  1643. if (WARN_ON(dp_reg & DP_PORT_EN))
  1644. return;
  1645. intel_edp_panel_vdd_on(intel_dp);
  1646. intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
  1647. intel_dp_start_link_train(intel_dp);
  1648. intel_edp_panel_on(intel_dp);
  1649. edp_panel_vdd_off(intel_dp, true);
  1650. intel_dp_complete_link_train(intel_dp);
  1651. intel_dp_stop_link_train(intel_dp);
  1652. }
  1653. static void g4x_enable_dp(struct intel_encoder *encoder)
  1654. {
  1655. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1656. intel_enable_dp(encoder);
  1657. intel_edp_backlight_on(intel_dp);
  1658. }
  1659. static void vlv_enable_dp(struct intel_encoder *encoder)
  1660. {
  1661. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1662. intel_edp_backlight_on(intel_dp);
  1663. }
  1664. static void g4x_pre_enable_dp(struct intel_encoder *encoder)
  1665. {
  1666. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1667. struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
  1668. intel_dp_prepare(encoder);
  1669. /* Only ilk+ has port A */
  1670. if (dport->port == PORT_A) {
  1671. ironlake_set_pll_cpu_edp(intel_dp);
  1672. ironlake_edp_pll_on(intel_dp);
  1673. }
  1674. }
  1675. static void vlv_pre_enable_dp(struct intel_encoder *encoder)
  1676. {
  1677. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1678. struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
  1679. struct drm_device *dev = encoder->base.dev;
  1680. struct drm_i915_private *dev_priv = dev->dev_private;
  1681. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  1682. enum dpio_channel port = vlv_dport_to_channel(dport);
  1683. int pipe = intel_crtc->pipe;
  1684. struct edp_power_seq power_seq;
  1685. u32 val;
  1686. mutex_lock(&dev_priv->dpio_lock);
  1687. val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
  1688. val = 0;
  1689. if (pipe)
  1690. val |= (1<<21);
  1691. else
  1692. val &= ~(1<<21);
  1693. val |= 0x001000c4;
  1694. vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
  1695. vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
  1696. vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
  1697. mutex_unlock(&dev_priv->dpio_lock);
  1698. if (is_edp(intel_dp)) {
  1699. /* init power sequencer on this pipe and port */
  1700. intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
  1701. intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
  1702. &power_seq);
  1703. }
  1704. intel_enable_dp(encoder);
  1705. vlv_wait_port_ready(dev_priv, dport);
  1706. }
  1707. static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
  1708. {
  1709. struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
  1710. struct drm_device *dev = encoder->base.dev;
  1711. struct drm_i915_private *dev_priv = dev->dev_private;
  1712. struct intel_crtc *intel_crtc =
  1713. to_intel_crtc(encoder->base.crtc);
  1714. enum dpio_channel port = vlv_dport_to_channel(dport);
  1715. int pipe = intel_crtc->pipe;
  1716. intel_dp_prepare(encoder);
  1717. /* Program Tx lane resets to default */
  1718. mutex_lock(&dev_priv->dpio_lock);
  1719. vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
  1720. DPIO_PCS_TX_LANE2_RESET |
  1721. DPIO_PCS_TX_LANE1_RESET);
  1722. vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
  1723. DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
  1724. DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
  1725. (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
  1726. DPIO_PCS_CLK_SOFT_RESET);
  1727. /* Fix up inter-pair skew failure */
  1728. vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
  1729. vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
  1730. vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
  1731. mutex_unlock(&dev_priv->dpio_lock);
  1732. }
  1733. static void chv_pre_enable_dp(struct intel_encoder *encoder)
  1734. {
  1735. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1736. struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
  1737. struct drm_device *dev = encoder->base.dev;
  1738. struct drm_i915_private *dev_priv = dev->dev_private;
  1739. struct edp_power_seq power_seq;
  1740. struct intel_crtc *intel_crtc =
  1741. to_intel_crtc(encoder->base.crtc);
  1742. enum dpio_channel ch = vlv_dport_to_channel(dport);
  1743. int pipe = intel_crtc->pipe;
  1744. int data, i;
  1745. u32 val;
  1746. mutex_lock(&dev_priv->dpio_lock);
  1747. /* Deassert soft data lane reset*/
  1748. val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
  1749. val |= CHV_PCS_REQ_SOFTRESET_EN;
  1750. vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
  1751. val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
  1752. val |= CHV_PCS_REQ_SOFTRESET_EN;
  1753. vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
  1754. val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
  1755. val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
  1756. vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
  1757. val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
  1758. val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
  1759. vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
  1760. /* Program Tx lane latency optimal setting*/
  1761. for (i = 0; i < 4; i++) {
  1762. /* Set the latency optimal bit */
  1763. data = (i == 1) ? 0x0 : 0x6;
  1764. vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
  1765. data << DPIO_FRC_LATENCY_SHFIT);
  1766. /* Set the upar bit */
  1767. data = (i == 1) ? 0x0 : 0x1;
  1768. vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
  1769. data << DPIO_UPAR_SHIFT);
  1770. }
  1771. /* Data lane stagger programming */
  1772. /* FIXME: Fix up value only after power analysis */
  1773. mutex_unlock(&dev_priv->dpio_lock);
  1774. if (is_edp(intel_dp)) {
  1775. /* init power sequencer on this pipe and port */
  1776. intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
  1777. intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
  1778. &power_seq);
  1779. }
  1780. intel_enable_dp(encoder);
  1781. vlv_wait_port_ready(dev_priv, dport);
  1782. }
  1783. /*
  1784. * Native read with retry for link status and receiver capability reads for
  1785. * cases where the sink may still be asleep.
  1786. *
  1787. * Sinks are *supposed* to come up within 1ms from an off state, but we're also
  1788. * supposed to retry 3 times per the spec.
  1789. */
  1790. static ssize_t
  1791. intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
  1792. void *buffer, size_t size)
  1793. {
  1794. ssize_t ret;
  1795. int i;
  1796. for (i = 0; i < 3; i++) {
  1797. ret = drm_dp_dpcd_read(aux, offset, buffer, size);
  1798. if (ret == size)
  1799. return ret;
  1800. msleep(1);
  1801. }
  1802. return ret;
  1803. }
  1804. /*
  1805. * Fetch AUX CH registers 0x202 - 0x207 which contain
  1806. * link status information
  1807. */
  1808. static bool
  1809. intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
  1810. {
  1811. return intel_dp_dpcd_read_wake(&intel_dp->aux,
  1812. DP_LANE0_1_STATUS,
  1813. link_status,
  1814. DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
  1815. }
  1816. /*
  1817. * These are source-specific values; current Intel hardware supports
  1818. * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
  1819. */
  1820. static uint8_t
  1821. intel_dp_voltage_max(struct intel_dp *intel_dp)
  1822. {
  1823. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1824. enum port port = dp_to_dig_port(intel_dp)->port;
  1825. if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
  1826. return DP_TRAIN_VOLTAGE_SWING_1200;
  1827. else if (IS_GEN7(dev) && port == PORT_A)
  1828. return DP_TRAIN_VOLTAGE_SWING_800;
  1829. else if (HAS_PCH_CPT(dev) && port != PORT_A)
  1830. return DP_TRAIN_VOLTAGE_SWING_1200;
  1831. else
  1832. return DP_TRAIN_VOLTAGE_SWING_800;
  1833. }
  1834. static uint8_t
  1835. intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
  1836. {
  1837. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1838. enum port port = dp_to_dig_port(intel_dp)->port;
  1839. if (IS_BROADWELL(dev)) {
  1840. switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1841. case DP_TRAIN_VOLTAGE_SWING_400:
  1842. case DP_TRAIN_VOLTAGE_SWING_600:
  1843. return DP_TRAIN_PRE_EMPHASIS_6;
  1844. case DP_TRAIN_VOLTAGE_SWING_800:
  1845. return DP_TRAIN_PRE_EMPHASIS_3_5;
  1846. case DP_TRAIN_VOLTAGE_SWING_1200:
  1847. default:
  1848. return DP_TRAIN_PRE_EMPHASIS_0;
  1849. }
  1850. } else if (IS_HASWELL(dev)) {
  1851. switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1852. case DP_TRAIN_VOLTAGE_SWING_400:
  1853. return DP_TRAIN_PRE_EMPHASIS_9_5;
  1854. case DP_TRAIN_VOLTAGE_SWING_600:
  1855. return DP_TRAIN_PRE_EMPHASIS_6;
  1856. case DP_TRAIN_VOLTAGE_SWING_800:
  1857. return DP_TRAIN_PRE_EMPHASIS_3_5;
  1858. case DP_TRAIN_VOLTAGE_SWING_1200:
  1859. default:
  1860. return DP_TRAIN_PRE_EMPHASIS_0;
  1861. }
  1862. } else if (IS_VALLEYVIEW(dev)) {
  1863. switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1864. case DP_TRAIN_VOLTAGE_SWING_400:
  1865. return DP_TRAIN_PRE_EMPHASIS_9_5;
  1866. case DP_TRAIN_VOLTAGE_SWING_600:
  1867. return DP_TRAIN_PRE_EMPHASIS_6;
  1868. case DP_TRAIN_VOLTAGE_SWING_800:
  1869. return DP_TRAIN_PRE_EMPHASIS_3_5;
  1870. case DP_TRAIN_VOLTAGE_SWING_1200:
  1871. default:
  1872. return DP_TRAIN_PRE_EMPHASIS_0;
  1873. }
  1874. } else if (IS_GEN7(dev) && port == PORT_A) {
  1875. switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1876. case DP_TRAIN_VOLTAGE_SWING_400:
  1877. return DP_TRAIN_PRE_EMPHASIS_6;
  1878. case DP_TRAIN_VOLTAGE_SWING_600:
  1879. case DP_TRAIN_VOLTAGE_SWING_800:
  1880. return DP_TRAIN_PRE_EMPHASIS_3_5;
  1881. default:
  1882. return DP_TRAIN_PRE_EMPHASIS_0;
  1883. }
  1884. } else {
  1885. switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1886. case DP_TRAIN_VOLTAGE_SWING_400:
  1887. return DP_TRAIN_PRE_EMPHASIS_6;
  1888. case DP_TRAIN_VOLTAGE_SWING_600:
  1889. return DP_TRAIN_PRE_EMPHASIS_6;
  1890. case DP_TRAIN_VOLTAGE_SWING_800:
  1891. return DP_TRAIN_PRE_EMPHASIS_3_5;
  1892. case DP_TRAIN_VOLTAGE_SWING_1200:
  1893. default:
  1894. return DP_TRAIN_PRE_EMPHASIS_0;
  1895. }
  1896. }
  1897. }
  1898. static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
  1899. {
  1900. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1901. struct drm_i915_private *dev_priv = dev->dev_private;
  1902. struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
  1903. struct intel_crtc *intel_crtc =
  1904. to_intel_crtc(dport->base.base.crtc);
  1905. unsigned long demph_reg_value, preemph_reg_value,
  1906. uniqtranscale_reg_value;
  1907. uint8_t train_set = intel_dp->train_set[0];
  1908. enum dpio_channel port = vlv_dport_to_channel(dport);
  1909. int pipe = intel_crtc->pipe;
  1910. switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
  1911. case DP_TRAIN_PRE_EMPHASIS_0:
  1912. preemph_reg_value = 0x0004000;
  1913. switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1914. case DP_TRAIN_VOLTAGE_SWING_400:
  1915. demph_reg_value = 0x2B405555;
  1916. uniqtranscale_reg_value = 0x552AB83A;
  1917. break;
  1918. case DP_TRAIN_VOLTAGE_SWING_600:
  1919. demph_reg_value = 0x2B404040;
  1920. uniqtranscale_reg_value = 0x5548B83A;
  1921. break;
  1922. case DP_TRAIN_VOLTAGE_SWING_800:
  1923. demph_reg_value = 0x2B245555;
  1924. uniqtranscale_reg_value = 0x5560B83A;
  1925. break;
  1926. case DP_TRAIN_VOLTAGE_SWING_1200:
  1927. demph_reg_value = 0x2B405555;
  1928. uniqtranscale_reg_value = 0x5598DA3A;
  1929. break;
  1930. default:
  1931. return 0;
  1932. }
  1933. break;
  1934. case DP_TRAIN_PRE_EMPHASIS_3_5:
  1935. preemph_reg_value = 0x0002000;
  1936. switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1937. case DP_TRAIN_VOLTAGE_SWING_400:
  1938. demph_reg_value = 0x2B404040;
  1939. uniqtranscale_reg_value = 0x5552B83A;
  1940. break;
  1941. case DP_TRAIN_VOLTAGE_SWING_600:
  1942. demph_reg_value = 0x2B404848;
  1943. uniqtranscale_reg_value = 0x5580B83A;
  1944. break;
  1945. case DP_TRAIN_VOLTAGE_SWING_800:
  1946. demph_reg_value = 0x2B404040;
  1947. uniqtranscale_reg_value = 0x55ADDA3A;
  1948. break;
  1949. default:
  1950. return 0;
  1951. }
  1952. break;
  1953. case DP_TRAIN_PRE_EMPHASIS_6:
  1954. preemph_reg_value = 0x0000000;
  1955. switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1956. case DP_TRAIN_VOLTAGE_SWING_400:
  1957. demph_reg_value = 0x2B305555;
  1958. uniqtranscale_reg_value = 0x5570B83A;
  1959. break;
  1960. case DP_TRAIN_VOLTAGE_SWING_600:
  1961. demph_reg_value = 0x2B2B4040;
  1962. uniqtranscale_reg_value = 0x55ADDA3A;
  1963. break;
  1964. default:
  1965. return 0;
  1966. }
  1967. break;
  1968. case DP_TRAIN_PRE_EMPHASIS_9_5:
  1969. preemph_reg_value = 0x0006000;
  1970. switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1971. case DP_TRAIN_VOLTAGE_SWING_400:
  1972. demph_reg_value = 0x1B405555;
  1973. uniqtranscale_reg_value = 0x55ADDA3A;
  1974. break;
  1975. default:
  1976. return 0;
  1977. }
  1978. break;
  1979. default:
  1980. return 0;
  1981. }
  1982. mutex_lock(&dev_priv->dpio_lock);
  1983. vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
  1984. vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
  1985. vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
  1986. uniqtranscale_reg_value);
  1987. vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
  1988. vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
  1989. vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
  1990. vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
  1991. mutex_unlock(&dev_priv->dpio_lock);
  1992. return 0;
  1993. }
  1994. static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
  1995. {
  1996. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1997. struct drm_i915_private *dev_priv = dev->dev_private;
  1998. struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
  1999. struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
  2000. u32 deemph_reg_value, margin_reg_value, val;
  2001. uint8_t train_set = intel_dp->train_set[0];
  2002. enum dpio_channel ch = vlv_dport_to_channel(dport);
  2003. enum pipe pipe = intel_crtc->pipe;
  2004. int i;
  2005. switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
  2006. case DP_TRAIN_PRE_EMPHASIS_0:
  2007. switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
  2008. case DP_TRAIN_VOLTAGE_SWING_400:
  2009. deemph_reg_value = 128;
  2010. margin_reg_value = 52;
  2011. break;
  2012. case DP_TRAIN_VOLTAGE_SWING_600:
  2013. deemph_reg_value = 128;
  2014. margin_reg_value = 77;
  2015. break;
  2016. case DP_TRAIN_VOLTAGE_SWING_800:
  2017. deemph_reg_value = 128;
  2018. margin_reg_value = 102;
  2019. break;
  2020. case DP_TRAIN_VOLTAGE_SWING_1200:
  2021. deemph_reg_value = 128;
  2022. margin_reg_value = 154;
  2023. /* FIXME extra to set for 1200 */
  2024. break;
  2025. default:
  2026. return 0;
  2027. }
  2028. break;
  2029. case DP_TRAIN_PRE_EMPHASIS_3_5:
  2030. switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
  2031. case DP_TRAIN_VOLTAGE_SWING_400:
  2032. deemph_reg_value = 85;
  2033. margin_reg_value = 78;
  2034. break;
  2035. case DP_TRAIN_VOLTAGE_SWING_600:
  2036. deemph_reg_value = 85;
  2037. margin_reg_value = 116;
  2038. break;
  2039. case DP_TRAIN_VOLTAGE_SWING_800:
  2040. deemph_reg_value = 85;
  2041. margin_reg_value = 154;
  2042. break;
  2043. default:
  2044. return 0;
  2045. }
  2046. break;
  2047. case DP_TRAIN_PRE_EMPHASIS_6:
  2048. switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
  2049. case DP_TRAIN_VOLTAGE_SWING_400:
  2050. deemph_reg_value = 64;
  2051. margin_reg_value = 104;
  2052. break;
  2053. case DP_TRAIN_VOLTAGE_SWING_600:
  2054. deemph_reg_value = 64;
  2055. margin_reg_value = 154;
  2056. break;
  2057. default:
  2058. return 0;
  2059. }
  2060. break;
  2061. case DP_TRAIN_PRE_EMPHASIS_9_5:
  2062. switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
  2063. case DP_TRAIN_VOLTAGE_SWING_400:
  2064. deemph_reg_value = 43;
  2065. margin_reg_value = 154;
  2066. break;
  2067. default:
  2068. return 0;
  2069. }
  2070. break;
  2071. default:
  2072. return 0;
  2073. }
  2074. mutex_lock(&dev_priv->dpio_lock);
  2075. /* Clear calc init */
  2076. val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
  2077. val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
  2078. vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
  2079. val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
  2080. val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
  2081. vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
  2082. /* Program swing deemph */
  2083. for (i = 0; i < 4; i++) {
  2084. val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
  2085. val &= ~DPIO_SWING_DEEMPH9P5_MASK;
  2086. val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
  2087. vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
  2088. }
  2089. /* Program swing margin */
  2090. for (i = 0; i < 4; i++) {
  2091. val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
  2092. val &= ~DPIO_SWING_MARGIN_MASK;
  2093. val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
  2094. vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
  2095. }
  2096. /* Disable unique transition scale */
  2097. for (i = 0; i < 4; i++) {
  2098. val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
  2099. val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
  2100. vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
  2101. }
  2102. if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
  2103. == DP_TRAIN_PRE_EMPHASIS_0) &&
  2104. ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
  2105. == DP_TRAIN_VOLTAGE_SWING_1200)) {
  2106. /*
  2107. * The document said it needs to set bit 27 for ch0 and bit 26
  2108. * for ch1. Might be a typo in the doc.
  2109. * For now, for this unique transition scale selection, set bit
  2110. * 27 for ch0 and ch1.
  2111. */
  2112. for (i = 0; i < 4; i++) {
  2113. val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
  2114. val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
  2115. vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
  2116. }
  2117. for (i = 0; i < 4; i++) {
  2118. val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
  2119. val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
  2120. val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
  2121. vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
  2122. }
  2123. }
  2124. /* Start swing calculation */
  2125. val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
  2126. val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
  2127. vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
  2128. val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
  2129. val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
  2130. vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
  2131. /* LRC Bypass */
  2132. val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
  2133. val |= DPIO_LRC_BYPASS;
  2134. vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
  2135. mutex_unlock(&dev_priv->dpio_lock);
  2136. return 0;
  2137. }
  2138. static void
  2139. intel_get_adjust_train(struct intel_dp *intel_dp,
  2140. const uint8_t link_status[DP_LINK_STATUS_SIZE])
  2141. {
  2142. uint8_t v = 0;
  2143. uint8_t p = 0;
  2144. int lane;
  2145. uint8_t voltage_max;
  2146. uint8_t preemph_max;
  2147. for (lane = 0; lane < intel_dp->lane_count; lane++) {
  2148. uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
  2149. uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
  2150. if (this_v > v)
  2151. v = this_v;
  2152. if (this_p > p)
  2153. p = this_p;
  2154. }
  2155. voltage_max = intel_dp_voltage_max(intel_dp);
  2156. if (v >= voltage_max)
  2157. v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
  2158. preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
  2159. if (p >= preemph_max)
  2160. p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  2161. for (lane = 0; lane < 4; lane++)
  2162. intel_dp->train_set[lane] = v | p;
  2163. }
  2164. static uint32_t
  2165. intel_gen4_signal_levels(uint8_t train_set)
  2166. {
  2167. uint32_t signal_levels = 0;
  2168. switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
  2169. case DP_TRAIN_VOLTAGE_SWING_400:
  2170. default:
  2171. signal_levels |= DP_VOLTAGE_0_4;
  2172. break;
  2173. case DP_TRAIN_VOLTAGE_SWING_600:
  2174. signal_levels |= DP_VOLTAGE_0_6;
  2175. break;
  2176. case DP_TRAIN_VOLTAGE_SWING_800:
  2177. signal_levels |= DP_VOLTAGE_0_8;
  2178. break;
  2179. case DP_TRAIN_VOLTAGE_SWING_1200:
  2180. signal_levels |= DP_VOLTAGE_1_2;
  2181. break;
  2182. }
  2183. switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
  2184. case DP_TRAIN_PRE_EMPHASIS_0:
  2185. default:
  2186. signal_levels |= DP_PRE_EMPHASIS_0;
  2187. break;
  2188. case DP_TRAIN_PRE_EMPHASIS_3_5:
  2189. signal_levels |= DP_PRE_EMPHASIS_3_5;
  2190. break;
  2191. case DP_TRAIN_PRE_EMPHASIS_6:
  2192. signal_levels |= DP_PRE_EMPHASIS_6;
  2193. break;
  2194. case DP_TRAIN_PRE_EMPHASIS_9_5:
  2195. signal_levels |= DP_PRE_EMPHASIS_9_5;
  2196. break;
  2197. }
  2198. return signal_levels;
  2199. }
  2200. /* Gen6's DP voltage swing and pre-emphasis control */
  2201. static uint32_t
  2202. intel_gen6_edp_signal_levels(uint8_t train_set)
  2203. {
  2204. int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
  2205. DP_TRAIN_PRE_EMPHASIS_MASK);
  2206. switch (signal_levels) {
  2207. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
  2208. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
  2209. return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
  2210. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
  2211. return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
  2212. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
  2213. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
  2214. return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
  2215. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
  2216. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
  2217. return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
  2218. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
  2219. case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
  2220. return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
  2221. default:
  2222. DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
  2223. "0x%x\n", signal_levels);
  2224. return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
  2225. }
  2226. }
  2227. /* Gen7's DP voltage swing and pre-emphasis control */
  2228. static uint32_t
  2229. intel_gen7_edp_signal_levels(uint8_t train_set)
  2230. {
  2231. int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
  2232. DP_TRAIN_PRE_EMPHASIS_MASK);
  2233. switch (signal_levels) {
  2234. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
  2235. return EDP_LINK_TRAIN_400MV_0DB_IVB;
  2236. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
  2237. return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
  2238. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
  2239. return EDP_LINK_TRAIN_400MV_6DB_IVB;
  2240. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
  2241. return EDP_LINK_TRAIN_600MV_0DB_IVB;
  2242. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
  2243. return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
  2244. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
  2245. return EDP_LINK_TRAIN_800MV_0DB_IVB;
  2246. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
  2247. return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
  2248. default:
  2249. DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
  2250. "0x%x\n", signal_levels);
  2251. return EDP_LINK_TRAIN_500MV_0DB_IVB;
  2252. }
  2253. }
  2254. /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
  2255. static uint32_t
  2256. intel_hsw_signal_levels(uint8_t train_set)
  2257. {
  2258. int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
  2259. DP_TRAIN_PRE_EMPHASIS_MASK);
  2260. switch (signal_levels) {
  2261. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
  2262. return DDI_BUF_EMP_400MV_0DB_HSW;
  2263. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
  2264. return DDI_BUF_EMP_400MV_3_5DB_HSW;
  2265. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
  2266. return DDI_BUF_EMP_400MV_6DB_HSW;
  2267. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
  2268. return DDI_BUF_EMP_400MV_9_5DB_HSW;
  2269. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
  2270. return DDI_BUF_EMP_600MV_0DB_HSW;
  2271. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
  2272. return DDI_BUF_EMP_600MV_3_5DB_HSW;
  2273. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
  2274. return DDI_BUF_EMP_600MV_6DB_HSW;
  2275. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
  2276. return DDI_BUF_EMP_800MV_0DB_HSW;
  2277. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
  2278. return DDI_BUF_EMP_800MV_3_5DB_HSW;
  2279. default:
  2280. DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
  2281. "0x%x\n", signal_levels);
  2282. return DDI_BUF_EMP_400MV_0DB_HSW;
  2283. }
  2284. }
  2285. static uint32_t
  2286. intel_bdw_signal_levels(uint8_t train_set)
  2287. {
  2288. int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
  2289. DP_TRAIN_PRE_EMPHASIS_MASK);
  2290. switch (signal_levels) {
  2291. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
  2292. return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
  2293. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
  2294. return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
  2295. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
  2296. return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
  2297. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
  2298. return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
  2299. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
  2300. return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
  2301. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
  2302. return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
  2303. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
  2304. return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
  2305. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
  2306. return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
  2307. case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
  2308. return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
  2309. default:
  2310. DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
  2311. "0x%x\n", signal_levels);
  2312. return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
  2313. }
  2314. }
  2315. /* Properly updates "DP" with the correct signal levels. */
  2316. static void
  2317. intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
  2318. {
  2319. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  2320. enum port port = intel_dig_port->port;
  2321. struct drm_device *dev = intel_dig_port->base.base.dev;
  2322. uint32_t signal_levels, mask;
  2323. uint8_t train_set = intel_dp->train_set[0];
  2324. if (IS_BROADWELL(dev)) {
  2325. signal_levels = intel_bdw_signal_levels(train_set);
  2326. mask = DDI_BUF_EMP_MASK;
  2327. } else if (IS_HASWELL(dev)) {
  2328. signal_levels = intel_hsw_signal_levels(train_set);
  2329. mask = DDI_BUF_EMP_MASK;
  2330. } else if (IS_CHERRYVIEW(dev)) {
  2331. signal_levels = intel_chv_signal_levels(intel_dp);
  2332. mask = 0;
  2333. } else if (IS_VALLEYVIEW(dev)) {
  2334. signal_levels = intel_vlv_signal_levels(intel_dp);
  2335. mask = 0;
  2336. } else if (IS_GEN7(dev) && port == PORT_A) {
  2337. signal_levels = intel_gen7_edp_signal_levels(train_set);
  2338. mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
  2339. } else if (IS_GEN6(dev) && port == PORT_A) {
  2340. signal_levels = intel_gen6_edp_signal_levels(train_set);
  2341. mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
  2342. } else {
  2343. signal_levels = intel_gen4_signal_levels(train_set);
  2344. mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
  2345. }
  2346. DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
  2347. *DP = (*DP & ~mask) | signal_levels;
  2348. }
  2349. static bool
  2350. intel_dp_set_link_train(struct intel_dp *intel_dp,
  2351. uint32_t *DP,
  2352. uint8_t dp_train_pat)
  2353. {
  2354. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  2355. struct drm_device *dev = intel_dig_port->base.base.dev;
  2356. struct drm_i915_private *dev_priv = dev->dev_private;
  2357. enum port port = intel_dig_port->port;
  2358. uint8_t buf[sizeof(intel_dp->train_set) + 1];
  2359. int ret, len;
  2360. if (HAS_DDI(dev)) {
  2361. uint32_t temp = I915_READ(DP_TP_CTL(port));
  2362. if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
  2363. temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
  2364. else
  2365. temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
  2366. temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
  2367. switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
  2368. case DP_TRAINING_PATTERN_DISABLE:
  2369. temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
  2370. break;
  2371. case DP_TRAINING_PATTERN_1:
  2372. temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
  2373. break;
  2374. case DP_TRAINING_PATTERN_2:
  2375. temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
  2376. break;
  2377. case DP_TRAINING_PATTERN_3:
  2378. temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
  2379. break;
  2380. }
  2381. I915_WRITE(DP_TP_CTL(port), temp);
  2382. } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
  2383. *DP &= ~DP_LINK_TRAIN_MASK_CPT;
  2384. switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
  2385. case DP_TRAINING_PATTERN_DISABLE:
  2386. *DP |= DP_LINK_TRAIN_OFF_CPT;
  2387. break;
  2388. case DP_TRAINING_PATTERN_1:
  2389. *DP |= DP_LINK_TRAIN_PAT_1_CPT;
  2390. break;
  2391. case DP_TRAINING_PATTERN_2:
  2392. *DP |= DP_LINK_TRAIN_PAT_2_CPT;
  2393. break;
  2394. case DP_TRAINING_PATTERN_3:
  2395. DRM_ERROR("DP training pattern 3 not supported\n");
  2396. *DP |= DP_LINK_TRAIN_PAT_2_CPT;
  2397. break;
  2398. }
  2399. } else {
  2400. *DP &= ~DP_LINK_TRAIN_MASK;
  2401. switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
  2402. case DP_TRAINING_PATTERN_DISABLE:
  2403. *DP |= DP_LINK_TRAIN_OFF;
  2404. break;
  2405. case DP_TRAINING_PATTERN_1:
  2406. *DP |= DP_LINK_TRAIN_PAT_1;
  2407. break;
  2408. case DP_TRAINING_PATTERN_2:
  2409. *DP |= DP_LINK_TRAIN_PAT_2;
  2410. break;
  2411. case DP_TRAINING_PATTERN_3:
  2412. DRM_ERROR("DP training pattern 3 not supported\n");
  2413. *DP |= DP_LINK_TRAIN_PAT_2;
  2414. break;
  2415. }
  2416. }
  2417. I915_WRITE(intel_dp->output_reg, *DP);
  2418. POSTING_READ(intel_dp->output_reg);
  2419. buf[0] = dp_train_pat;
  2420. if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
  2421. DP_TRAINING_PATTERN_DISABLE) {
  2422. /* don't write DP_TRAINING_LANEx_SET on disable */
  2423. len = 1;
  2424. } else {
  2425. /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
  2426. memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
  2427. len = intel_dp->lane_count + 1;
  2428. }
  2429. ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
  2430. buf, len);
  2431. return ret == len;
  2432. }
  2433. static bool
  2434. intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
  2435. uint8_t dp_train_pat)
  2436. {
  2437. memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
  2438. intel_dp_set_signal_levels(intel_dp, DP);
  2439. return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
  2440. }
  2441. static bool
  2442. intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
  2443. const uint8_t link_status[DP_LINK_STATUS_SIZE])
  2444. {
  2445. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  2446. struct drm_device *dev = intel_dig_port->base.base.dev;
  2447. struct drm_i915_private *dev_priv = dev->dev_private;
  2448. int ret;
  2449. intel_get_adjust_train(intel_dp, link_status);
  2450. intel_dp_set_signal_levels(intel_dp, DP);
  2451. I915_WRITE(intel_dp->output_reg, *DP);
  2452. POSTING_READ(intel_dp->output_reg);
  2453. ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
  2454. intel_dp->train_set, intel_dp->lane_count);
  2455. return ret == intel_dp->lane_count;
  2456. }
  2457. static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
  2458. {
  2459. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  2460. struct drm_device *dev = intel_dig_port->base.base.dev;
  2461. struct drm_i915_private *dev_priv = dev->dev_private;
  2462. enum port port = intel_dig_port->port;
  2463. uint32_t val;
  2464. if (!HAS_DDI(dev))
  2465. return;
  2466. val = I915_READ(DP_TP_CTL(port));
  2467. val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
  2468. val |= DP_TP_CTL_LINK_TRAIN_IDLE;
  2469. I915_WRITE(DP_TP_CTL(port), val);
  2470. /*
  2471. * On PORT_A we can have only eDP in SST mode. There the only reason
  2472. * we need to set idle transmission mode is to work around a HW issue
  2473. * where we enable the pipe while not in idle link-training mode.
  2474. * In this case there is requirement to wait for a minimum number of
  2475. * idle patterns to be sent.
  2476. */
  2477. if (port == PORT_A)
  2478. return;
  2479. if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
  2480. 1))
  2481. DRM_ERROR("Timed out waiting for DP idle patterns\n");
  2482. }
  2483. /* Enable corresponding port and start training pattern 1 */
  2484. void
  2485. intel_dp_start_link_train(struct intel_dp *intel_dp)
  2486. {
  2487. struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
  2488. struct drm_device *dev = encoder->dev;
  2489. int i;
  2490. uint8_t voltage;
  2491. int voltage_tries, loop_tries;
  2492. uint32_t DP = intel_dp->DP;
  2493. uint8_t link_config[2];
  2494. if (HAS_DDI(dev))
  2495. intel_ddi_prepare_link_retrain(encoder);
  2496. /* Write the link configuration data */
  2497. link_config[0] = intel_dp->link_bw;
  2498. link_config[1] = intel_dp->lane_count;
  2499. if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
  2500. link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
  2501. drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
  2502. link_config[0] = 0;
  2503. link_config[1] = DP_SET_ANSI_8B10B;
  2504. drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
  2505. DP |= DP_PORT_EN;
  2506. /* clock recovery */
  2507. if (!intel_dp_reset_link_train(intel_dp, &DP,
  2508. DP_TRAINING_PATTERN_1 |
  2509. DP_LINK_SCRAMBLING_DISABLE)) {
  2510. DRM_ERROR("failed to enable link training\n");
  2511. return;
  2512. }
  2513. voltage = 0xff;
  2514. voltage_tries = 0;
  2515. loop_tries = 0;
  2516. for (;;) {
  2517. uint8_t link_status[DP_LINK_STATUS_SIZE];
  2518. drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
  2519. if (!intel_dp_get_link_status(intel_dp, link_status)) {
  2520. DRM_ERROR("failed to get link status\n");
  2521. break;
  2522. }
  2523. if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
  2524. DRM_DEBUG_KMS("clock recovery OK\n");
  2525. break;
  2526. }
  2527. /* Check to see if we've tried the max voltage */
  2528. for (i = 0; i < intel_dp->lane_count; i++)
  2529. if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
  2530. break;
  2531. if (i == intel_dp->lane_count) {
  2532. ++loop_tries;
  2533. if (loop_tries == 5) {
  2534. DRM_ERROR("too many full retries, give up\n");
  2535. break;
  2536. }
  2537. intel_dp_reset_link_train(intel_dp, &DP,
  2538. DP_TRAINING_PATTERN_1 |
  2539. DP_LINK_SCRAMBLING_DISABLE);
  2540. voltage_tries = 0;
  2541. continue;
  2542. }
  2543. /* Check to see if we've tried the same voltage 5 times */
  2544. if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
  2545. ++voltage_tries;
  2546. if (voltage_tries == 5) {
  2547. DRM_ERROR("too many voltage retries, give up\n");
  2548. break;
  2549. }
  2550. } else
  2551. voltage_tries = 0;
  2552. voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
  2553. /* Update training set as requested by target */
  2554. if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
  2555. DRM_ERROR("failed to update link training\n");
  2556. break;
  2557. }
  2558. }
  2559. intel_dp->DP = DP;
  2560. }
  2561. void
  2562. intel_dp_complete_link_train(struct intel_dp *intel_dp)
  2563. {
  2564. bool channel_eq = false;
  2565. int tries, cr_tries;
  2566. uint32_t DP = intel_dp->DP;
  2567. uint32_t training_pattern = DP_TRAINING_PATTERN_2;
  2568. /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
  2569. if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
  2570. training_pattern = DP_TRAINING_PATTERN_3;
  2571. /* channel equalization */
  2572. if (!intel_dp_set_link_train(intel_dp, &DP,
  2573. training_pattern |
  2574. DP_LINK_SCRAMBLING_DISABLE)) {
  2575. DRM_ERROR("failed to start channel equalization\n");
  2576. return;
  2577. }
  2578. tries = 0;
  2579. cr_tries = 0;
  2580. channel_eq = false;
  2581. for (;;) {
  2582. uint8_t link_status[DP_LINK_STATUS_SIZE];
  2583. if (cr_tries > 5) {
  2584. DRM_ERROR("failed to train DP, aborting\n");
  2585. break;
  2586. }
  2587. drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
  2588. if (!intel_dp_get_link_status(intel_dp, link_status)) {
  2589. DRM_ERROR("failed to get link status\n");
  2590. break;
  2591. }
  2592. /* Make sure clock is still ok */
  2593. if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
  2594. intel_dp_start_link_train(intel_dp);
  2595. intel_dp_set_link_train(intel_dp, &DP,
  2596. training_pattern |
  2597. DP_LINK_SCRAMBLING_DISABLE);
  2598. cr_tries++;
  2599. continue;
  2600. }
  2601. if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
  2602. channel_eq = true;
  2603. break;
  2604. }
  2605. /* Try 5 times, then try clock recovery if that fails */
  2606. if (tries > 5) {
  2607. intel_dp_link_down(intel_dp);
  2608. intel_dp_start_link_train(intel_dp);
  2609. intel_dp_set_link_train(intel_dp, &DP,
  2610. training_pattern |
  2611. DP_LINK_SCRAMBLING_DISABLE);
  2612. tries = 0;
  2613. cr_tries++;
  2614. continue;
  2615. }
  2616. /* Update training set as requested by target */
  2617. if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
  2618. DRM_ERROR("failed to update link training\n");
  2619. break;
  2620. }
  2621. ++tries;
  2622. }
  2623. intel_dp_set_idle_link_train(intel_dp);
  2624. intel_dp->DP = DP;
  2625. if (channel_eq)
  2626. DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
  2627. }
  2628. void intel_dp_stop_link_train(struct intel_dp *intel_dp)
  2629. {
  2630. intel_dp_set_link_train(intel_dp, &intel_dp->DP,
  2631. DP_TRAINING_PATTERN_DISABLE);
  2632. }
  2633. static void
  2634. intel_dp_link_down(struct intel_dp *intel_dp)
  2635. {
  2636. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  2637. enum port port = intel_dig_port->port;
  2638. struct drm_device *dev = intel_dig_port->base.base.dev;
  2639. struct drm_i915_private *dev_priv = dev->dev_private;
  2640. struct intel_crtc *intel_crtc =
  2641. to_intel_crtc(intel_dig_port->base.base.crtc);
  2642. uint32_t DP = intel_dp->DP;
  2643. if (WARN_ON(HAS_DDI(dev)))
  2644. return;
  2645. if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
  2646. return;
  2647. DRM_DEBUG_KMS("\n");
  2648. if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
  2649. DP &= ~DP_LINK_TRAIN_MASK_CPT;
  2650. I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
  2651. } else {
  2652. DP &= ~DP_LINK_TRAIN_MASK;
  2653. I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
  2654. }
  2655. POSTING_READ(intel_dp->output_reg);
  2656. if (HAS_PCH_IBX(dev) &&
  2657. I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
  2658. struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
  2659. /* Hardware workaround: leaving our transcoder select
  2660. * set to transcoder B while it's off will prevent the
  2661. * corresponding HDMI output on transcoder A.
  2662. *
  2663. * Combine this with another hardware workaround:
  2664. * transcoder select bit can only be cleared while the
  2665. * port is enabled.
  2666. */
  2667. DP &= ~DP_PIPEB_SELECT;
  2668. I915_WRITE(intel_dp->output_reg, DP);
  2669. /* Changes to enable or select take place the vblank
  2670. * after being written.
  2671. */
  2672. if (WARN_ON(crtc == NULL)) {
  2673. /* We should never try to disable a port without a crtc
  2674. * attached. For paranoia keep the code around for a
  2675. * bit. */
  2676. POSTING_READ(intel_dp->output_reg);
  2677. msleep(50);
  2678. } else
  2679. intel_wait_for_vblank(dev, intel_crtc->pipe);
  2680. }
  2681. DP &= ~DP_AUDIO_OUTPUT_ENABLE;
  2682. I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
  2683. POSTING_READ(intel_dp->output_reg);
  2684. msleep(intel_dp->panel_power_down_delay);
  2685. }
  2686. static bool
  2687. intel_dp_get_dpcd(struct intel_dp *intel_dp)
  2688. {
  2689. struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
  2690. struct drm_device *dev = dig_port->base.base.dev;
  2691. struct drm_i915_private *dev_priv = dev->dev_private;
  2692. char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
  2693. if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
  2694. sizeof(intel_dp->dpcd)) < 0)
  2695. return false; /* aux transfer failed */
  2696. hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
  2697. 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
  2698. DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
  2699. if (intel_dp->dpcd[DP_DPCD_REV] == 0)
  2700. return false; /* DPCD not present */
  2701. /* Check if the panel supports PSR */
  2702. memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
  2703. if (is_edp(intel_dp)) {
  2704. intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
  2705. intel_dp->psr_dpcd,
  2706. sizeof(intel_dp->psr_dpcd));
  2707. if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
  2708. dev_priv->psr.sink_support = true;
  2709. DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
  2710. }
  2711. }
  2712. /* Training Pattern 3 support */
  2713. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
  2714. intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
  2715. intel_dp->use_tps3 = true;
  2716. DRM_DEBUG_KMS("Displayport TPS3 supported");
  2717. } else
  2718. intel_dp->use_tps3 = false;
  2719. if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
  2720. DP_DWN_STRM_PORT_PRESENT))
  2721. return true; /* native DP sink */
  2722. if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
  2723. return true; /* no per-port downstream info */
  2724. if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
  2725. intel_dp->downstream_ports,
  2726. DP_MAX_DOWNSTREAM_PORTS) < 0)
  2727. return false; /* downstream port status fetch failed */
  2728. return true;
  2729. }
  2730. static void
  2731. intel_dp_probe_oui(struct intel_dp *intel_dp)
  2732. {
  2733. u8 buf[3];
  2734. if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
  2735. return;
  2736. intel_edp_panel_vdd_on(intel_dp);
  2737. if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
  2738. DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
  2739. buf[0], buf[1], buf[2]);
  2740. if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
  2741. DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
  2742. buf[0], buf[1], buf[2]);
  2743. edp_panel_vdd_off(intel_dp, false);
  2744. }
  2745. int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
  2746. {
  2747. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  2748. struct drm_device *dev = intel_dig_port->base.base.dev;
  2749. struct intel_crtc *intel_crtc =
  2750. to_intel_crtc(intel_dig_port->base.base.crtc);
  2751. u8 buf[1];
  2752. if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
  2753. return -EAGAIN;
  2754. if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
  2755. return -ENOTTY;
  2756. if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
  2757. DP_TEST_SINK_START) < 0)
  2758. return -EAGAIN;
  2759. /* Wait 2 vblanks to be sure we will have the correct CRC value */
  2760. intel_wait_for_vblank(dev, intel_crtc->pipe);
  2761. intel_wait_for_vblank(dev, intel_crtc->pipe);
  2762. if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
  2763. return -EAGAIN;
  2764. drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
  2765. return 0;
  2766. }
  2767. static bool
  2768. intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
  2769. {
  2770. return intel_dp_dpcd_read_wake(&intel_dp->aux,
  2771. DP_DEVICE_SERVICE_IRQ_VECTOR,
  2772. sink_irq_vector, 1) == 1;
  2773. }
  2774. static void
  2775. intel_dp_handle_test_request(struct intel_dp *intel_dp)
  2776. {
  2777. /* NAK by default */
  2778. drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
  2779. }
  2780. /*
  2781. * According to DP spec
  2782. * 5.1.2:
  2783. * 1. Read DPCD
  2784. * 2. Configure link according to Receiver Capabilities
  2785. * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
  2786. * 4. Check link status on receipt of hot-plug interrupt
  2787. */
  2788. void
  2789. intel_dp_check_link_status(struct intel_dp *intel_dp)
  2790. {
  2791. struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
  2792. u8 sink_irq_vector;
  2793. u8 link_status[DP_LINK_STATUS_SIZE];
  2794. /* FIXME: This access isn't protected by any locks. */
  2795. if (!intel_encoder->connectors_active)
  2796. return;
  2797. if (WARN_ON(!intel_encoder->base.crtc))
  2798. return;
  2799. /* Try to read receiver status if the link appears to be up */
  2800. if (!intel_dp_get_link_status(intel_dp, link_status)) {
  2801. return;
  2802. }
  2803. /* Now read the DPCD to see if it's actually running */
  2804. if (!intel_dp_get_dpcd(intel_dp)) {
  2805. return;
  2806. }
  2807. /* Try to read the source of the interrupt */
  2808. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
  2809. intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
  2810. /* Clear interrupt source */
  2811. drm_dp_dpcd_writeb(&intel_dp->aux,
  2812. DP_DEVICE_SERVICE_IRQ_VECTOR,
  2813. sink_irq_vector);
  2814. if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
  2815. intel_dp_handle_test_request(intel_dp);
  2816. if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
  2817. DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
  2818. }
  2819. if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
  2820. DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
  2821. intel_encoder->base.name);
  2822. intel_dp_start_link_train(intel_dp);
  2823. intel_dp_complete_link_train(intel_dp);
  2824. intel_dp_stop_link_train(intel_dp);
  2825. }
  2826. }
  2827. /* XXX this is probably wrong for multiple downstream ports */
  2828. static enum drm_connector_status
  2829. intel_dp_detect_dpcd(struct intel_dp *intel_dp)
  2830. {
  2831. uint8_t *dpcd = intel_dp->dpcd;
  2832. uint8_t type;
  2833. if (!intel_dp_get_dpcd(intel_dp))
  2834. return connector_status_disconnected;
  2835. /* if there's no downstream port, we're done */
  2836. if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
  2837. return connector_status_connected;
  2838. /* If we're HPD-aware, SINK_COUNT changes dynamically */
  2839. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
  2840. intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
  2841. uint8_t reg;
  2842. if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
  2843. &reg, 1) < 0)
  2844. return connector_status_unknown;
  2845. return DP_GET_SINK_COUNT(reg) ? connector_status_connected
  2846. : connector_status_disconnected;
  2847. }
  2848. /* If no HPD, poke DDC gently */
  2849. if (drm_probe_ddc(&intel_dp->aux.ddc))
  2850. return connector_status_connected;
  2851. /* Well we tried, say unknown for unreliable port types */
  2852. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
  2853. type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
  2854. if (type == DP_DS_PORT_TYPE_VGA ||
  2855. type == DP_DS_PORT_TYPE_NON_EDID)
  2856. return connector_status_unknown;
  2857. } else {
  2858. type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
  2859. DP_DWN_STRM_PORT_TYPE_MASK;
  2860. if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
  2861. type == DP_DWN_STRM_PORT_TYPE_OTHER)
  2862. return connector_status_unknown;
  2863. }
  2864. /* Anything else is out of spec, warn and ignore */
  2865. DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
  2866. return connector_status_disconnected;
  2867. }
  2868. static enum drm_connector_status
  2869. ironlake_dp_detect(struct intel_dp *intel_dp)
  2870. {
  2871. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  2872. struct drm_i915_private *dev_priv = dev->dev_private;
  2873. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  2874. enum drm_connector_status status;
  2875. /* Can't disconnect eDP, but you can close the lid... */
  2876. if (is_edp(intel_dp)) {
  2877. status = intel_panel_detect(dev);
  2878. if (status == connector_status_unknown)
  2879. status = connector_status_connected;
  2880. return status;
  2881. }
  2882. if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
  2883. return connector_status_disconnected;
  2884. return intel_dp_detect_dpcd(intel_dp);
  2885. }
  2886. static enum drm_connector_status
  2887. g4x_dp_detect(struct intel_dp *intel_dp)
  2888. {
  2889. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  2890. struct drm_i915_private *dev_priv = dev->dev_private;
  2891. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  2892. uint32_t bit;
  2893. /* Can't disconnect eDP, but you can close the lid... */
  2894. if (is_edp(intel_dp)) {
  2895. enum drm_connector_status status;
  2896. status = intel_panel_detect(dev);
  2897. if (status == connector_status_unknown)
  2898. status = connector_status_connected;
  2899. return status;
  2900. }
  2901. if (IS_VALLEYVIEW(dev)) {
  2902. switch (intel_dig_port->port) {
  2903. case PORT_B:
  2904. bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
  2905. break;
  2906. case PORT_C:
  2907. bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
  2908. break;
  2909. case PORT_D:
  2910. bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
  2911. break;
  2912. default:
  2913. return connector_status_unknown;
  2914. }
  2915. } else {
  2916. switch (intel_dig_port->port) {
  2917. case PORT_B:
  2918. bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
  2919. break;
  2920. case PORT_C:
  2921. bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
  2922. break;
  2923. case PORT_D:
  2924. bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
  2925. break;
  2926. default:
  2927. return connector_status_unknown;
  2928. }
  2929. }
  2930. if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
  2931. return connector_status_disconnected;
  2932. return intel_dp_detect_dpcd(intel_dp);
  2933. }
  2934. static struct edid *
  2935. intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
  2936. {
  2937. struct intel_connector *intel_connector = to_intel_connector(connector);
  2938. /* use cached edid if we have one */
  2939. if (intel_connector->edid) {
  2940. /* invalid edid */
  2941. if (IS_ERR(intel_connector->edid))
  2942. return NULL;
  2943. return drm_edid_duplicate(intel_connector->edid);
  2944. }
  2945. return drm_get_edid(connector, adapter);
  2946. }
  2947. static int
  2948. intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
  2949. {
  2950. struct intel_connector *intel_connector = to_intel_connector(connector);
  2951. /* use cached edid if we have one */
  2952. if (intel_connector->edid) {
  2953. /* invalid edid */
  2954. if (IS_ERR(intel_connector->edid))
  2955. return 0;
  2956. return intel_connector_update_modes(connector,
  2957. intel_connector->edid);
  2958. }
  2959. return intel_ddc_get_modes(connector, adapter);
  2960. }
  2961. static enum drm_connector_status
  2962. intel_dp_detect(struct drm_connector *connector, bool force)
  2963. {
  2964. struct intel_dp *intel_dp = intel_attached_dp(connector);
  2965. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  2966. struct intel_encoder *intel_encoder = &intel_dig_port->base;
  2967. struct drm_device *dev = connector->dev;
  2968. struct drm_i915_private *dev_priv = dev->dev_private;
  2969. enum drm_connector_status status;
  2970. enum intel_display_power_domain power_domain;
  2971. struct edid *edid = NULL;
  2972. intel_runtime_pm_get(dev_priv);
  2973. power_domain = intel_display_port_power_domain(intel_encoder);
  2974. intel_display_power_get(dev_priv, power_domain);
  2975. DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  2976. connector->base.id, connector->name);
  2977. intel_dp->has_audio = false;
  2978. if (HAS_PCH_SPLIT(dev))
  2979. status = ironlake_dp_detect(intel_dp);
  2980. else
  2981. status = g4x_dp_detect(intel_dp);
  2982. if (status != connector_status_connected)
  2983. goto out;
  2984. intel_dp_probe_oui(intel_dp);
  2985. if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
  2986. intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
  2987. } else {
  2988. edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
  2989. if (edid) {
  2990. intel_dp->has_audio = drm_detect_monitor_audio(edid);
  2991. kfree(edid);
  2992. }
  2993. }
  2994. if (intel_encoder->type != INTEL_OUTPUT_EDP)
  2995. intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
  2996. status = connector_status_connected;
  2997. out:
  2998. intel_display_power_put(dev_priv, power_domain);
  2999. intel_runtime_pm_put(dev_priv);
  3000. return status;
  3001. }
  3002. static int intel_dp_get_modes(struct drm_connector *connector)
  3003. {
  3004. struct intel_dp *intel_dp = intel_attached_dp(connector);
  3005. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  3006. struct intel_encoder *intel_encoder = &intel_dig_port->base;
  3007. struct intel_connector *intel_connector = to_intel_connector(connector);
  3008. struct drm_device *dev = connector->dev;
  3009. struct drm_i915_private *dev_priv = dev->dev_private;
  3010. enum intel_display_power_domain power_domain;
  3011. int ret;
  3012. /* We should parse the EDID data and find out if it has an audio sink
  3013. */
  3014. power_domain = intel_display_port_power_domain(intel_encoder);
  3015. intel_display_power_get(dev_priv, power_domain);
  3016. ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
  3017. intel_display_power_put(dev_priv, power_domain);
  3018. if (ret)
  3019. return ret;
  3020. /* if eDP has no EDID, fall back to fixed mode */
  3021. if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
  3022. struct drm_display_mode *mode;
  3023. mode = drm_mode_duplicate(dev,
  3024. intel_connector->panel.fixed_mode);
  3025. if (mode) {
  3026. drm_mode_probed_add(connector, mode);
  3027. return 1;
  3028. }
  3029. }
  3030. return 0;
  3031. }
  3032. static bool
  3033. intel_dp_detect_audio(struct drm_connector *connector)
  3034. {
  3035. struct intel_dp *intel_dp = intel_attached_dp(connector);
  3036. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  3037. struct intel_encoder *intel_encoder = &intel_dig_port->base;
  3038. struct drm_device *dev = connector->dev;
  3039. struct drm_i915_private *dev_priv = dev->dev_private;
  3040. enum intel_display_power_domain power_domain;
  3041. struct edid *edid;
  3042. bool has_audio = false;
  3043. power_domain = intel_display_port_power_domain(intel_encoder);
  3044. intel_display_power_get(dev_priv, power_domain);
  3045. edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
  3046. if (edid) {
  3047. has_audio = drm_detect_monitor_audio(edid);
  3048. kfree(edid);
  3049. }
  3050. intel_display_power_put(dev_priv, power_domain);
  3051. return has_audio;
  3052. }
  3053. static int
  3054. intel_dp_set_property(struct drm_connector *connector,
  3055. struct drm_property *property,
  3056. uint64_t val)
  3057. {
  3058. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  3059. struct intel_connector *intel_connector = to_intel_connector(connector);
  3060. struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
  3061. struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
  3062. int ret;
  3063. ret = drm_object_property_set_value(&connector->base, property, val);
  3064. if (ret)
  3065. return ret;
  3066. if (property == dev_priv->force_audio_property) {
  3067. int i = val;
  3068. bool has_audio;
  3069. if (i == intel_dp->force_audio)
  3070. return 0;
  3071. intel_dp->force_audio = i;
  3072. if (i == HDMI_AUDIO_AUTO)
  3073. has_audio = intel_dp_detect_audio(connector);
  3074. else
  3075. has_audio = (i == HDMI_AUDIO_ON);
  3076. if (has_audio == intel_dp->has_audio)
  3077. return 0;
  3078. intel_dp->has_audio = has_audio;
  3079. goto done;
  3080. }
  3081. if (property == dev_priv->broadcast_rgb_property) {
  3082. bool old_auto = intel_dp->color_range_auto;
  3083. uint32_t old_range = intel_dp->color_range;
  3084. switch (val) {
  3085. case INTEL_BROADCAST_RGB_AUTO:
  3086. intel_dp->color_range_auto = true;
  3087. break;
  3088. case INTEL_BROADCAST_RGB_FULL:
  3089. intel_dp->color_range_auto = false;
  3090. intel_dp->color_range = 0;
  3091. break;
  3092. case INTEL_BROADCAST_RGB_LIMITED:
  3093. intel_dp->color_range_auto = false;
  3094. intel_dp->color_range = DP_COLOR_RANGE_16_235;
  3095. break;
  3096. default:
  3097. return -EINVAL;
  3098. }
  3099. if (old_auto == intel_dp->color_range_auto &&
  3100. old_range == intel_dp->color_range)
  3101. return 0;
  3102. goto done;
  3103. }
  3104. if (is_edp(intel_dp) &&
  3105. property == connector->dev->mode_config.scaling_mode_property) {
  3106. if (val == DRM_MODE_SCALE_NONE) {
  3107. DRM_DEBUG_KMS("no scaling not supported\n");
  3108. return -EINVAL;
  3109. }
  3110. if (intel_connector->panel.fitting_mode == val) {
  3111. /* the eDP scaling property is not changed */
  3112. return 0;
  3113. }
  3114. intel_connector->panel.fitting_mode = val;
  3115. goto done;
  3116. }
  3117. return -EINVAL;
  3118. done:
  3119. if (intel_encoder->base.crtc)
  3120. intel_crtc_restore_mode(intel_encoder->base.crtc);
  3121. return 0;
  3122. }
  3123. static void
  3124. intel_dp_connector_destroy(struct drm_connector *connector)
  3125. {
  3126. struct intel_connector *intel_connector = to_intel_connector(connector);
  3127. if (!IS_ERR_OR_NULL(intel_connector->edid))
  3128. kfree(intel_connector->edid);
  3129. /* Can't call is_edp() since the encoder may have been destroyed
  3130. * already. */
  3131. if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
  3132. intel_panel_fini(&intel_connector->panel);
  3133. drm_connector_cleanup(connector);
  3134. kfree(connector);
  3135. }
  3136. void intel_dp_encoder_destroy(struct drm_encoder *encoder)
  3137. {
  3138. struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  3139. struct intel_dp *intel_dp = &intel_dig_port->dp;
  3140. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  3141. drm_dp_aux_unregister(&intel_dp->aux);
  3142. drm_encoder_cleanup(encoder);
  3143. if (is_edp(intel_dp)) {
  3144. cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
  3145. drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
  3146. edp_panel_vdd_off_sync(intel_dp);
  3147. drm_modeset_unlock(&dev->mode_config.connection_mutex);
  3148. if (intel_dp->edp_notifier.notifier_call) {
  3149. unregister_reboot_notifier(&intel_dp->edp_notifier);
  3150. intel_dp->edp_notifier.notifier_call = NULL;
  3151. }
  3152. }
  3153. kfree(intel_dig_port);
  3154. }
  3155. static const struct drm_connector_funcs intel_dp_connector_funcs = {
  3156. .dpms = intel_connector_dpms,
  3157. .detect = intel_dp_detect,
  3158. .fill_modes = drm_helper_probe_single_connector_modes,
  3159. .set_property = intel_dp_set_property,
  3160. .destroy = intel_dp_connector_destroy,
  3161. };
  3162. static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
  3163. .get_modes = intel_dp_get_modes,
  3164. .mode_valid = intel_dp_mode_valid,
  3165. .best_encoder = intel_best_encoder,
  3166. };
  3167. static const struct drm_encoder_funcs intel_dp_enc_funcs = {
  3168. .destroy = intel_dp_encoder_destroy,
  3169. };
  3170. static void
  3171. intel_dp_hot_plug(struct intel_encoder *intel_encoder)
  3172. {
  3173. struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
  3174. intel_dp_check_link_status(intel_dp);
  3175. }
  3176. /* Return which DP Port should be selected for Transcoder DP control */
  3177. int
  3178. intel_trans_dp_port_sel(struct drm_crtc *crtc)
  3179. {
  3180. struct drm_device *dev = crtc->dev;
  3181. struct intel_encoder *intel_encoder;
  3182. struct intel_dp *intel_dp;
  3183. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  3184. intel_dp = enc_to_intel_dp(&intel_encoder->base);
  3185. if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
  3186. intel_encoder->type == INTEL_OUTPUT_EDP)
  3187. return intel_dp->output_reg;
  3188. }
  3189. return -1;
  3190. }
  3191. /* check the VBT to see whether the eDP is on DP-D port */
  3192. bool intel_dp_is_edp(struct drm_device *dev, enum port port)
  3193. {
  3194. struct drm_i915_private *dev_priv = dev->dev_private;
  3195. union child_device_config *p_child;
  3196. int i;
  3197. static const short port_mapping[] = {
  3198. [PORT_B] = PORT_IDPB,
  3199. [PORT_C] = PORT_IDPC,
  3200. [PORT_D] = PORT_IDPD,
  3201. };
  3202. if (port == PORT_A)
  3203. return true;
  3204. if (!dev_priv->vbt.child_dev_num)
  3205. return false;
  3206. for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
  3207. p_child = dev_priv->vbt.child_dev + i;
  3208. if (p_child->common.dvo_port == port_mapping[port] &&
  3209. (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
  3210. (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
  3211. return true;
  3212. }
  3213. return false;
  3214. }
  3215. static void
  3216. intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
  3217. {
  3218. struct intel_connector *intel_connector = to_intel_connector(connector);
  3219. intel_attach_force_audio_property(connector);
  3220. intel_attach_broadcast_rgb_property(connector);
  3221. intel_dp->color_range_auto = true;
  3222. if (is_edp(intel_dp)) {
  3223. drm_mode_create_scaling_mode_property(connector->dev);
  3224. drm_object_attach_property(
  3225. &connector->base,
  3226. connector->dev->mode_config.scaling_mode_property,
  3227. DRM_MODE_SCALE_ASPECT);
  3228. intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
  3229. }
  3230. }
  3231. static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
  3232. {
  3233. intel_dp->last_power_cycle = jiffies;
  3234. intel_dp->last_power_on = jiffies;
  3235. intel_dp->last_backlight_off = jiffies;
  3236. }
  3237. static void
  3238. intel_dp_init_panel_power_sequencer(struct drm_device *dev,
  3239. struct intel_dp *intel_dp,
  3240. struct edp_power_seq *out)
  3241. {
  3242. struct drm_i915_private *dev_priv = dev->dev_private;
  3243. struct edp_power_seq cur, vbt, spec, final;
  3244. u32 pp_on, pp_off, pp_div, pp;
  3245. int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
  3246. if (HAS_PCH_SPLIT(dev)) {
  3247. pp_ctrl_reg = PCH_PP_CONTROL;
  3248. pp_on_reg = PCH_PP_ON_DELAYS;
  3249. pp_off_reg = PCH_PP_OFF_DELAYS;
  3250. pp_div_reg = PCH_PP_DIVISOR;
  3251. } else {
  3252. enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
  3253. pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
  3254. pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
  3255. pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
  3256. pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
  3257. }
  3258. /* Workaround: Need to write PP_CONTROL with the unlock key as
  3259. * the very first thing. */
  3260. pp = ironlake_get_pp_control(intel_dp);
  3261. I915_WRITE(pp_ctrl_reg, pp);
  3262. pp_on = I915_READ(pp_on_reg);
  3263. pp_off = I915_READ(pp_off_reg);
  3264. pp_div = I915_READ(pp_div_reg);
  3265. /* Pull timing values out of registers */
  3266. cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
  3267. PANEL_POWER_UP_DELAY_SHIFT;
  3268. cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
  3269. PANEL_LIGHT_ON_DELAY_SHIFT;
  3270. cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
  3271. PANEL_LIGHT_OFF_DELAY_SHIFT;
  3272. cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
  3273. PANEL_POWER_DOWN_DELAY_SHIFT;
  3274. cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
  3275. PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
  3276. DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
  3277. cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
  3278. vbt = dev_priv->vbt.edp_pps;
  3279. /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
  3280. * our hw here, which are all in 100usec. */
  3281. spec.t1_t3 = 210 * 10;
  3282. spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
  3283. spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
  3284. spec.t10 = 500 * 10;
  3285. /* This one is special and actually in units of 100ms, but zero
  3286. * based in the hw (so we need to add 100 ms). But the sw vbt
  3287. * table multiplies it with 1000 to make it in units of 100usec,
  3288. * too. */
  3289. spec.t11_t12 = (510 + 100) * 10;
  3290. DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
  3291. vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
  3292. /* Use the max of the register settings and vbt. If both are
  3293. * unset, fall back to the spec limits. */
  3294. #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
  3295. spec.field : \
  3296. max(cur.field, vbt.field))
  3297. assign_final(t1_t3);
  3298. assign_final(t8);
  3299. assign_final(t9);
  3300. assign_final(t10);
  3301. assign_final(t11_t12);
  3302. #undef assign_final
  3303. #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
  3304. intel_dp->panel_power_up_delay = get_delay(t1_t3);
  3305. intel_dp->backlight_on_delay = get_delay(t8);
  3306. intel_dp->backlight_off_delay = get_delay(t9);
  3307. intel_dp->panel_power_down_delay = get_delay(t10);
  3308. intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
  3309. #undef get_delay
  3310. DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
  3311. intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
  3312. intel_dp->panel_power_cycle_delay);
  3313. DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
  3314. intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
  3315. if (out)
  3316. *out = final;
  3317. }
  3318. static void
  3319. intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
  3320. struct intel_dp *intel_dp,
  3321. struct edp_power_seq *seq)
  3322. {
  3323. struct drm_i915_private *dev_priv = dev->dev_private;
  3324. u32 pp_on, pp_off, pp_div, port_sel = 0;
  3325. int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
  3326. int pp_on_reg, pp_off_reg, pp_div_reg;
  3327. if (HAS_PCH_SPLIT(dev)) {
  3328. pp_on_reg = PCH_PP_ON_DELAYS;
  3329. pp_off_reg = PCH_PP_OFF_DELAYS;
  3330. pp_div_reg = PCH_PP_DIVISOR;
  3331. } else {
  3332. enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
  3333. pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
  3334. pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
  3335. pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
  3336. }
  3337. /*
  3338. * And finally store the new values in the power sequencer. The
  3339. * backlight delays are set to 1 because we do manual waits on them. For
  3340. * T8, even BSpec recommends doing it. For T9, if we don't do this,
  3341. * we'll end up waiting for the backlight off delay twice: once when we
  3342. * do the manual sleep, and once when we disable the panel and wait for
  3343. * the PP_STATUS bit to become zero.
  3344. */
  3345. pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
  3346. (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
  3347. pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
  3348. (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
  3349. /* Compute the divisor for the pp clock, simply match the Bspec
  3350. * formula. */
  3351. pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
  3352. pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
  3353. << PANEL_POWER_CYCLE_DELAY_SHIFT);
  3354. /* Haswell doesn't have any port selection bits for the panel
  3355. * power sequencer any more. */
  3356. if (IS_VALLEYVIEW(dev)) {
  3357. if (dp_to_dig_port(intel_dp)->port == PORT_B)
  3358. port_sel = PANEL_PORT_SELECT_DPB_VLV;
  3359. else
  3360. port_sel = PANEL_PORT_SELECT_DPC_VLV;
  3361. } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
  3362. if (dp_to_dig_port(intel_dp)->port == PORT_A)
  3363. port_sel = PANEL_PORT_SELECT_DPA;
  3364. else
  3365. port_sel = PANEL_PORT_SELECT_DPD;
  3366. }
  3367. pp_on |= port_sel;
  3368. I915_WRITE(pp_on_reg, pp_on);
  3369. I915_WRITE(pp_off_reg, pp_off);
  3370. I915_WRITE(pp_div_reg, pp_div);
  3371. DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
  3372. I915_READ(pp_on_reg),
  3373. I915_READ(pp_off_reg),
  3374. I915_READ(pp_div_reg));
  3375. }
  3376. void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
  3377. {
  3378. struct drm_i915_private *dev_priv = dev->dev_private;
  3379. struct intel_encoder *encoder;
  3380. struct intel_dp *intel_dp = NULL;
  3381. struct intel_crtc_config *config = NULL;
  3382. struct intel_crtc *intel_crtc = NULL;
  3383. struct intel_connector *intel_connector = dev_priv->drrs.connector;
  3384. u32 reg, val;
  3385. enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
  3386. if (refresh_rate <= 0) {
  3387. DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
  3388. return;
  3389. }
  3390. if (intel_connector == NULL) {
  3391. DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
  3392. return;
  3393. }
  3394. if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
  3395. DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
  3396. return;
  3397. }
  3398. encoder = intel_attached_encoder(&intel_connector->base);
  3399. intel_dp = enc_to_intel_dp(&encoder->base);
  3400. intel_crtc = encoder->new_crtc;
  3401. if (!intel_crtc) {
  3402. DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
  3403. return;
  3404. }
  3405. config = &intel_crtc->config;
  3406. if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
  3407. DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
  3408. return;
  3409. }
  3410. if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
  3411. index = DRRS_LOW_RR;
  3412. if (index == intel_dp->drrs_state.refresh_rate_type) {
  3413. DRM_DEBUG_KMS(
  3414. "DRRS requested for previously set RR...ignoring\n");
  3415. return;
  3416. }
  3417. if (!intel_crtc->active) {
  3418. DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
  3419. return;
  3420. }
  3421. if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
  3422. reg = PIPECONF(intel_crtc->config.cpu_transcoder);
  3423. val = I915_READ(reg);
  3424. if (index > DRRS_HIGH_RR) {
  3425. val |= PIPECONF_EDP_RR_MODE_SWITCH;
  3426. intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
  3427. } else {
  3428. val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
  3429. }
  3430. I915_WRITE(reg, val);
  3431. }
  3432. /*
  3433. * mutex taken to ensure that there is no race between differnt
  3434. * drrs calls trying to update refresh rate. This scenario may occur
  3435. * in future when idleness detection based DRRS in kernel and
  3436. * possible calls from user space to set differnt RR are made.
  3437. */
  3438. mutex_lock(&intel_dp->drrs_state.mutex);
  3439. intel_dp->drrs_state.refresh_rate_type = index;
  3440. mutex_unlock(&intel_dp->drrs_state.mutex);
  3441. DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
  3442. }
  3443. static struct drm_display_mode *
  3444. intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
  3445. struct intel_connector *intel_connector,
  3446. struct drm_display_mode *fixed_mode)
  3447. {
  3448. struct drm_connector *connector = &intel_connector->base;
  3449. struct intel_dp *intel_dp = &intel_dig_port->dp;
  3450. struct drm_device *dev = intel_dig_port->base.base.dev;
  3451. struct drm_i915_private *dev_priv = dev->dev_private;
  3452. struct drm_display_mode *downclock_mode = NULL;
  3453. if (INTEL_INFO(dev)->gen <= 6) {
  3454. DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
  3455. return NULL;
  3456. }
  3457. if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
  3458. DRM_INFO("VBT doesn't support DRRS\n");
  3459. return NULL;
  3460. }
  3461. downclock_mode = intel_find_panel_downclock
  3462. (dev, fixed_mode, connector);
  3463. if (!downclock_mode) {
  3464. DRM_INFO("DRRS not supported\n");
  3465. return NULL;
  3466. }
  3467. dev_priv->drrs.connector = intel_connector;
  3468. mutex_init(&intel_dp->drrs_state.mutex);
  3469. intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
  3470. intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
  3471. DRM_INFO("seamless DRRS supported for eDP panel.\n");
  3472. return downclock_mode;
  3473. }
  3474. static bool intel_edp_init_connector(struct intel_dp *intel_dp,
  3475. struct intel_connector *intel_connector,
  3476. struct edp_power_seq *power_seq)
  3477. {
  3478. struct drm_connector *connector = &intel_connector->base;
  3479. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  3480. struct intel_encoder *intel_encoder = &intel_dig_port->base;
  3481. struct drm_device *dev = intel_encoder->base.dev;
  3482. struct drm_i915_private *dev_priv = dev->dev_private;
  3483. struct drm_display_mode *fixed_mode = NULL;
  3484. struct drm_display_mode *downclock_mode = NULL;
  3485. bool has_dpcd;
  3486. struct drm_display_mode *scan;
  3487. struct edid *edid;
  3488. intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
  3489. if (!is_edp(intel_dp))
  3490. return true;
  3491. /* The VDD bit needs a power domain reference, so if the bit is already
  3492. * enabled when we boot, grab this reference. */
  3493. if (edp_have_panel_vdd(intel_dp)) {
  3494. enum intel_display_power_domain power_domain;
  3495. power_domain = intel_display_port_power_domain(intel_encoder);
  3496. intel_display_power_get(dev_priv, power_domain);
  3497. }
  3498. /* Cache DPCD and EDID for edp. */
  3499. intel_edp_panel_vdd_on(intel_dp);
  3500. has_dpcd = intel_dp_get_dpcd(intel_dp);
  3501. edp_panel_vdd_off(intel_dp, false);
  3502. if (has_dpcd) {
  3503. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
  3504. dev_priv->no_aux_handshake =
  3505. intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
  3506. DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
  3507. } else {
  3508. /* if this fails, presume the device is a ghost */
  3509. DRM_INFO("failed to retrieve link info, disabling eDP\n");
  3510. return false;
  3511. }
  3512. /* We now know it's not a ghost, init power sequence regs. */
  3513. intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
  3514. mutex_lock(&dev->mode_config.mutex);
  3515. edid = drm_get_edid(connector, &intel_dp->aux.ddc);
  3516. if (edid) {
  3517. if (drm_add_edid_modes(connector, edid)) {
  3518. drm_mode_connector_update_edid_property(connector,
  3519. edid);
  3520. drm_edid_to_eld(connector, edid);
  3521. } else {
  3522. kfree(edid);
  3523. edid = ERR_PTR(-EINVAL);
  3524. }
  3525. } else {
  3526. edid = ERR_PTR(-ENOENT);
  3527. }
  3528. intel_connector->edid = edid;
  3529. /* prefer fixed mode from EDID if available */
  3530. list_for_each_entry(scan, &connector->probed_modes, head) {
  3531. if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
  3532. fixed_mode = drm_mode_duplicate(dev, scan);
  3533. downclock_mode = intel_dp_drrs_init(
  3534. intel_dig_port,
  3535. intel_connector, fixed_mode);
  3536. break;
  3537. }
  3538. }
  3539. /* fallback to VBT if available for eDP */
  3540. if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
  3541. fixed_mode = drm_mode_duplicate(dev,
  3542. dev_priv->vbt.lfp_lvds_vbt_mode);
  3543. if (fixed_mode)
  3544. fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
  3545. }
  3546. mutex_unlock(&dev->mode_config.mutex);
  3547. if (IS_VALLEYVIEW(dev)) {
  3548. intel_dp->edp_notifier.notifier_call = edp_notify_handler;
  3549. register_reboot_notifier(&intel_dp->edp_notifier);
  3550. }
  3551. intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
  3552. intel_panel_setup_backlight(connector);
  3553. return true;
  3554. }
  3555. bool
  3556. intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
  3557. struct intel_connector *intel_connector)
  3558. {
  3559. struct drm_connector *connector = &intel_connector->base;
  3560. struct intel_dp *intel_dp = &intel_dig_port->dp;
  3561. struct intel_encoder *intel_encoder = &intel_dig_port->base;
  3562. struct drm_device *dev = intel_encoder->base.dev;
  3563. struct drm_i915_private *dev_priv = dev->dev_private;
  3564. enum port port = intel_dig_port->port;
  3565. struct edp_power_seq power_seq = { 0 };
  3566. int type;
  3567. /* intel_dp vfuncs */
  3568. if (IS_VALLEYVIEW(dev))
  3569. intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
  3570. else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
  3571. intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
  3572. else if (HAS_PCH_SPLIT(dev))
  3573. intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
  3574. else
  3575. intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
  3576. intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
  3577. /* Preserve the current hw state. */
  3578. intel_dp->DP = I915_READ(intel_dp->output_reg);
  3579. intel_dp->attached_connector = intel_connector;
  3580. if (intel_dp_is_edp(dev, port))
  3581. type = DRM_MODE_CONNECTOR_eDP;
  3582. else
  3583. type = DRM_MODE_CONNECTOR_DisplayPort;
  3584. /*
  3585. * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
  3586. * for DP the encoder type can be set by the caller to
  3587. * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
  3588. */
  3589. if (type == DRM_MODE_CONNECTOR_eDP)
  3590. intel_encoder->type = INTEL_OUTPUT_EDP;
  3591. DRM_DEBUG_KMS("Adding %s connector on port %c\n",
  3592. type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
  3593. port_name(port));
  3594. drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
  3595. drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
  3596. connector->interlace_allowed = true;
  3597. connector->doublescan_allowed = 0;
  3598. INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
  3599. edp_panel_vdd_work);
  3600. intel_connector_attach_encoder(intel_connector, intel_encoder);
  3601. drm_sysfs_connector_add(connector);
  3602. if (HAS_DDI(dev))
  3603. intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
  3604. else
  3605. intel_connector->get_hw_state = intel_connector_get_hw_state;
  3606. intel_connector->unregister = intel_dp_connector_unregister;
  3607. /* Set up the hotplug pin. */
  3608. switch (port) {
  3609. case PORT_A:
  3610. intel_encoder->hpd_pin = HPD_PORT_A;
  3611. break;
  3612. case PORT_B:
  3613. intel_encoder->hpd_pin = HPD_PORT_B;
  3614. break;
  3615. case PORT_C:
  3616. intel_encoder->hpd_pin = HPD_PORT_C;
  3617. break;
  3618. case PORT_D:
  3619. intel_encoder->hpd_pin = HPD_PORT_D;
  3620. break;
  3621. default:
  3622. BUG();
  3623. }
  3624. if (is_edp(intel_dp)) {
  3625. intel_dp_init_panel_power_timestamps(intel_dp);
  3626. intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
  3627. }
  3628. intel_dp_aux_init(intel_dp, intel_connector);
  3629. intel_dp->psr_setup_done = false;
  3630. if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
  3631. drm_dp_aux_unregister(&intel_dp->aux);
  3632. if (is_edp(intel_dp)) {
  3633. cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
  3634. drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
  3635. edp_panel_vdd_off_sync(intel_dp);
  3636. drm_modeset_unlock(&dev->mode_config.connection_mutex);
  3637. }
  3638. drm_sysfs_connector_remove(connector);
  3639. drm_connector_cleanup(connector);
  3640. return false;
  3641. }
  3642. intel_dp_add_properties(intel_dp, connector);
  3643. /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
  3644. * 0xd. Failure to do so will result in spurious interrupts being
  3645. * generated on the port when a cable is not attached.
  3646. */
  3647. if (IS_G4X(dev) && !IS_GM45(dev)) {
  3648. u32 temp = I915_READ(PEG_BAND_GAP_DATA);
  3649. I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
  3650. }
  3651. return true;
  3652. }
  3653. void
  3654. intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
  3655. {
  3656. struct intel_digital_port *intel_dig_port;
  3657. struct intel_encoder *intel_encoder;
  3658. struct drm_encoder *encoder;
  3659. struct intel_connector *intel_connector;
  3660. intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
  3661. if (!intel_dig_port)
  3662. return;
  3663. intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
  3664. if (!intel_connector) {
  3665. kfree(intel_dig_port);
  3666. return;
  3667. }
  3668. intel_encoder = &intel_dig_port->base;
  3669. encoder = &intel_encoder->base;
  3670. drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
  3671. DRM_MODE_ENCODER_TMDS);
  3672. intel_encoder->compute_config = intel_dp_compute_config;
  3673. intel_encoder->disable = intel_disable_dp;
  3674. intel_encoder->get_hw_state = intel_dp_get_hw_state;
  3675. intel_encoder->get_config = intel_dp_get_config;
  3676. if (IS_CHERRYVIEW(dev)) {
  3677. intel_encoder->pre_enable = chv_pre_enable_dp;
  3678. intel_encoder->enable = vlv_enable_dp;
  3679. intel_encoder->post_disable = chv_post_disable_dp;
  3680. } else if (IS_VALLEYVIEW(dev)) {
  3681. intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
  3682. intel_encoder->pre_enable = vlv_pre_enable_dp;
  3683. intel_encoder->enable = vlv_enable_dp;
  3684. intel_encoder->post_disable = vlv_post_disable_dp;
  3685. } else {
  3686. intel_encoder->pre_enable = g4x_pre_enable_dp;
  3687. intel_encoder->enable = g4x_enable_dp;
  3688. intel_encoder->post_disable = g4x_post_disable_dp;
  3689. }
  3690. intel_dig_port->port = port;
  3691. intel_dig_port->dp.output_reg = output_reg;
  3692. intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
  3693. if (IS_CHERRYVIEW(dev)) {
  3694. if (port == PORT_D)
  3695. intel_encoder->crtc_mask = 1 << 2;
  3696. else
  3697. intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
  3698. } else {
  3699. intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  3700. }
  3701. intel_encoder->cloneable = 0;
  3702. intel_encoder->hot_plug = intel_dp_hot_plug;
  3703. if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
  3704. drm_encoder_cleanup(encoder);
  3705. kfree(intel_dig_port);
  3706. kfree(intel_connector);
  3707. }
  3708. }