drm_dp_helper.c 20 KB

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  1. /*
  2. * Copyright © 2009 Keith Packard
  3. *
  4. * Permission to use, copy, modify, distribute, and sell this software and its
  5. * documentation for any purpose is hereby granted without fee, provided that
  6. * the above copyright notice appear in all copies and that both that copyright
  7. * notice and this permission notice appear in supporting documentation, and
  8. * that the name of the copyright holders not be used in advertising or
  9. * publicity pertaining to distribution of the software without specific,
  10. * written prior permission. The copyright holders make no representations
  11. * about the suitability of this software for any purpose. It is provided "as
  12. * is" without express or implied warranty.
  13. *
  14. * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
  15. * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
  16. * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
  17. * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
  18. * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  19. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
  20. * OF THIS SOFTWARE.
  21. */
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/delay.h>
  25. #include <linux/init.h>
  26. #include <linux/errno.h>
  27. #include <linux/sched.h>
  28. #include <linux/i2c.h>
  29. #include <drm/drm_dp_helper.h>
  30. #include <drm/drmP.h>
  31. /**
  32. * DOC: dp helpers
  33. *
  34. * These functions contain some common logic and helpers at various abstraction
  35. * levels to deal with Display Port sink devices and related things like DP aux
  36. * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
  37. * blocks, ...
  38. */
  39. /* Run a single AUX_CH I2C transaction, writing/reading data as necessary */
  40. static int
  41. i2c_algo_dp_aux_transaction(struct i2c_adapter *adapter, int mode,
  42. uint8_t write_byte, uint8_t *read_byte)
  43. {
  44. struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
  45. int ret;
  46. ret = (*algo_data->aux_ch)(adapter, mode,
  47. write_byte, read_byte);
  48. return ret;
  49. }
  50. /*
  51. * I2C over AUX CH
  52. */
  53. /*
  54. * Send the address. If the I2C link is running, this 'restarts'
  55. * the connection with the new address, this is used for doing
  56. * a write followed by a read (as needed for DDC)
  57. */
  58. static int
  59. i2c_algo_dp_aux_address(struct i2c_adapter *adapter, u16 address, bool reading)
  60. {
  61. struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
  62. int mode = MODE_I2C_START;
  63. int ret;
  64. if (reading)
  65. mode |= MODE_I2C_READ;
  66. else
  67. mode |= MODE_I2C_WRITE;
  68. algo_data->address = address;
  69. algo_data->running = true;
  70. ret = i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
  71. return ret;
  72. }
  73. /*
  74. * Stop the I2C transaction. This closes out the link, sending
  75. * a bare address packet with the MOT bit turned off
  76. */
  77. static void
  78. i2c_algo_dp_aux_stop(struct i2c_adapter *adapter, bool reading)
  79. {
  80. struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
  81. int mode = MODE_I2C_STOP;
  82. if (reading)
  83. mode |= MODE_I2C_READ;
  84. else
  85. mode |= MODE_I2C_WRITE;
  86. if (algo_data->running) {
  87. (void) i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
  88. algo_data->running = false;
  89. }
  90. }
  91. /*
  92. * Write a single byte to the current I2C address, the
  93. * the I2C link must be running or this returns -EIO
  94. */
  95. static int
  96. i2c_algo_dp_aux_put_byte(struct i2c_adapter *adapter, u8 byte)
  97. {
  98. struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
  99. int ret;
  100. if (!algo_data->running)
  101. return -EIO;
  102. ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_WRITE, byte, NULL);
  103. return ret;
  104. }
  105. /*
  106. * Read a single byte from the current I2C address, the
  107. * I2C link must be running or this returns -EIO
  108. */
  109. static int
  110. i2c_algo_dp_aux_get_byte(struct i2c_adapter *adapter, u8 *byte_ret)
  111. {
  112. struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
  113. int ret;
  114. if (!algo_data->running)
  115. return -EIO;
  116. ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_READ, 0, byte_ret);
  117. return ret;
  118. }
  119. static int
  120. i2c_algo_dp_aux_xfer(struct i2c_adapter *adapter,
  121. struct i2c_msg *msgs,
  122. int num)
  123. {
  124. int ret = 0;
  125. bool reading = false;
  126. int m;
  127. int b;
  128. for (m = 0; m < num; m++) {
  129. u16 len = msgs[m].len;
  130. u8 *buf = msgs[m].buf;
  131. reading = (msgs[m].flags & I2C_M_RD) != 0;
  132. ret = i2c_algo_dp_aux_address(adapter, msgs[m].addr, reading);
  133. if (ret < 0)
  134. break;
  135. if (reading) {
  136. for (b = 0; b < len; b++) {
  137. ret = i2c_algo_dp_aux_get_byte(adapter, &buf[b]);
  138. if (ret < 0)
  139. break;
  140. }
  141. } else {
  142. for (b = 0; b < len; b++) {
  143. ret = i2c_algo_dp_aux_put_byte(adapter, buf[b]);
  144. if (ret < 0)
  145. break;
  146. }
  147. }
  148. if (ret < 0)
  149. break;
  150. }
  151. if (ret >= 0)
  152. ret = num;
  153. i2c_algo_dp_aux_stop(adapter, reading);
  154. DRM_DEBUG_KMS("dp_aux_xfer return %d\n", ret);
  155. return ret;
  156. }
  157. static u32
  158. i2c_algo_dp_aux_functionality(struct i2c_adapter *adapter)
  159. {
  160. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
  161. I2C_FUNC_SMBUS_READ_BLOCK_DATA |
  162. I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
  163. I2C_FUNC_10BIT_ADDR;
  164. }
  165. static const struct i2c_algorithm i2c_dp_aux_algo = {
  166. .master_xfer = i2c_algo_dp_aux_xfer,
  167. .functionality = i2c_algo_dp_aux_functionality,
  168. };
  169. static void
  170. i2c_dp_aux_reset_bus(struct i2c_adapter *adapter)
  171. {
  172. (void) i2c_algo_dp_aux_address(adapter, 0, false);
  173. (void) i2c_algo_dp_aux_stop(adapter, false);
  174. }
  175. static int
  176. i2c_dp_aux_prepare_bus(struct i2c_adapter *adapter)
  177. {
  178. adapter->algo = &i2c_dp_aux_algo;
  179. adapter->retries = 3;
  180. i2c_dp_aux_reset_bus(adapter);
  181. return 0;
  182. }
  183. /**
  184. * i2c_dp_aux_add_bus() - register an i2c adapter using the aux ch helper
  185. * @adapter: i2c adapter to register
  186. *
  187. * This registers an i2c adapter that uses dp aux channel as it's underlaying
  188. * transport. The driver needs to fill out the &i2c_algo_dp_aux_data structure
  189. * and store it in the algo_data member of the @adapter argument. This will be
  190. * used by the i2c over dp aux algorithm to drive the hardware.
  191. *
  192. * RETURNS:
  193. * 0 on success, -ERRNO on failure.
  194. *
  195. * IMPORTANT:
  196. * This interface is deprecated, please switch to the new dp aux helpers and
  197. * drm_dp_aux_register().
  198. */
  199. int
  200. i2c_dp_aux_add_bus(struct i2c_adapter *adapter)
  201. {
  202. int error;
  203. error = i2c_dp_aux_prepare_bus(adapter);
  204. if (error)
  205. return error;
  206. error = i2c_add_adapter(adapter);
  207. return error;
  208. }
  209. EXPORT_SYMBOL(i2c_dp_aux_add_bus);
  210. /* Helpers for DP link training */
  211. static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
  212. {
  213. return link_status[r - DP_LANE0_1_STATUS];
  214. }
  215. static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
  216. int lane)
  217. {
  218. int i = DP_LANE0_1_STATUS + (lane >> 1);
  219. int s = (lane & 1) * 4;
  220. u8 l = dp_link_status(link_status, i);
  221. return (l >> s) & 0xf;
  222. }
  223. bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
  224. int lane_count)
  225. {
  226. u8 lane_align;
  227. u8 lane_status;
  228. int lane;
  229. lane_align = dp_link_status(link_status,
  230. DP_LANE_ALIGN_STATUS_UPDATED);
  231. if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
  232. return false;
  233. for (lane = 0; lane < lane_count; lane++) {
  234. lane_status = dp_get_lane_status(link_status, lane);
  235. if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
  236. return false;
  237. }
  238. return true;
  239. }
  240. EXPORT_SYMBOL(drm_dp_channel_eq_ok);
  241. bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
  242. int lane_count)
  243. {
  244. int lane;
  245. u8 lane_status;
  246. for (lane = 0; lane < lane_count; lane++) {
  247. lane_status = dp_get_lane_status(link_status, lane);
  248. if ((lane_status & DP_LANE_CR_DONE) == 0)
  249. return false;
  250. }
  251. return true;
  252. }
  253. EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
  254. u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
  255. int lane)
  256. {
  257. int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
  258. int s = ((lane & 1) ?
  259. DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
  260. DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
  261. u8 l = dp_link_status(link_status, i);
  262. return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
  263. }
  264. EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
  265. u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
  266. int lane)
  267. {
  268. int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
  269. int s = ((lane & 1) ?
  270. DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
  271. DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
  272. u8 l = dp_link_status(link_status, i);
  273. return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
  274. }
  275. EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
  276. void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
  277. if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
  278. udelay(100);
  279. else
  280. mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
  281. }
  282. EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
  283. void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
  284. if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
  285. udelay(400);
  286. else
  287. mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
  288. }
  289. EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
  290. u8 drm_dp_link_rate_to_bw_code(int link_rate)
  291. {
  292. switch (link_rate) {
  293. case 162000:
  294. default:
  295. return DP_LINK_BW_1_62;
  296. case 270000:
  297. return DP_LINK_BW_2_7;
  298. case 540000:
  299. return DP_LINK_BW_5_4;
  300. }
  301. }
  302. EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
  303. int drm_dp_bw_code_to_link_rate(u8 link_bw)
  304. {
  305. switch (link_bw) {
  306. case DP_LINK_BW_1_62:
  307. default:
  308. return 162000;
  309. case DP_LINK_BW_2_7:
  310. return 270000;
  311. case DP_LINK_BW_5_4:
  312. return 540000;
  313. }
  314. }
  315. EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
  316. /**
  317. * DOC: dp helpers
  318. *
  319. * The DisplayPort AUX channel is an abstraction to allow generic, driver-
  320. * independent access to AUX functionality. Drivers can take advantage of
  321. * this by filling in the fields of the drm_dp_aux structure.
  322. *
  323. * Transactions are described using a hardware-independent drm_dp_aux_msg
  324. * structure, which is passed into a driver's .transfer() implementation.
  325. * Both native and I2C-over-AUX transactions are supported.
  326. */
  327. static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
  328. unsigned int offset, void *buffer, size_t size)
  329. {
  330. struct drm_dp_aux_msg msg;
  331. unsigned int retry;
  332. int err;
  333. memset(&msg, 0, sizeof(msg));
  334. msg.address = offset;
  335. msg.request = request;
  336. msg.buffer = buffer;
  337. msg.size = size;
  338. /*
  339. * The specification doesn't give any recommendation on how often to
  340. * retry native transactions, so retry 7 times like for I2C-over-AUX
  341. * transactions.
  342. */
  343. for (retry = 0; retry < 7; retry++) {
  344. mutex_lock(&aux->hw_mutex);
  345. err = aux->transfer(aux, &msg);
  346. mutex_unlock(&aux->hw_mutex);
  347. if (err < 0) {
  348. if (err == -EBUSY)
  349. continue;
  350. return err;
  351. }
  352. switch (msg.reply & DP_AUX_NATIVE_REPLY_MASK) {
  353. case DP_AUX_NATIVE_REPLY_ACK:
  354. if (err < size)
  355. return -EPROTO;
  356. return err;
  357. case DP_AUX_NATIVE_REPLY_NACK:
  358. return -EIO;
  359. case DP_AUX_NATIVE_REPLY_DEFER:
  360. usleep_range(400, 500);
  361. break;
  362. }
  363. }
  364. DRM_DEBUG_KMS("too many retries, giving up\n");
  365. return -EIO;
  366. }
  367. /**
  368. * drm_dp_dpcd_read() - read a series of bytes from the DPCD
  369. * @aux: DisplayPort AUX channel
  370. * @offset: address of the (first) register to read
  371. * @buffer: buffer to store the register values
  372. * @size: number of bytes in @buffer
  373. *
  374. * Returns the number of bytes transferred on success, or a negative error
  375. * code on failure. -EIO is returned if the request was NAKed by the sink or
  376. * if the retry count was exceeded. If not all bytes were transferred, this
  377. * function returns -EPROTO. Errors from the underlying AUX channel transfer
  378. * function, with the exception of -EBUSY (which causes the transaction to
  379. * be retried), are propagated to the caller.
  380. */
  381. ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
  382. void *buffer, size_t size)
  383. {
  384. return drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, buffer,
  385. size);
  386. }
  387. EXPORT_SYMBOL(drm_dp_dpcd_read);
  388. /**
  389. * drm_dp_dpcd_write() - write a series of bytes to the DPCD
  390. * @aux: DisplayPort AUX channel
  391. * @offset: address of the (first) register to write
  392. * @buffer: buffer containing the values to write
  393. * @size: number of bytes in @buffer
  394. *
  395. * Returns the number of bytes transferred on success, or a negative error
  396. * code on failure. -EIO is returned if the request was NAKed by the sink or
  397. * if the retry count was exceeded. If not all bytes were transferred, this
  398. * function returns -EPROTO. Errors from the underlying AUX channel transfer
  399. * function, with the exception of -EBUSY (which causes the transaction to
  400. * be retried), are propagated to the caller.
  401. */
  402. ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
  403. void *buffer, size_t size)
  404. {
  405. return drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer,
  406. size);
  407. }
  408. EXPORT_SYMBOL(drm_dp_dpcd_write);
  409. /**
  410. * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
  411. * @aux: DisplayPort AUX channel
  412. * @status: buffer to store the link status in (must be at least 6 bytes)
  413. *
  414. * Returns the number of bytes transferred on success or a negative error
  415. * code on failure.
  416. */
  417. int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
  418. u8 status[DP_LINK_STATUS_SIZE])
  419. {
  420. return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
  421. DP_LINK_STATUS_SIZE);
  422. }
  423. EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
  424. /**
  425. * drm_dp_link_probe() - probe a DisplayPort link for capabilities
  426. * @aux: DisplayPort AUX channel
  427. * @link: pointer to structure in which to return link capabilities
  428. *
  429. * The structure filled in by this function can usually be passed directly
  430. * into drm_dp_link_power_up() and drm_dp_link_configure() to power up and
  431. * configure the link based on the link's capabilities.
  432. *
  433. * Returns 0 on success or a negative error code on failure.
  434. */
  435. int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
  436. {
  437. u8 values[3];
  438. int err;
  439. memset(link, 0, sizeof(*link));
  440. err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values));
  441. if (err < 0)
  442. return err;
  443. link->revision = values[0];
  444. link->rate = drm_dp_bw_code_to_link_rate(values[1]);
  445. link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
  446. if (values[2] & DP_ENHANCED_FRAME_CAP)
  447. link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING;
  448. return 0;
  449. }
  450. EXPORT_SYMBOL(drm_dp_link_probe);
  451. /**
  452. * drm_dp_link_power_up() - power up a DisplayPort link
  453. * @aux: DisplayPort AUX channel
  454. * @link: pointer to a structure containing the link configuration
  455. *
  456. * Returns 0 on success or a negative error code on failure.
  457. */
  458. int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link)
  459. {
  460. u8 value;
  461. int err;
  462. /* DP_SET_POWER register is only available on DPCD v1.1 and later */
  463. if (link->revision < 0x11)
  464. return 0;
  465. err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
  466. if (err < 0)
  467. return err;
  468. value &= ~DP_SET_POWER_MASK;
  469. value |= DP_SET_POWER_D0;
  470. err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
  471. if (err < 0)
  472. return err;
  473. /*
  474. * According to the DP 1.1 specification, a "Sink Device must exit the
  475. * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
  476. * Control Field" (register 0x600).
  477. */
  478. usleep_range(1000, 2000);
  479. return 0;
  480. }
  481. EXPORT_SYMBOL(drm_dp_link_power_up);
  482. /**
  483. * drm_dp_link_configure() - configure a DisplayPort link
  484. * @aux: DisplayPort AUX channel
  485. * @link: pointer to a structure containing the link configuration
  486. *
  487. * Returns 0 on success or a negative error code on failure.
  488. */
  489. int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
  490. {
  491. u8 values[2];
  492. int err;
  493. values[0] = drm_dp_link_rate_to_bw_code(link->rate);
  494. values[1] = link->num_lanes;
  495. if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
  496. values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
  497. err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
  498. if (err < 0)
  499. return err;
  500. return 0;
  501. }
  502. EXPORT_SYMBOL(drm_dp_link_configure);
  503. /*
  504. * I2C-over-AUX implementation
  505. */
  506. static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
  507. {
  508. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
  509. I2C_FUNC_SMBUS_READ_BLOCK_DATA |
  510. I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
  511. I2C_FUNC_10BIT_ADDR;
  512. }
  513. /*
  514. * Transfer a single I2C-over-AUX message and handle various error conditions,
  515. * retrying the transaction as appropriate. It is assumed that the
  516. * aux->transfer function does not modify anything in the msg other than the
  517. * reply field.
  518. */
  519. static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
  520. {
  521. unsigned int retry;
  522. int err;
  523. /*
  524. * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
  525. * is required to retry at least seven times upon receiving AUX_DEFER
  526. * before giving up the AUX transaction.
  527. */
  528. for (retry = 0; retry < 7; retry++) {
  529. mutex_lock(&aux->hw_mutex);
  530. err = aux->transfer(aux, msg);
  531. mutex_unlock(&aux->hw_mutex);
  532. if (err < 0) {
  533. if (err == -EBUSY)
  534. continue;
  535. DRM_DEBUG_KMS("transaction failed: %d\n", err);
  536. return err;
  537. }
  538. switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
  539. case DP_AUX_NATIVE_REPLY_ACK:
  540. /*
  541. * For I2C-over-AUX transactions this isn't enough, we
  542. * need to check for the I2C ACK reply.
  543. */
  544. break;
  545. case DP_AUX_NATIVE_REPLY_NACK:
  546. DRM_DEBUG_KMS("native nack\n");
  547. return -EREMOTEIO;
  548. case DP_AUX_NATIVE_REPLY_DEFER:
  549. DRM_DEBUG_KMS("native defer");
  550. /*
  551. * We could check for I2C bit rate capabilities and if
  552. * available adjust this interval. We could also be
  553. * more careful with DP-to-legacy adapters where a
  554. * long legacy cable may force very low I2C bit rates.
  555. *
  556. * For now just defer for long enough to hopefully be
  557. * safe for all use-cases.
  558. */
  559. usleep_range(500, 600);
  560. continue;
  561. default:
  562. DRM_ERROR("invalid native reply %#04x\n", msg->reply);
  563. return -EREMOTEIO;
  564. }
  565. switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
  566. case DP_AUX_I2C_REPLY_ACK:
  567. /*
  568. * Both native ACK and I2C ACK replies received. We
  569. * can assume the transfer was successful.
  570. */
  571. if (err < msg->size)
  572. return -EPROTO;
  573. return 0;
  574. case DP_AUX_I2C_REPLY_NACK:
  575. DRM_DEBUG_KMS("I2C nack\n");
  576. return -EREMOTEIO;
  577. case DP_AUX_I2C_REPLY_DEFER:
  578. DRM_DEBUG_KMS("I2C defer\n");
  579. usleep_range(400, 500);
  580. continue;
  581. default:
  582. DRM_ERROR("invalid I2C reply %#04x\n", msg->reply);
  583. return -EREMOTEIO;
  584. }
  585. }
  586. DRM_DEBUG_KMS("too many retries, giving up\n");
  587. return -EREMOTEIO;
  588. }
  589. static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
  590. int num)
  591. {
  592. struct drm_dp_aux *aux = adapter->algo_data;
  593. unsigned int i, j;
  594. struct drm_dp_aux_msg msg;
  595. int err = 0;
  596. memset(&msg, 0, sizeof(msg));
  597. for (i = 0; i < num; i++) {
  598. msg.address = msgs[i].addr;
  599. msg.request = (msgs[i].flags & I2C_M_RD) ?
  600. DP_AUX_I2C_READ :
  601. DP_AUX_I2C_WRITE;
  602. msg.request |= DP_AUX_I2C_MOT;
  603. /* Send a bare address packet to start the transaction.
  604. * Zero sized messages specify an address only (bare
  605. * address) transaction.
  606. */
  607. msg.buffer = NULL;
  608. msg.size = 0;
  609. err = drm_dp_i2c_do_msg(aux, &msg);
  610. if (err < 0)
  611. break;
  612. /*
  613. * Many hardware implementations support FIFOs larger than a
  614. * single byte, but it has been empirically determined that
  615. * transferring data in larger chunks can actually lead to
  616. * decreased performance. Therefore each message is simply
  617. * transferred byte-by-byte.
  618. */
  619. for (j = 0; j < msgs[i].len; j++) {
  620. msg.buffer = msgs[i].buf + j;
  621. msg.size = 1;
  622. err = drm_dp_i2c_do_msg(aux, &msg);
  623. if (err < 0)
  624. break;
  625. }
  626. if (err < 0)
  627. break;
  628. }
  629. if (err >= 0)
  630. err = num;
  631. /* Send a bare address packet to close out the transaction.
  632. * Zero sized messages specify an address only (bare
  633. * address) transaction.
  634. */
  635. msg.request &= ~DP_AUX_I2C_MOT;
  636. msg.buffer = NULL;
  637. msg.size = 0;
  638. (void)drm_dp_i2c_do_msg(aux, &msg);
  639. return err;
  640. }
  641. static const struct i2c_algorithm drm_dp_i2c_algo = {
  642. .functionality = drm_dp_i2c_functionality,
  643. .master_xfer = drm_dp_i2c_xfer,
  644. };
  645. /**
  646. * drm_dp_aux_register() - initialise and register aux channel
  647. * @aux: DisplayPort AUX channel
  648. *
  649. * Returns 0 on success or a negative error code on failure.
  650. */
  651. int drm_dp_aux_register(struct drm_dp_aux *aux)
  652. {
  653. mutex_init(&aux->hw_mutex);
  654. aux->ddc.algo = &drm_dp_i2c_algo;
  655. aux->ddc.algo_data = aux;
  656. aux->ddc.retries = 3;
  657. aux->ddc.class = I2C_CLASS_DDC;
  658. aux->ddc.owner = THIS_MODULE;
  659. aux->ddc.dev.parent = aux->dev;
  660. aux->ddc.dev.of_node = aux->dev->of_node;
  661. strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
  662. sizeof(aux->ddc.name));
  663. return i2c_add_adapter(&aux->ddc);
  664. }
  665. EXPORT_SYMBOL(drm_dp_aux_register);
  666. /**
  667. * drm_dp_aux_unregister() - unregister an AUX adapter
  668. * @aux: DisplayPort AUX channel
  669. */
  670. void drm_dp_aux_unregister(struct drm_dp_aux *aux)
  671. {
  672. i2c_del_adapter(&aux->ddc);
  673. }
  674. EXPORT_SYMBOL(drm_dp_aux_unregister);