ast_mode.c 33 KB

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  1. /*
  2. * Copyright 2012 Red Hat Inc.
  3. * Parts based on xf86-video-ast
  4. * Copyright (c) 2005 ASPEED Technology Inc.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sub license, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  18. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  19. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * The above copyright notice and this permission notice (including the
  23. * next paragraph) shall be included in all copies or substantial portions
  24. * of the Software.
  25. *
  26. */
  27. /*
  28. * Authors: Dave Airlie <airlied@redhat.com>
  29. */
  30. #include <linux/export.h>
  31. #include <drm/drmP.h>
  32. #include <drm/drm_crtc.h>
  33. #include <drm/drm_crtc_helper.h>
  34. #include "ast_drv.h"
  35. #include "ast_tables.h"
  36. static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);
  37. static void ast_i2c_destroy(struct ast_i2c_chan *i2c);
  38. static int ast_cursor_set(struct drm_crtc *crtc,
  39. struct drm_file *file_priv,
  40. uint32_t handle,
  41. uint32_t width,
  42. uint32_t height);
  43. static int ast_cursor_move(struct drm_crtc *crtc,
  44. int x, int y);
  45. static inline void ast_load_palette_index(struct ast_private *ast,
  46. u8 index, u8 red, u8 green,
  47. u8 blue)
  48. {
  49. ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index);
  50. ast_io_read8(ast, AST_IO_SEQ_PORT);
  51. ast_io_write8(ast, AST_IO_DAC_DATA, red);
  52. ast_io_read8(ast, AST_IO_SEQ_PORT);
  53. ast_io_write8(ast, AST_IO_DAC_DATA, green);
  54. ast_io_read8(ast, AST_IO_SEQ_PORT);
  55. ast_io_write8(ast, AST_IO_DAC_DATA, blue);
  56. ast_io_read8(ast, AST_IO_SEQ_PORT);
  57. }
  58. static void ast_crtc_load_lut(struct drm_crtc *crtc)
  59. {
  60. struct ast_private *ast = crtc->dev->dev_private;
  61. struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
  62. int i;
  63. if (!crtc->enabled)
  64. return;
  65. for (i = 0; i < 256; i++)
  66. ast_load_palette_index(ast, i, ast_crtc->lut_r[i],
  67. ast_crtc->lut_g[i], ast_crtc->lut_b[i]);
  68. }
  69. static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mode *mode,
  70. struct drm_display_mode *adjusted_mode,
  71. struct ast_vbios_mode_info *vbios_mode)
  72. {
  73. struct ast_private *ast = crtc->dev->dev_private;
  74. u32 refresh_rate_index = 0, mode_id, color_index, refresh_rate;
  75. u32 hborder, vborder;
  76. switch (crtc->primary->fb->bits_per_pixel) {
  77. case 8:
  78. vbios_mode->std_table = &vbios_stdtable[VGAModeIndex];
  79. color_index = VGAModeIndex - 1;
  80. break;
  81. case 16:
  82. vbios_mode->std_table = &vbios_stdtable[HiCModeIndex];
  83. color_index = HiCModeIndex;
  84. break;
  85. case 24:
  86. case 32:
  87. vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex];
  88. color_index = TrueCModeIndex;
  89. break;
  90. default:
  91. return false;
  92. }
  93. switch (crtc->mode.crtc_hdisplay) {
  94. case 640:
  95. vbios_mode->enh_table = &res_640x480[refresh_rate_index];
  96. break;
  97. case 800:
  98. vbios_mode->enh_table = &res_800x600[refresh_rate_index];
  99. break;
  100. case 1024:
  101. vbios_mode->enh_table = &res_1024x768[refresh_rate_index];
  102. break;
  103. case 1280:
  104. if (crtc->mode.crtc_vdisplay == 800)
  105. vbios_mode->enh_table = &res_1280x800[refresh_rate_index];
  106. else
  107. vbios_mode->enh_table = &res_1280x1024[refresh_rate_index];
  108. break;
  109. case 1360:
  110. vbios_mode->enh_table = &res_1360x768[refresh_rate_index];
  111. break;
  112. case 1440:
  113. vbios_mode->enh_table = &res_1440x900[refresh_rate_index];
  114. break;
  115. case 1600:
  116. if (crtc->mode.crtc_vdisplay == 900)
  117. vbios_mode->enh_table = &res_1600x900[refresh_rate_index];
  118. else
  119. vbios_mode->enh_table = &res_1600x1200[refresh_rate_index];
  120. break;
  121. case 1680:
  122. vbios_mode->enh_table = &res_1680x1050[refresh_rate_index];
  123. break;
  124. case 1920:
  125. if (crtc->mode.crtc_vdisplay == 1080)
  126. vbios_mode->enh_table = &res_1920x1080[refresh_rate_index];
  127. else
  128. vbios_mode->enh_table = &res_1920x1200[refresh_rate_index];
  129. break;
  130. default:
  131. return false;
  132. }
  133. refresh_rate = drm_mode_vrefresh(mode);
  134. while (vbios_mode->enh_table->refresh_rate < refresh_rate) {
  135. vbios_mode->enh_table++;
  136. if ((vbios_mode->enh_table->refresh_rate > refresh_rate) ||
  137. (vbios_mode->enh_table->refresh_rate == 0xff)) {
  138. vbios_mode->enh_table--;
  139. break;
  140. }
  141. }
  142. hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0;
  143. vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0;
  144. adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht;
  145. adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder;
  146. adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder;
  147. adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder +
  148. vbios_mode->enh_table->hfp;
  149. adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder +
  150. vbios_mode->enh_table->hfp +
  151. vbios_mode->enh_table->hsync);
  152. adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt;
  153. adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder;
  154. adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder;
  155. adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder +
  156. vbios_mode->enh_table->vfp;
  157. adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder +
  158. vbios_mode->enh_table->vfp +
  159. vbios_mode->enh_table->vsync);
  160. refresh_rate_index = vbios_mode->enh_table->refresh_rate_index;
  161. mode_id = vbios_mode->enh_table->mode_id;
  162. if (ast->chip == AST1180) {
  163. /* TODO 1180 */
  164. } else {
  165. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0xf) << 4));
  166. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff);
  167. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff);
  168. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
  169. if (vbios_mode->enh_table->flags & NewModeInfo) {
  170. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
  171. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, crtc->primary->fb->bits_per_pixel);
  172. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
  173. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay);
  174. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8);
  175. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay);
  176. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8);
  177. }
  178. }
  179. return true;
  180. }
  181. static void ast_set_std_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
  182. struct ast_vbios_mode_info *vbios_mode)
  183. {
  184. struct ast_private *ast = crtc->dev->dev_private;
  185. struct ast_vbios_stdtable *stdtable;
  186. u32 i;
  187. u8 jreg;
  188. stdtable = vbios_mode->std_table;
  189. jreg = stdtable->misc;
  190. ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
  191. /* Set SEQ */
  192. ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03);
  193. for (i = 0; i < 4; i++) {
  194. jreg = stdtable->seq[i];
  195. if (!i)
  196. jreg |= 0x20;
  197. ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg);
  198. }
  199. /* Set CRTC */
  200. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
  201. for (i = 0; i < 25; i++)
  202. ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
  203. /* set AR */
  204. jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
  205. for (i = 0; i < 20; i++) {
  206. jreg = stdtable->ar[i];
  207. ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i);
  208. ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg);
  209. }
  210. ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14);
  211. ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00);
  212. jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
  213. ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20);
  214. /* Set GR */
  215. for (i = 0; i < 9; i++)
  216. ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]);
  217. }
  218. static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
  219. struct ast_vbios_mode_info *vbios_mode)
  220. {
  221. struct ast_private *ast = crtc->dev->dev_private;
  222. u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0;
  223. u16 temp;
  224. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
  225. temp = (mode->crtc_htotal >> 3) - 5;
  226. if (temp & 0x100)
  227. jregAC |= 0x01; /* HT D[8] */
  228. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp);
  229. temp = (mode->crtc_hdisplay >> 3) - 1;
  230. if (temp & 0x100)
  231. jregAC |= 0x04; /* HDE D[8] */
  232. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp);
  233. temp = (mode->crtc_hblank_start >> 3) - 1;
  234. if (temp & 0x100)
  235. jregAC |= 0x10; /* HBS D[8] */
  236. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp);
  237. temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f;
  238. if (temp & 0x20)
  239. jreg05 |= 0x80; /* HBE D[5] */
  240. if (temp & 0x40)
  241. jregAD |= 0x01; /* HBE D[5] */
  242. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
  243. temp = (mode->crtc_hsync_start >> 3) - 1;
  244. if (temp & 0x100)
  245. jregAC |= 0x40; /* HRS D[5] */
  246. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
  247. temp = ((mode->crtc_hsync_end >> 3) - 1) & 0x3f;
  248. if (temp & 0x20)
  249. jregAD |= 0x04; /* HRE D[5] */
  250. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
  251. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC);
  252. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD);
  253. /* vert timings */
  254. temp = (mode->crtc_vtotal) - 2;
  255. if (temp & 0x100)
  256. jreg07 |= 0x01;
  257. if (temp & 0x200)
  258. jreg07 |= 0x20;
  259. if (temp & 0x400)
  260. jregAE |= 0x01;
  261. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp);
  262. temp = (mode->crtc_vsync_start) - 1;
  263. if (temp & 0x100)
  264. jreg07 |= 0x04;
  265. if (temp & 0x200)
  266. jreg07 |= 0x80;
  267. if (temp & 0x400)
  268. jregAE |= 0x08;
  269. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp);
  270. temp = (mode->crtc_vsync_end - 1) & 0x3f;
  271. if (temp & 0x10)
  272. jregAE |= 0x20;
  273. if (temp & 0x20)
  274. jregAE |= 0x40;
  275. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf);
  276. temp = mode->crtc_vdisplay - 1;
  277. if (temp & 0x100)
  278. jreg07 |= 0x02;
  279. if (temp & 0x200)
  280. jreg07 |= 0x40;
  281. if (temp & 0x400)
  282. jregAE |= 0x02;
  283. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp);
  284. temp = mode->crtc_vblank_start - 1;
  285. if (temp & 0x100)
  286. jreg07 |= 0x08;
  287. if (temp & 0x200)
  288. jreg09 |= 0x20;
  289. if (temp & 0x400)
  290. jregAE |= 0x04;
  291. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp);
  292. temp = mode->crtc_vblank_end - 1;
  293. if (temp & 0x100)
  294. jregAE |= 0x10;
  295. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp);
  296. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07);
  297. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
  298. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
  299. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
  300. }
  301. static void ast_set_offset_reg(struct drm_crtc *crtc)
  302. {
  303. struct ast_private *ast = crtc->dev->dev_private;
  304. u16 offset;
  305. offset = crtc->primary->fb->pitches[0] >> 3;
  306. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff));
  307. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f);
  308. }
  309. static void ast_set_dclk_reg(struct drm_device *dev, struct drm_display_mode *mode,
  310. struct ast_vbios_mode_info *vbios_mode)
  311. {
  312. struct ast_private *ast = dev->dev_private;
  313. struct ast_vbios_dclk_info *clk_info;
  314. clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
  315. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
  316. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
  317. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
  318. (clk_info->param3 & 0x80) | ((clk_info->param3 & 0x3) << 4));
  319. }
  320. static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
  321. struct ast_vbios_mode_info *vbios_mode)
  322. {
  323. struct ast_private *ast = crtc->dev->dev_private;
  324. u8 jregA0 = 0, jregA3 = 0, jregA8 = 0;
  325. switch (crtc->primary->fb->bits_per_pixel) {
  326. case 8:
  327. jregA0 = 0x70;
  328. jregA3 = 0x01;
  329. jregA8 = 0x00;
  330. break;
  331. case 15:
  332. case 16:
  333. jregA0 = 0x70;
  334. jregA3 = 0x04;
  335. jregA8 = 0x02;
  336. break;
  337. case 32:
  338. jregA0 = 0x70;
  339. jregA3 = 0x08;
  340. jregA8 = 0x02;
  341. break;
  342. }
  343. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0);
  344. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3);
  345. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
  346. /* Set Threshold */
  347. if (ast->chip == AST2300 || ast->chip == AST2400) {
  348. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
  349. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
  350. } else if (ast->chip == AST2100 ||
  351. ast->chip == AST1100 ||
  352. ast->chip == AST2200 ||
  353. ast->chip == AST2150) {
  354. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f);
  355. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f);
  356. } else {
  357. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f);
  358. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f);
  359. }
  360. }
  361. static void ast_set_sync_reg(struct drm_device *dev, struct drm_display_mode *mode,
  362. struct ast_vbios_mode_info *vbios_mode)
  363. {
  364. struct ast_private *ast = dev->dev_private;
  365. u8 jreg;
  366. jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ);
  367. jreg |= (vbios_mode->enh_table->flags & SyncNN);
  368. ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
  369. }
  370. static bool ast_set_dac_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
  371. struct ast_vbios_mode_info *vbios_mode)
  372. {
  373. switch (crtc->primary->fb->bits_per_pixel) {
  374. case 8:
  375. break;
  376. default:
  377. return false;
  378. }
  379. return true;
  380. }
  381. static void ast_set_start_address_crt1(struct drm_crtc *crtc, unsigned offset)
  382. {
  383. struct ast_private *ast = crtc->dev->dev_private;
  384. u32 addr;
  385. addr = offset >> 2;
  386. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff));
  387. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff));
  388. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff));
  389. }
  390. static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)
  391. {
  392. struct ast_private *ast = crtc->dev->dev_private;
  393. if (ast->chip == AST1180)
  394. return;
  395. switch (mode) {
  396. case DRM_MODE_DPMS_ON:
  397. case DRM_MODE_DPMS_STANDBY:
  398. case DRM_MODE_DPMS_SUSPEND:
  399. ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
  400. if (ast->tx_chip_type == AST_TX_DP501)
  401. ast_set_dp501_video_output(crtc->dev, 1);
  402. ast_crtc_load_lut(crtc);
  403. break;
  404. case DRM_MODE_DPMS_OFF:
  405. if (ast->tx_chip_type == AST_TX_DP501)
  406. ast_set_dp501_video_output(crtc->dev, 0);
  407. ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
  408. break;
  409. }
  410. }
  411. static bool ast_crtc_mode_fixup(struct drm_crtc *crtc,
  412. const struct drm_display_mode *mode,
  413. struct drm_display_mode *adjusted_mode)
  414. {
  415. return true;
  416. }
  417. /* ast is different - we will force move buffers out of VRAM */
  418. static int ast_crtc_do_set_base(struct drm_crtc *crtc,
  419. struct drm_framebuffer *fb,
  420. int x, int y, int atomic)
  421. {
  422. struct ast_private *ast = crtc->dev->dev_private;
  423. struct drm_gem_object *obj;
  424. struct ast_framebuffer *ast_fb;
  425. struct ast_bo *bo;
  426. int ret;
  427. u64 gpu_addr;
  428. /* push the previous fb to system ram */
  429. if (!atomic && fb) {
  430. ast_fb = to_ast_framebuffer(fb);
  431. obj = ast_fb->obj;
  432. bo = gem_to_ast_bo(obj);
  433. ret = ast_bo_reserve(bo, false);
  434. if (ret)
  435. return ret;
  436. ast_bo_push_sysram(bo);
  437. ast_bo_unreserve(bo);
  438. }
  439. ast_fb = to_ast_framebuffer(crtc->primary->fb);
  440. obj = ast_fb->obj;
  441. bo = gem_to_ast_bo(obj);
  442. ret = ast_bo_reserve(bo, false);
  443. if (ret)
  444. return ret;
  445. ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
  446. if (ret) {
  447. ast_bo_unreserve(bo);
  448. return ret;
  449. }
  450. if (&ast->fbdev->afb == ast_fb) {
  451. /* if pushing console in kmap it */
  452. ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
  453. if (ret)
  454. DRM_ERROR("failed to kmap fbcon\n");
  455. }
  456. ast_bo_unreserve(bo);
  457. ast_set_start_address_crt1(crtc, (u32)gpu_addr);
  458. return 0;
  459. }
  460. static int ast_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
  461. struct drm_framebuffer *old_fb)
  462. {
  463. return ast_crtc_do_set_base(crtc, old_fb, x, y, 0);
  464. }
  465. static int ast_crtc_mode_set(struct drm_crtc *crtc,
  466. struct drm_display_mode *mode,
  467. struct drm_display_mode *adjusted_mode,
  468. int x, int y,
  469. struct drm_framebuffer *old_fb)
  470. {
  471. struct drm_device *dev = crtc->dev;
  472. struct ast_private *ast = crtc->dev->dev_private;
  473. struct ast_vbios_mode_info vbios_mode;
  474. bool ret;
  475. if (ast->chip == AST1180) {
  476. DRM_ERROR("AST 1180 modesetting not supported\n");
  477. return -EINVAL;
  478. }
  479. ret = ast_get_vbios_mode_info(crtc, mode, adjusted_mode, &vbios_mode);
  480. if (ret == false)
  481. return -EINVAL;
  482. ast_open_key(ast);
  483. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04);
  484. ast_set_std_reg(crtc, adjusted_mode, &vbios_mode);
  485. ast_set_crtc_reg(crtc, adjusted_mode, &vbios_mode);
  486. ast_set_offset_reg(crtc);
  487. ast_set_dclk_reg(dev, adjusted_mode, &vbios_mode);
  488. ast_set_ext_reg(crtc, adjusted_mode, &vbios_mode);
  489. ast_set_sync_reg(dev, adjusted_mode, &vbios_mode);
  490. ast_set_dac_reg(crtc, adjusted_mode, &vbios_mode);
  491. ast_crtc_mode_set_base(crtc, x, y, old_fb);
  492. return 0;
  493. }
  494. static void ast_crtc_disable(struct drm_crtc *crtc)
  495. {
  496. }
  497. static void ast_crtc_prepare(struct drm_crtc *crtc)
  498. {
  499. }
  500. static void ast_crtc_commit(struct drm_crtc *crtc)
  501. {
  502. struct ast_private *ast = crtc->dev->dev_private;
  503. ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
  504. }
  505. static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = {
  506. .dpms = ast_crtc_dpms,
  507. .mode_fixup = ast_crtc_mode_fixup,
  508. .mode_set = ast_crtc_mode_set,
  509. .mode_set_base = ast_crtc_mode_set_base,
  510. .disable = ast_crtc_disable,
  511. .load_lut = ast_crtc_load_lut,
  512. .prepare = ast_crtc_prepare,
  513. .commit = ast_crtc_commit,
  514. };
  515. static void ast_crtc_reset(struct drm_crtc *crtc)
  516. {
  517. }
  518. static void ast_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  519. u16 *blue, uint32_t start, uint32_t size)
  520. {
  521. struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
  522. int end = (start + size > 256) ? 256 : start + size, i;
  523. /* userspace palettes are always correct as is */
  524. for (i = start; i < end; i++) {
  525. ast_crtc->lut_r[i] = red[i] >> 8;
  526. ast_crtc->lut_g[i] = green[i] >> 8;
  527. ast_crtc->lut_b[i] = blue[i] >> 8;
  528. }
  529. ast_crtc_load_lut(crtc);
  530. }
  531. static void ast_crtc_destroy(struct drm_crtc *crtc)
  532. {
  533. drm_crtc_cleanup(crtc);
  534. kfree(crtc);
  535. }
  536. static const struct drm_crtc_funcs ast_crtc_funcs = {
  537. .cursor_set = ast_cursor_set,
  538. .cursor_move = ast_cursor_move,
  539. .reset = ast_crtc_reset,
  540. .set_config = drm_crtc_helper_set_config,
  541. .gamma_set = ast_crtc_gamma_set,
  542. .destroy = ast_crtc_destroy,
  543. };
  544. static int ast_crtc_init(struct drm_device *dev)
  545. {
  546. struct ast_crtc *crtc;
  547. int i;
  548. crtc = kzalloc(sizeof(struct ast_crtc), GFP_KERNEL);
  549. if (!crtc)
  550. return -ENOMEM;
  551. drm_crtc_init(dev, &crtc->base, &ast_crtc_funcs);
  552. drm_mode_crtc_set_gamma_size(&crtc->base, 256);
  553. drm_crtc_helper_add(&crtc->base, &ast_crtc_helper_funcs);
  554. for (i = 0; i < 256; i++) {
  555. crtc->lut_r[i] = i;
  556. crtc->lut_g[i] = i;
  557. crtc->lut_b[i] = i;
  558. }
  559. return 0;
  560. }
  561. static void ast_encoder_destroy(struct drm_encoder *encoder)
  562. {
  563. drm_encoder_cleanup(encoder);
  564. kfree(encoder);
  565. }
  566. static struct drm_encoder *ast_best_single_encoder(struct drm_connector *connector)
  567. {
  568. int enc_id = connector->encoder_ids[0];
  569. struct drm_mode_object *obj;
  570. struct drm_encoder *encoder;
  571. /* pick the encoder ids */
  572. if (enc_id) {
  573. obj = drm_mode_object_find(connector->dev, enc_id, DRM_MODE_OBJECT_ENCODER);
  574. if (!obj)
  575. return NULL;
  576. encoder = obj_to_encoder(obj);
  577. return encoder;
  578. }
  579. return NULL;
  580. }
  581. static const struct drm_encoder_funcs ast_enc_funcs = {
  582. .destroy = ast_encoder_destroy,
  583. };
  584. static void ast_encoder_dpms(struct drm_encoder *encoder, int mode)
  585. {
  586. }
  587. static bool ast_mode_fixup(struct drm_encoder *encoder,
  588. const struct drm_display_mode *mode,
  589. struct drm_display_mode *adjusted_mode)
  590. {
  591. return true;
  592. }
  593. static void ast_encoder_mode_set(struct drm_encoder *encoder,
  594. struct drm_display_mode *mode,
  595. struct drm_display_mode *adjusted_mode)
  596. {
  597. }
  598. static void ast_encoder_prepare(struct drm_encoder *encoder)
  599. {
  600. }
  601. static void ast_encoder_commit(struct drm_encoder *encoder)
  602. {
  603. }
  604. static const struct drm_encoder_helper_funcs ast_enc_helper_funcs = {
  605. .dpms = ast_encoder_dpms,
  606. .mode_fixup = ast_mode_fixup,
  607. .prepare = ast_encoder_prepare,
  608. .commit = ast_encoder_commit,
  609. .mode_set = ast_encoder_mode_set,
  610. };
  611. static int ast_encoder_init(struct drm_device *dev)
  612. {
  613. struct ast_encoder *ast_encoder;
  614. ast_encoder = kzalloc(sizeof(struct ast_encoder), GFP_KERNEL);
  615. if (!ast_encoder)
  616. return -ENOMEM;
  617. drm_encoder_init(dev, &ast_encoder->base, &ast_enc_funcs,
  618. DRM_MODE_ENCODER_DAC);
  619. drm_encoder_helper_add(&ast_encoder->base, &ast_enc_helper_funcs);
  620. ast_encoder->base.possible_crtcs = 1;
  621. return 0;
  622. }
  623. static int ast_get_modes(struct drm_connector *connector)
  624. {
  625. struct ast_connector *ast_connector = to_ast_connector(connector);
  626. struct ast_private *ast = connector->dev->dev_private;
  627. struct edid *edid;
  628. int ret;
  629. bool flags = false;
  630. if (ast->tx_chip_type == AST_TX_DP501) {
  631. ast->dp501_maxclk = 0xff;
  632. edid = kmalloc(128, GFP_KERNEL);
  633. if (!edid)
  634. return -ENOMEM;
  635. flags = ast_dp501_read_edid(connector->dev, (u8 *)edid);
  636. if (flags)
  637. ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
  638. else
  639. kfree(edid);
  640. }
  641. if (!flags)
  642. edid = drm_get_edid(connector, &ast_connector->i2c->adapter);
  643. if (edid) {
  644. drm_mode_connector_update_edid_property(&ast_connector->base, edid);
  645. ret = drm_add_edid_modes(connector, edid);
  646. kfree(edid);
  647. return ret;
  648. } else
  649. drm_mode_connector_update_edid_property(&ast_connector->base, NULL);
  650. return 0;
  651. }
  652. static int ast_mode_valid(struct drm_connector *connector,
  653. struct drm_display_mode *mode)
  654. {
  655. struct ast_private *ast = connector->dev->dev_private;
  656. int flags = MODE_NOMODE;
  657. uint32_t jtemp;
  658. if (ast->support_wide_screen) {
  659. if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050))
  660. return MODE_OK;
  661. if ((mode->hdisplay == 1280) && (mode->vdisplay == 800))
  662. return MODE_OK;
  663. if ((mode->hdisplay == 1440) && (mode->vdisplay == 900))
  664. return MODE_OK;
  665. if ((mode->hdisplay == 1360) && (mode->vdisplay == 768))
  666. return MODE_OK;
  667. if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
  668. return MODE_OK;
  669. if ((ast->chip == AST2100) || (ast->chip == AST2200) || (ast->chip == AST2300) || (ast->chip == AST2400) || (ast->chip == AST1180)) {
  670. if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
  671. return MODE_OK;
  672. if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) {
  673. jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
  674. if (jtemp & 0x01)
  675. return MODE_NOMODE;
  676. else
  677. return MODE_OK;
  678. }
  679. }
  680. }
  681. switch (mode->hdisplay) {
  682. case 640:
  683. if (mode->vdisplay == 480) flags = MODE_OK;
  684. break;
  685. case 800:
  686. if (mode->vdisplay == 600) flags = MODE_OK;
  687. break;
  688. case 1024:
  689. if (mode->vdisplay == 768) flags = MODE_OK;
  690. break;
  691. case 1280:
  692. if (mode->vdisplay == 1024) flags = MODE_OK;
  693. break;
  694. case 1600:
  695. if (mode->vdisplay == 1200) flags = MODE_OK;
  696. break;
  697. default:
  698. return flags;
  699. }
  700. return flags;
  701. }
  702. static void ast_connector_destroy(struct drm_connector *connector)
  703. {
  704. struct ast_connector *ast_connector = to_ast_connector(connector);
  705. ast_i2c_destroy(ast_connector->i2c);
  706. drm_sysfs_connector_remove(connector);
  707. drm_connector_cleanup(connector);
  708. kfree(connector);
  709. }
  710. static enum drm_connector_status
  711. ast_connector_detect(struct drm_connector *connector, bool force)
  712. {
  713. return connector_status_connected;
  714. }
  715. static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
  716. .mode_valid = ast_mode_valid,
  717. .get_modes = ast_get_modes,
  718. .best_encoder = ast_best_single_encoder,
  719. };
  720. static const struct drm_connector_funcs ast_connector_funcs = {
  721. .dpms = drm_helper_connector_dpms,
  722. .detect = ast_connector_detect,
  723. .fill_modes = drm_helper_probe_single_connector_modes,
  724. .destroy = ast_connector_destroy,
  725. };
  726. static int ast_connector_init(struct drm_device *dev)
  727. {
  728. struct ast_connector *ast_connector;
  729. struct drm_connector *connector;
  730. struct drm_encoder *encoder;
  731. ast_connector = kzalloc(sizeof(struct ast_connector), GFP_KERNEL);
  732. if (!ast_connector)
  733. return -ENOMEM;
  734. connector = &ast_connector->base;
  735. drm_connector_init(dev, connector, &ast_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  736. drm_connector_helper_add(connector, &ast_connector_helper_funcs);
  737. connector->interlace_allowed = 0;
  738. connector->doublescan_allowed = 0;
  739. drm_sysfs_connector_add(connector);
  740. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  741. encoder = list_first_entry(&dev->mode_config.encoder_list, struct drm_encoder, head);
  742. drm_mode_connector_attach_encoder(connector, encoder);
  743. ast_connector->i2c = ast_i2c_create(dev);
  744. if (!ast_connector->i2c)
  745. DRM_ERROR("failed to add ddc bus for connector\n");
  746. return 0;
  747. }
  748. /* allocate cursor cache and pin at start of VRAM */
  749. static int ast_cursor_init(struct drm_device *dev)
  750. {
  751. struct ast_private *ast = dev->dev_private;
  752. int size;
  753. int ret;
  754. struct drm_gem_object *obj;
  755. struct ast_bo *bo;
  756. uint64_t gpu_addr;
  757. size = (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE) * AST_DEFAULT_HWC_NUM;
  758. ret = ast_gem_create(dev, size, true, &obj);
  759. if (ret)
  760. return ret;
  761. bo = gem_to_ast_bo(obj);
  762. ret = ast_bo_reserve(bo, false);
  763. if (unlikely(ret != 0))
  764. goto fail;
  765. ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
  766. ast_bo_unreserve(bo);
  767. if (ret)
  768. goto fail;
  769. /* kmap the object */
  770. ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &ast->cache_kmap);
  771. if (ret)
  772. goto fail;
  773. ast->cursor_cache = obj;
  774. ast->cursor_cache_gpu_addr = gpu_addr;
  775. DRM_DEBUG_KMS("pinned cursor cache at %llx\n", ast->cursor_cache_gpu_addr);
  776. return 0;
  777. fail:
  778. return ret;
  779. }
  780. static void ast_cursor_fini(struct drm_device *dev)
  781. {
  782. struct ast_private *ast = dev->dev_private;
  783. ttm_bo_kunmap(&ast->cache_kmap);
  784. drm_gem_object_unreference_unlocked(ast->cursor_cache);
  785. }
  786. int ast_mode_init(struct drm_device *dev)
  787. {
  788. ast_cursor_init(dev);
  789. ast_crtc_init(dev);
  790. ast_encoder_init(dev);
  791. ast_connector_init(dev);
  792. return 0;
  793. }
  794. void ast_mode_fini(struct drm_device *dev)
  795. {
  796. ast_cursor_fini(dev);
  797. }
  798. static int get_clock(void *i2c_priv)
  799. {
  800. struct ast_i2c_chan *i2c = i2c_priv;
  801. struct ast_private *ast = i2c->dev->dev_private;
  802. uint32_t val;
  803. val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4;
  804. return val & 1 ? 1 : 0;
  805. }
  806. static int get_data(void *i2c_priv)
  807. {
  808. struct ast_i2c_chan *i2c = i2c_priv;
  809. struct ast_private *ast = i2c->dev->dev_private;
  810. uint32_t val;
  811. val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5;
  812. return val & 1 ? 1 : 0;
  813. }
  814. static void set_clock(void *i2c_priv, int clock)
  815. {
  816. struct ast_i2c_chan *i2c = i2c_priv;
  817. struct ast_private *ast = i2c->dev->dev_private;
  818. int i;
  819. u8 ujcrb7, jtemp;
  820. for (i = 0; i < 0x10000; i++) {
  821. ujcrb7 = ((clock & 0x01) ? 0 : 1);
  822. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfe, ujcrb7);
  823. jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01);
  824. if (ujcrb7 == jtemp)
  825. break;
  826. }
  827. }
  828. static void set_data(void *i2c_priv, int data)
  829. {
  830. struct ast_i2c_chan *i2c = i2c_priv;
  831. struct ast_private *ast = i2c->dev->dev_private;
  832. int i;
  833. u8 ujcrb7, jtemp;
  834. for (i = 0; i < 0x10000; i++) {
  835. ujcrb7 = ((data & 0x01) ? 0 : 1) << 2;
  836. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfb, ujcrb7);
  837. jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04);
  838. if (ujcrb7 == jtemp)
  839. break;
  840. }
  841. }
  842. static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev)
  843. {
  844. struct ast_i2c_chan *i2c;
  845. int ret;
  846. i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL);
  847. if (!i2c)
  848. return NULL;
  849. i2c->adapter.owner = THIS_MODULE;
  850. i2c->adapter.class = I2C_CLASS_DDC;
  851. i2c->adapter.dev.parent = &dev->pdev->dev;
  852. i2c->dev = dev;
  853. i2c_set_adapdata(&i2c->adapter, i2c);
  854. snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
  855. "AST i2c bit bus");
  856. i2c->adapter.algo_data = &i2c->bit;
  857. i2c->bit.udelay = 20;
  858. i2c->bit.timeout = 2;
  859. i2c->bit.data = i2c;
  860. i2c->bit.setsda = set_data;
  861. i2c->bit.setscl = set_clock;
  862. i2c->bit.getsda = get_data;
  863. i2c->bit.getscl = get_clock;
  864. ret = i2c_bit_add_bus(&i2c->adapter);
  865. if (ret) {
  866. DRM_ERROR("Failed to register bit i2c\n");
  867. goto out_free;
  868. }
  869. return i2c;
  870. out_free:
  871. kfree(i2c);
  872. return NULL;
  873. }
  874. static void ast_i2c_destroy(struct ast_i2c_chan *i2c)
  875. {
  876. if (!i2c)
  877. return;
  878. i2c_del_adapter(&i2c->adapter);
  879. kfree(i2c);
  880. }
  881. static void ast_show_cursor(struct drm_crtc *crtc)
  882. {
  883. struct ast_private *ast = crtc->dev->dev_private;
  884. u8 jreg;
  885. jreg = 0x2;
  886. /* enable ARGB cursor */
  887. jreg |= 1;
  888. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg);
  889. }
  890. static void ast_hide_cursor(struct drm_crtc *crtc)
  891. {
  892. struct ast_private *ast = crtc->dev->dev_private;
  893. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00);
  894. }
  895. static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height)
  896. {
  897. union {
  898. u32 ul;
  899. u8 b[4];
  900. } srcdata32[2], data32;
  901. union {
  902. u16 us;
  903. u8 b[2];
  904. } data16;
  905. u32 csum = 0;
  906. s32 alpha_dst_delta, last_alpha_dst_delta;
  907. u8 *srcxor, *dstxor;
  908. int i, j;
  909. u32 per_pixel_copy, two_pixel_copy;
  910. alpha_dst_delta = AST_MAX_HWC_WIDTH << 1;
  911. last_alpha_dst_delta = alpha_dst_delta - (width << 1);
  912. srcxor = src;
  913. dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta;
  914. per_pixel_copy = width & 1;
  915. two_pixel_copy = width >> 1;
  916. for (j = 0; j < height; j++) {
  917. for (i = 0; i < two_pixel_copy; i++) {
  918. srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
  919. srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0;
  920. data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
  921. data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
  922. data32.b[2] = srcdata32[0].b[1] | (srcdata32[1].b[0] >> 4);
  923. data32.b[3] = srcdata32[0].b[3] | (srcdata32[1].b[2] >> 4);
  924. writel(data32.ul, dstxor);
  925. csum += data32.ul;
  926. dstxor += 4;
  927. srcxor += 8;
  928. }
  929. for (i = 0; i < per_pixel_copy; i++) {
  930. srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
  931. data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
  932. data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
  933. writew(data16.us, dstxor);
  934. csum += (u32)data16.us;
  935. dstxor += 2;
  936. srcxor += 4;
  937. }
  938. dstxor += last_alpha_dst_delta;
  939. }
  940. return csum;
  941. }
  942. static int ast_cursor_set(struct drm_crtc *crtc,
  943. struct drm_file *file_priv,
  944. uint32_t handle,
  945. uint32_t width,
  946. uint32_t height)
  947. {
  948. struct ast_private *ast = crtc->dev->dev_private;
  949. struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
  950. struct drm_gem_object *obj;
  951. struct ast_bo *bo;
  952. uint64_t gpu_addr;
  953. u32 csum;
  954. int ret;
  955. struct ttm_bo_kmap_obj uobj_map;
  956. u8 *src, *dst;
  957. bool src_isiomem, dst_isiomem;
  958. if (!handle) {
  959. ast_hide_cursor(crtc);
  960. return 0;
  961. }
  962. if (width > AST_MAX_HWC_WIDTH || height > AST_MAX_HWC_HEIGHT)
  963. return -EINVAL;
  964. obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
  965. if (!obj) {
  966. DRM_ERROR("Cannot find cursor object %x for crtc\n", handle);
  967. return -ENOENT;
  968. }
  969. bo = gem_to_ast_bo(obj);
  970. ret = ast_bo_reserve(bo, false);
  971. if (ret)
  972. goto fail;
  973. ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &uobj_map);
  974. src = ttm_kmap_obj_virtual(&uobj_map, &src_isiomem);
  975. dst = ttm_kmap_obj_virtual(&ast->cache_kmap, &dst_isiomem);
  976. if (src_isiomem == true)
  977. DRM_ERROR("src cursor bo should be in main memory\n");
  978. if (dst_isiomem == false)
  979. DRM_ERROR("dst bo should be in VRAM\n");
  980. dst += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor;
  981. /* do data transfer to cursor cache */
  982. csum = copy_cursor_image(src, dst, width, height);
  983. /* write checksum + signature */
  984. ttm_bo_kunmap(&uobj_map);
  985. ast_bo_unreserve(bo);
  986. {
  987. u8 *dst = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE;
  988. writel(csum, dst);
  989. writel(width, dst + AST_HWC_SIGNATURE_SizeX);
  990. writel(height, dst + AST_HWC_SIGNATURE_SizeY);
  991. writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX);
  992. writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY);
  993. /* set pattern offset */
  994. gpu_addr = ast->cursor_cache_gpu_addr;
  995. gpu_addr += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor;
  996. gpu_addr >>= 3;
  997. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, gpu_addr & 0xff);
  998. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, (gpu_addr >> 8) & 0xff);
  999. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, (gpu_addr >> 16) & 0xff);
  1000. }
  1001. ast_crtc->cursor_width = width;
  1002. ast_crtc->cursor_height = height;
  1003. ast_crtc->offset_x = AST_MAX_HWC_WIDTH - width;
  1004. ast_crtc->offset_y = AST_MAX_HWC_WIDTH - height;
  1005. ast->next_cursor = (ast->next_cursor + 1) % AST_DEFAULT_HWC_NUM;
  1006. ast_show_cursor(crtc);
  1007. drm_gem_object_unreference_unlocked(obj);
  1008. return 0;
  1009. fail:
  1010. drm_gem_object_unreference_unlocked(obj);
  1011. return ret;
  1012. }
  1013. static int ast_cursor_move(struct drm_crtc *crtc,
  1014. int x, int y)
  1015. {
  1016. struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
  1017. struct ast_private *ast = crtc->dev->dev_private;
  1018. int x_offset, y_offset;
  1019. u8 *sig;
  1020. sig = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE;
  1021. writel(x, sig + AST_HWC_SIGNATURE_X);
  1022. writel(y, sig + AST_HWC_SIGNATURE_Y);
  1023. x_offset = ast_crtc->offset_x;
  1024. y_offset = ast_crtc->offset_y;
  1025. if (x < 0) {
  1026. x_offset = (-x) + ast_crtc->offset_x;
  1027. x = 0;
  1028. }
  1029. if (y < 0) {
  1030. y_offset = (-y) + ast_crtc->offset_y;
  1031. y = 0;
  1032. }
  1033. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset);
  1034. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset);
  1035. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff));
  1036. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f));
  1037. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff));
  1038. ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07));
  1039. /* dummy write to fire HWC */
  1040. ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xCB, 0xFF, 0x00);
  1041. return 0;
  1042. }