gpio-sx150x.c 15 KB

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  1. /* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. * You should have received a copy of the GNU General Public License
  13. * along with this program; if not, write to the Free Software
  14. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  15. * 02110-1301, USA.
  16. */
  17. #include <linux/gpio.h>
  18. #include <linux/i2c.h>
  19. #include <linux/init.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/irq.h>
  22. #include <linux/module.h>
  23. #include <linux/mutex.h>
  24. #include <linux/slab.h>
  25. #include <linux/i2c/sx150x.h>
  26. #define NO_UPDATE_PENDING -1
  27. struct sx150x_device_data {
  28. u8 reg_pullup;
  29. u8 reg_pulldn;
  30. u8 reg_drain;
  31. u8 reg_polarity;
  32. u8 reg_dir;
  33. u8 reg_data;
  34. u8 reg_irq_mask;
  35. u8 reg_irq_src;
  36. u8 reg_sense;
  37. u8 reg_clock;
  38. u8 reg_misc;
  39. u8 reg_reset;
  40. u8 ngpios;
  41. };
  42. struct sx150x_chip {
  43. struct gpio_chip gpio_chip;
  44. struct i2c_client *client;
  45. const struct sx150x_device_data *dev_cfg;
  46. int irq_summary;
  47. int irq_base;
  48. int irq_update;
  49. u32 irq_sense;
  50. u32 irq_masked;
  51. u32 dev_sense;
  52. u32 dev_masked;
  53. struct irq_chip irq_chip;
  54. struct mutex lock;
  55. };
  56. static const struct sx150x_device_data sx150x_devices[] = {
  57. [0] = { /* sx1508q */
  58. .reg_pullup = 0x03,
  59. .reg_pulldn = 0x04,
  60. .reg_drain = 0x05,
  61. .reg_polarity = 0x06,
  62. .reg_dir = 0x07,
  63. .reg_data = 0x08,
  64. .reg_irq_mask = 0x09,
  65. .reg_irq_src = 0x0c,
  66. .reg_sense = 0x0b,
  67. .reg_clock = 0x0f,
  68. .reg_misc = 0x10,
  69. .reg_reset = 0x7d,
  70. .ngpios = 8
  71. },
  72. [1] = { /* sx1509q */
  73. .reg_pullup = 0x07,
  74. .reg_pulldn = 0x09,
  75. .reg_drain = 0x0b,
  76. .reg_polarity = 0x0d,
  77. .reg_dir = 0x0f,
  78. .reg_data = 0x11,
  79. .reg_irq_mask = 0x13,
  80. .reg_irq_src = 0x19,
  81. .reg_sense = 0x17,
  82. .reg_clock = 0x1e,
  83. .reg_misc = 0x1f,
  84. .reg_reset = 0x7d,
  85. .ngpios = 16
  86. },
  87. };
  88. static const struct i2c_device_id sx150x_id[] = {
  89. {"sx1508q", 0},
  90. {"sx1509q", 1},
  91. {}
  92. };
  93. MODULE_DEVICE_TABLE(i2c, sx150x_id);
  94. static s32 sx150x_i2c_write(struct i2c_client *client, u8 reg, u8 val)
  95. {
  96. s32 err = i2c_smbus_write_byte_data(client, reg, val);
  97. if (err < 0)
  98. dev_warn(&client->dev,
  99. "i2c write fail: can't write %02x to %02x: %d\n",
  100. val, reg, err);
  101. return err;
  102. }
  103. static s32 sx150x_i2c_read(struct i2c_client *client, u8 reg, u8 *val)
  104. {
  105. s32 err = i2c_smbus_read_byte_data(client, reg);
  106. if (err >= 0)
  107. *val = err;
  108. else
  109. dev_warn(&client->dev,
  110. "i2c read fail: can't read from %02x: %d\n",
  111. reg, err);
  112. return err;
  113. }
  114. static inline bool offset_is_oscio(struct sx150x_chip *chip, unsigned offset)
  115. {
  116. return (chip->dev_cfg->ngpios == offset);
  117. }
  118. /*
  119. * These utility functions solve the common problem of locating and setting
  120. * configuration bits. Configuration bits are grouped into registers
  121. * whose indexes increase downwards. For example, with eight-bit registers,
  122. * sixteen gpios would have their config bits grouped in the following order:
  123. * REGISTER N-1 [ f e d c b a 9 8 ]
  124. * N [ 7 6 5 4 3 2 1 0 ]
  125. *
  126. * For multi-bit configurations, the pattern gets wider:
  127. * REGISTER N-3 [ f f e e d d c c ]
  128. * N-2 [ b b a a 9 9 8 8 ]
  129. * N-1 [ 7 7 6 6 5 5 4 4 ]
  130. * N [ 3 3 2 2 1 1 0 0 ]
  131. *
  132. * Given the address of the starting register 'N', the index of the gpio
  133. * whose configuration we seek to change, and the width in bits of that
  134. * configuration, these functions allow us to locate the correct
  135. * register and mask the correct bits.
  136. */
  137. static inline void sx150x_find_cfg(u8 offset, u8 width,
  138. u8 *reg, u8 *mask, u8 *shift)
  139. {
  140. *reg -= offset * width / 8;
  141. *mask = (1 << width) - 1;
  142. *shift = (offset * width) % 8;
  143. *mask <<= *shift;
  144. }
  145. static s32 sx150x_write_cfg(struct sx150x_chip *chip,
  146. u8 offset, u8 width, u8 reg, u8 val)
  147. {
  148. u8 mask;
  149. u8 data;
  150. u8 shift;
  151. s32 err;
  152. sx150x_find_cfg(offset, width, &reg, &mask, &shift);
  153. err = sx150x_i2c_read(chip->client, reg, &data);
  154. if (err < 0)
  155. return err;
  156. data &= ~mask;
  157. data |= (val << shift) & mask;
  158. return sx150x_i2c_write(chip->client, reg, data);
  159. }
  160. static int sx150x_get_io(struct sx150x_chip *chip, unsigned offset)
  161. {
  162. u8 reg = chip->dev_cfg->reg_data;
  163. u8 mask;
  164. u8 data;
  165. u8 shift;
  166. s32 err;
  167. sx150x_find_cfg(offset, 1, &reg, &mask, &shift);
  168. err = sx150x_i2c_read(chip->client, reg, &data);
  169. if (err >= 0)
  170. err = (data & mask) != 0 ? 1 : 0;
  171. return err;
  172. }
  173. static void sx150x_set_oscio(struct sx150x_chip *chip, int val)
  174. {
  175. sx150x_i2c_write(chip->client,
  176. chip->dev_cfg->reg_clock,
  177. (val ? 0x1f : 0x10));
  178. }
  179. static void sx150x_set_io(struct sx150x_chip *chip, unsigned offset, int val)
  180. {
  181. sx150x_write_cfg(chip,
  182. offset,
  183. 1,
  184. chip->dev_cfg->reg_data,
  185. (val ? 1 : 0));
  186. }
  187. static int sx150x_io_input(struct sx150x_chip *chip, unsigned offset)
  188. {
  189. return sx150x_write_cfg(chip,
  190. offset,
  191. 1,
  192. chip->dev_cfg->reg_dir,
  193. 1);
  194. }
  195. static int sx150x_io_output(struct sx150x_chip *chip, unsigned offset, int val)
  196. {
  197. int err;
  198. err = sx150x_write_cfg(chip,
  199. offset,
  200. 1,
  201. chip->dev_cfg->reg_data,
  202. (val ? 1 : 0));
  203. if (err >= 0)
  204. err = sx150x_write_cfg(chip,
  205. offset,
  206. 1,
  207. chip->dev_cfg->reg_dir,
  208. 0);
  209. return err;
  210. }
  211. static int sx150x_gpio_get(struct gpio_chip *gc, unsigned offset)
  212. {
  213. struct sx150x_chip *chip;
  214. int status = -EINVAL;
  215. chip = container_of(gc, struct sx150x_chip, gpio_chip);
  216. if (!offset_is_oscio(chip, offset)) {
  217. mutex_lock(&chip->lock);
  218. status = sx150x_get_io(chip, offset);
  219. mutex_unlock(&chip->lock);
  220. }
  221. return status;
  222. }
  223. static void sx150x_gpio_set(struct gpio_chip *gc, unsigned offset, int val)
  224. {
  225. struct sx150x_chip *chip;
  226. chip = container_of(gc, struct sx150x_chip, gpio_chip);
  227. mutex_lock(&chip->lock);
  228. if (offset_is_oscio(chip, offset))
  229. sx150x_set_oscio(chip, val);
  230. else
  231. sx150x_set_io(chip, offset, val);
  232. mutex_unlock(&chip->lock);
  233. }
  234. static int sx150x_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
  235. {
  236. struct sx150x_chip *chip;
  237. int status = -EINVAL;
  238. chip = container_of(gc, struct sx150x_chip, gpio_chip);
  239. if (!offset_is_oscio(chip, offset)) {
  240. mutex_lock(&chip->lock);
  241. status = sx150x_io_input(chip, offset);
  242. mutex_unlock(&chip->lock);
  243. }
  244. return status;
  245. }
  246. static int sx150x_gpio_direction_output(struct gpio_chip *gc,
  247. unsigned offset,
  248. int val)
  249. {
  250. struct sx150x_chip *chip;
  251. int status = 0;
  252. chip = container_of(gc, struct sx150x_chip, gpio_chip);
  253. if (!offset_is_oscio(chip, offset)) {
  254. mutex_lock(&chip->lock);
  255. status = sx150x_io_output(chip, offset, val);
  256. mutex_unlock(&chip->lock);
  257. }
  258. return status;
  259. }
  260. static int sx150x_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
  261. {
  262. struct sx150x_chip *chip;
  263. chip = container_of(gc, struct sx150x_chip, gpio_chip);
  264. if (offset >= chip->dev_cfg->ngpios)
  265. return -EINVAL;
  266. if (chip->irq_base < 0)
  267. return -EINVAL;
  268. return chip->irq_base + offset;
  269. }
  270. static void sx150x_irq_mask(struct irq_data *d)
  271. {
  272. struct sx150x_chip *chip = irq_data_get_irq_chip_data(d);
  273. unsigned n;
  274. n = d->irq - chip->irq_base;
  275. chip->irq_masked |= (1 << n);
  276. chip->irq_update = n;
  277. }
  278. static void sx150x_irq_unmask(struct irq_data *d)
  279. {
  280. struct sx150x_chip *chip = irq_data_get_irq_chip_data(d);
  281. unsigned n;
  282. n = d->irq - chip->irq_base;
  283. chip->irq_masked &= ~(1 << n);
  284. chip->irq_update = n;
  285. }
  286. static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
  287. {
  288. struct sx150x_chip *chip = irq_data_get_irq_chip_data(d);
  289. unsigned n, val = 0;
  290. if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
  291. return -EINVAL;
  292. n = d->irq - chip->irq_base;
  293. if (flow_type & IRQ_TYPE_EDGE_RISING)
  294. val |= 0x1;
  295. if (flow_type & IRQ_TYPE_EDGE_FALLING)
  296. val |= 0x2;
  297. chip->irq_sense &= ~(3UL << (n * 2));
  298. chip->irq_sense |= val << (n * 2);
  299. chip->irq_update = n;
  300. return 0;
  301. }
  302. static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
  303. {
  304. struct sx150x_chip *chip = (struct sx150x_chip *)dev_id;
  305. unsigned nhandled = 0;
  306. unsigned sub_irq;
  307. unsigned n;
  308. s32 err;
  309. u8 val;
  310. int i;
  311. for (i = (chip->dev_cfg->ngpios / 8) - 1; i >= 0; --i) {
  312. err = sx150x_i2c_read(chip->client,
  313. chip->dev_cfg->reg_irq_src - i,
  314. &val);
  315. if (err < 0)
  316. continue;
  317. sx150x_i2c_write(chip->client,
  318. chip->dev_cfg->reg_irq_src - i,
  319. val);
  320. for (n = 0; n < 8; ++n) {
  321. if (val & (1 << n)) {
  322. sub_irq = chip->irq_base + (i * 8) + n;
  323. handle_nested_irq(sub_irq);
  324. ++nhandled;
  325. }
  326. }
  327. }
  328. return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
  329. }
  330. static void sx150x_irq_bus_lock(struct irq_data *d)
  331. {
  332. struct sx150x_chip *chip = irq_data_get_irq_chip_data(d);
  333. mutex_lock(&chip->lock);
  334. }
  335. static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
  336. {
  337. struct sx150x_chip *chip = irq_data_get_irq_chip_data(d);
  338. unsigned n;
  339. if (chip->irq_update == NO_UPDATE_PENDING)
  340. goto out;
  341. n = chip->irq_update;
  342. chip->irq_update = NO_UPDATE_PENDING;
  343. /* Avoid updates if nothing changed */
  344. if (chip->dev_sense == chip->irq_sense &&
  345. chip->dev_sense == chip->irq_masked)
  346. goto out;
  347. chip->dev_sense = chip->irq_sense;
  348. chip->dev_masked = chip->irq_masked;
  349. if (chip->irq_masked & (1 << n)) {
  350. sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 1);
  351. sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense, 0);
  352. } else {
  353. sx150x_write_cfg(chip, n, 1, chip->dev_cfg->reg_irq_mask, 0);
  354. sx150x_write_cfg(chip, n, 2, chip->dev_cfg->reg_sense,
  355. chip->irq_sense >> (n * 2));
  356. }
  357. out:
  358. mutex_unlock(&chip->lock);
  359. }
  360. static void sx150x_init_chip(struct sx150x_chip *chip,
  361. struct i2c_client *client,
  362. kernel_ulong_t driver_data,
  363. struct sx150x_platform_data *pdata)
  364. {
  365. mutex_init(&chip->lock);
  366. chip->client = client;
  367. chip->dev_cfg = &sx150x_devices[driver_data];
  368. chip->gpio_chip.label = client->name;
  369. chip->gpio_chip.direction_input = sx150x_gpio_direction_input;
  370. chip->gpio_chip.direction_output = sx150x_gpio_direction_output;
  371. chip->gpio_chip.get = sx150x_gpio_get;
  372. chip->gpio_chip.set = sx150x_gpio_set;
  373. chip->gpio_chip.to_irq = sx150x_gpio_to_irq;
  374. chip->gpio_chip.base = pdata->gpio_base;
  375. chip->gpio_chip.can_sleep = true;
  376. chip->gpio_chip.ngpio = chip->dev_cfg->ngpios;
  377. if (pdata->oscio_is_gpo)
  378. ++chip->gpio_chip.ngpio;
  379. chip->irq_chip.name = client->name;
  380. chip->irq_chip.irq_mask = sx150x_irq_mask;
  381. chip->irq_chip.irq_unmask = sx150x_irq_unmask;
  382. chip->irq_chip.irq_set_type = sx150x_irq_set_type;
  383. chip->irq_chip.irq_bus_lock = sx150x_irq_bus_lock;
  384. chip->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock;
  385. chip->irq_summary = -1;
  386. chip->irq_base = -1;
  387. chip->irq_masked = ~0;
  388. chip->irq_sense = 0;
  389. chip->dev_masked = ~0;
  390. chip->dev_sense = 0;
  391. chip->irq_update = NO_UPDATE_PENDING;
  392. }
  393. static int sx150x_init_io(struct sx150x_chip *chip, u8 base, u16 cfg)
  394. {
  395. int err = 0;
  396. unsigned n;
  397. for (n = 0; err >= 0 && n < (chip->dev_cfg->ngpios / 8); ++n)
  398. err = sx150x_i2c_write(chip->client, base - n, cfg >> (n * 8));
  399. return err;
  400. }
  401. static int sx150x_reset(struct sx150x_chip *chip)
  402. {
  403. int err;
  404. err = i2c_smbus_write_byte_data(chip->client,
  405. chip->dev_cfg->reg_reset,
  406. 0x12);
  407. if (err < 0)
  408. return err;
  409. err = i2c_smbus_write_byte_data(chip->client,
  410. chip->dev_cfg->reg_reset,
  411. 0x34);
  412. return err;
  413. }
  414. static int sx150x_init_hw(struct sx150x_chip *chip,
  415. struct sx150x_platform_data *pdata)
  416. {
  417. int err = 0;
  418. if (pdata->reset_during_probe) {
  419. err = sx150x_reset(chip);
  420. if (err < 0)
  421. return err;
  422. }
  423. err = sx150x_i2c_write(chip->client,
  424. chip->dev_cfg->reg_misc,
  425. 0x01);
  426. if (err < 0)
  427. return err;
  428. err = sx150x_init_io(chip, chip->dev_cfg->reg_pullup,
  429. pdata->io_pullup_ena);
  430. if (err < 0)
  431. return err;
  432. err = sx150x_init_io(chip, chip->dev_cfg->reg_pulldn,
  433. pdata->io_pulldn_ena);
  434. if (err < 0)
  435. return err;
  436. err = sx150x_init_io(chip, chip->dev_cfg->reg_drain,
  437. pdata->io_open_drain_ena);
  438. if (err < 0)
  439. return err;
  440. err = sx150x_init_io(chip, chip->dev_cfg->reg_polarity,
  441. pdata->io_polarity);
  442. if (err < 0)
  443. return err;
  444. if (pdata->oscio_is_gpo)
  445. sx150x_set_oscio(chip, 0);
  446. return err;
  447. }
  448. static int sx150x_install_irq_chip(struct sx150x_chip *chip,
  449. int irq_summary,
  450. int irq_base)
  451. {
  452. int err;
  453. unsigned n;
  454. unsigned irq;
  455. chip->irq_summary = irq_summary;
  456. chip->irq_base = irq_base;
  457. for (n = 0; n < chip->dev_cfg->ngpios; ++n) {
  458. irq = irq_base + n;
  459. irq_set_chip_data(irq, chip);
  460. irq_set_chip_and_handler(irq, &chip->irq_chip, handle_edge_irq);
  461. irq_set_nested_thread(irq, 1);
  462. #ifdef CONFIG_ARM
  463. set_irq_flags(irq, IRQF_VALID);
  464. #else
  465. irq_set_noprobe(irq);
  466. #endif
  467. }
  468. err = devm_request_threaded_irq(&chip->client->dev,
  469. irq_summary,
  470. NULL,
  471. sx150x_irq_thread_fn,
  472. IRQF_SHARED | IRQF_TRIGGER_FALLING,
  473. chip->irq_chip.name,
  474. chip);
  475. if (err < 0) {
  476. chip->irq_summary = -1;
  477. chip->irq_base = -1;
  478. }
  479. return err;
  480. }
  481. static void sx150x_remove_irq_chip(struct sx150x_chip *chip)
  482. {
  483. unsigned n;
  484. unsigned irq;
  485. for (n = 0; n < chip->dev_cfg->ngpios; ++n) {
  486. irq = chip->irq_base + n;
  487. irq_set_chip_and_handler(irq, NULL, NULL);
  488. }
  489. }
  490. static int sx150x_probe(struct i2c_client *client,
  491. const struct i2c_device_id *id)
  492. {
  493. static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
  494. I2C_FUNC_SMBUS_WRITE_WORD_DATA;
  495. struct sx150x_platform_data *pdata;
  496. struct sx150x_chip *chip;
  497. int rc;
  498. pdata = dev_get_platdata(&client->dev);
  499. if (!pdata)
  500. return -EINVAL;
  501. if (!i2c_check_functionality(client->adapter, i2c_funcs))
  502. return -ENOSYS;
  503. chip = devm_kzalloc(&client->dev,
  504. sizeof(struct sx150x_chip), GFP_KERNEL);
  505. if (!chip)
  506. return -ENOMEM;
  507. sx150x_init_chip(chip, client, id->driver_data, pdata);
  508. rc = sx150x_init_hw(chip, pdata);
  509. if (rc < 0)
  510. return rc;
  511. rc = gpiochip_add(&chip->gpio_chip);
  512. if (rc)
  513. return rc;
  514. if (pdata->irq_summary >= 0) {
  515. rc = sx150x_install_irq_chip(chip,
  516. pdata->irq_summary,
  517. pdata->irq_base);
  518. if (rc < 0)
  519. goto probe_fail_post_gpiochip_add;
  520. }
  521. i2c_set_clientdata(client, chip);
  522. return 0;
  523. probe_fail_post_gpiochip_add:
  524. WARN_ON(gpiochip_remove(&chip->gpio_chip) < 0);
  525. return rc;
  526. }
  527. static int sx150x_remove(struct i2c_client *client)
  528. {
  529. struct sx150x_chip *chip;
  530. int rc;
  531. chip = i2c_get_clientdata(client);
  532. rc = gpiochip_remove(&chip->gpio_chip);
  533. if (rc < 0)
  534. return rc;
  535. if (chip->irq_summary >= 0)
  536. sx150x_remove_irq_chip(chip);
  537. return 0;
  538. }
  539. static struct i2c_driver sx150x_driver = {
  540. .driver = {
  541. .name = "sx150x",
  542. .owner = THIS_MODULE
  543. },
  544. .probe = sx150x_probe,
  545. .remove = sx150x_remove,
  546. .id_table = sx150x_id,
  547. };
  548. static int __init sx150x_init(void)
  549. {
  550. return i2c_add_driver(&sx150x_driver);
  551. }
  552. subsys_initcall(sx150x_init);
  553. static void __exit sx150x_exit(void)
  554. {
  555. return i2c_del_driver(&sx150x_driver);
  556. }
  557. module_exit(sx150x_exit);
  558. MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>");
  559. MODULE_DESCRIPTION("Driver for Semtech SX150X I2C GPIO Expanders");
  560. MODULE_LICENSE("GPL v2");
  561. MODULE_ALIAS("i2c:sx150x");