gpio-f7188x.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470
  1. /*
  2. * GPIO driver for Fintek Super-I/O F71882 and F71889
  3. *
  4. * Copyright (C) 2010-2013 LaCie
  5. *
  6. * Author: Simon Guinot <simon.guinot@sequanux.org>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/io.h>
  17. #include <linux/gpio.h>
  18. #define DRVNAME "gpio-f7188x"
  19. /*
  20. * Super-I/O registers
  21. */
  22. #define SIO_LDSEL 0x07 /* Logical device select */
  23. #define SIO_DEVID 0x20 /* Device ID (2 bytes) */
  24. #define SIO_DEVREV 0x22 /* Device revision */
  25. #define SIO_MANID 0x23 /* Fintek ID (2 bytes) */
  26. #define SIO_LD_GPIO 0x06 /* GPIO logical device */
  27. #define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
  28. #define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
  29. #define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */
  30. #define SIO_F71882_ID 0x0541 /* F71882 chipset ID */
  31. #define SIO_F71889_ID 0x0909 /* F71889 chipset ID */
  32. enum chips { f71882fg, f71889f };
  33. static const char * const f7188x_names[] = {
  34. "f71882fg",
  35. "f71889f",
  36. };
  37. struct f7188x_sio {
  38. int addr;
  39. enum chips type;
  40. };
  41. struct f7188x_gpio_bank {
  42. struct gpio_chip chip;
  43. unsigned int regbase;
  44. struct f7188x_gpio_data *data;
  45. };
  46. struct f7188x_gpio_data {
  47. struct f7188x_sio *sio;
  48. int nr_bank;
  49. struct f7188x_gpio_bank *bank;
  50. };
  51. /*
  52. * Super-I/O functions.
  53. */
  54. static inline int superio_inb(int base, int reg)
  55. {
  56. outb(reg, base);
  57. return inb(base + 1);
  58. }
  59. static int superio_inw(int base, int reg)
  60. {
  61. int val;
  62. outb(reg++, base);
  63. val = inb(base + 1) << 8;
  64. outb(reg, base);
  65. val |= inb(base + 1);
  66. return val;
  67. }
  68. static inline void superio_outb(int base, int reg, int val)
  69. {
  70. outb(reg, base);
  71. outb(val, base + 1);
  72. }
  73. static inline int superio_enter(int base)
  74. {
  75. /* Don't step on other drivers' I/O space by accident. */
  76. if (!request_muxed_region(base, 2, DRVNAME)) {
  77. pr_err(DRVNAME "I/O address 0x%04x already in use\n", base);
  78. return -EBUSY;
  79. }
  80. /* According to the datasheet the key must be send twice. */
  81. outb(SIO_UNLOCK_KEY, base);
  82. outb(SIO_UNLOCK_KEY, base);
  83. return 0;
  84. }
  85. static inline void superio_select(int base, int ld)
  86. {
  87. outb(SIO_LDSEL, base);
  88. outb(ld, base + 1);
  89. }
  90. static inline void superio_exit(int base)
  91. {
  92. outb(SIO_LOCK_KEY, base);
  93. release_region(base, 2);
  94. }
  95. /*
  96. * GPIO chip.
  97. */
  98. static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset);
  99. static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset);
  100. static int f7188x_gpio_direction_out(struct gpio_chip *chip,
  101. unsigned offset, int value);
  102. static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value);
  103. #define F7188X_GPIO_BANK(_base, _ngpio, _regbase) \
  104. { \
  105. .chip = { \
  106. .label = DRVNAME, \
  107. .owner = THIS_MODULE, \
  108. .direction_input = f7188x_gpio_direction_in, \
  109. .get = f7188x_gpio_get, \
  110. .direction_output = f7188x_gpio_direction_out, \
  111. .set = f7188x_gpio_set, \
  112. .base = _base, \
  113. .ngpio = _ngpio, \
  114. .can_sleep = true, \
  115. }, \
  116. .regbase = _regbase, \
  117. }
  118. #define gpio_dir(base) (base + 0)
  119. #define gpio_data_out(base) (base + 1)
  120. #define gpio_data_in(base) (base + 2)
  121. /* Output mode register (0:open drain 1:push-pull). */
  122. #define gpio_out_mode(base) (base + 3)
  123. static struct f7188x_gpio_bank f71882_gpio_bank[] = {
  124. F7188X_GPIO_BANK(0 , 8, 0xF0),
  125. F7188X_GPIO_BANK(10, 8, 0xE0),
  126. F7188X_GPIO_BANK(20, 8, 0xD0),
  127. F7188X_GPIO_BANK(30, 4, 0xC0),
  128. F7188X_GPIO_BANK(40, 4, 0xB0),
  129. };
  130. static struct f7188x_gpio_bank f71889_gpio_bank[] = {
  131. F7188X_GPIO_BANK(0 , 7, 0xF0),
  132. F7188X_GPIO_BANK(10, 7, 0xE0),
  133. F7188X_GPIO_BANK(20, 8, 0xD0),
  134. F7188X_GPIO_BANK(30, 8, 0xC0),
  135. F7188X_GPIO_BANK(40, 8, 0xB0),
  136. F7188X_GPIO_BANK(50, 5, 0xA0),
  137. F7188X_GPIO_BANK(60, 8, 0x90),
  138. F7188X_GPIO_BANK(70, 8, 0x80),
  139. };
  140. static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
  141. {
  142. int err;
  143. struct f7188x_gpio_bank *bank =
  144. container_of(chip, struct f7188x_gpio_bank, chip);
  145. struct f7188x_sio *sio = bank->data->sio;
  146. u8 dir;
  147. err = superio_enter(sio->addr);
  148. if (err)
  149. return err;
  150. superio_select(sio->addr, SIO_LD_GPIO);
  151. dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
  152. dir &= ~(1 << offset);
  153. superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
  154. superio_exit(sio->addr);
  155. return 0;
  156. }
  157. static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset)
  158. {
  159. int err;
  160. struct f7188x_gpio_bank *bank =
  161. container_of(chip, struct f7188x_gpio_bank, chip);
  162. struct f7188x_sio *sio = bank->data->sio;
  163. u8 dir, data;
  164. err = superio_enter(sio->addr);
  165. if (err)
  166. return err;
  167. superio_select(sio->addr, SIO_LD_GPIO);
  168. dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
  169. dir = !!(dir & (1 << offset));
  170. if (dir)
  171. data = superio_inb(sio->addr, gpio_data_out(bank->regbase));
  172. else
  173. data = superio_inb(sio->addr, gpio_data_in(bank->regbase));
  174. superio_exit(sio->addr);
  175. return !!(data & 1 << offset);
  176. }
  177. static int f7188x_gpio_direction_out(struct gpio_chip *chip,
  178. unsigned offset, int value)
  179. {
  180. int err;
  181. struct f7188x_gpio_bank *bank =
  182. container_of(chip, struct f7188x_gpio_bank, chip);
  183. struct f7188x_sio *sio = bank->data->sio;
  184. u8 dir, data_out;
  185. err = superio_enter(sio->addr);
  186. if (err)
  187. return err;
  188. superio_select(sio->addr, SIO_LD_GPIO);
  189. data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
  190. if (value)
  191. data_out |= (1 << offset);
  192. else
  193. data_out &= ~(1 << offset);
  194. superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
  195. dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
  196. dir |= (1 << offset);
  197. superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
  198. superio_exit(sio->addr);
  199. return 0;
  200. }
  201. static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  202. {
  203. int err;
  204. struct f7188x_gpio_bank *bank =
  205. container_of(chip, struct f7188x_gpio_bank, chip);
  206. struct f7188x_sio *sio = bank->data->sio;
  207. u8 data_out;
  208. err = superio_enter(sio->addr);
  209. if (err)
  210. return;
  211. superio_select(sio->addr, SIO_LD_GPIO);
  212. data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
  213. if (value)
  214. data_out |= (1 << offset);
  215. else
  216. data_out &= ~(1 << offset);
  217. superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
  218. superio_exit(sio->addr);
  219. }
  220. /*
  221. * Platform device and driver.
  222. */
  223. static int f7188x_gpio_probe(struct platform_device *pdev)
  224. {
  225. int err;
  226. int i;
  227. struct f7188x_sio *sio = pdev->dev.platform_data;
  228. struct f7188x_gpio_data *data;
  229. data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
  230. if (!data)
  231. return -ENOMEM;
  232. switch (sio->type) {
  233. case f71882fg:
  234. data->nr_bank = ARRAY_SIZE(f71882_gpio_bank);
  235. data->bank = f71882_gpio_bank;
  236. break;
  237. case f71889f:
  238. data->nr_bank = ARRAY_SIZE(f71889_gpio_bank);
  239. data->bank = f71889_gpio_bank;
  240. break;
  241. default:
  242. return -ENODEV;
  243. }
  244. data->sio = sio;
  245. platform_set_drvdata(pdev, data);
  246. /* For each GPIO bank, register a GPIO chip. */
  247. for (i = 0; i < data->nr_bank; i++) {
  248. struct f7188x_gpio_bank *bank = &data->bank[i];
  249. bank->chip.dev = &pdev->dev;
  250. bank->data = data;
  251. err = gpiochip_add(&bank->chip);
  252. if (err) {
  253. dev_err(&pdev->dev,
  254. "Failed to register gpiochip %d: %d\n",
  255. i, err);
  256. goto err_gpiochip;
  257. }
  258. }
  259. return 0;
  260. err_gpiochip:
  261. for (i = i - 1; i >= 0; i--) {
  262. struct f7188x_gpio_bank *bank = &data->bank[i];
  263. int tmp;
  264. tmp = gpiochip_remove(&bank->chip);
  265. if (tmp < 0)
  266. dev_err(&pdev->dev,
  267. "Failed to remove gpiochip %d: %d\n",
  268. i, tmp);
  269. }
  270. return err;
  271. }
  272. static int f7188x_gpio_remove(struct platform_device *pdev)
  273. {
  274. int err;
  275. int i;
  276. struct f7188x_gpio_data *data = platform_get_drvdata(pdev);
  277. for (i = 0; i < data->nr_bank; i++) {
  278. struct f7188x_gpio_bank *bank = &data->bank[i];
  279. err = gpiochip_remove(&bank->chip);
  280. if (err) {
  281. dev_err(&pdev->dev,
  282. "Failed to remove GPIO gpiochip %d: %d\n",
  283. i, err);
  284. return err;
  285. }
  286. }
  287. return 0;
  288. }
  289. static int __init f7188x_find(int addr, struct f7188x_sio *sio)
  290. {
  291. int err;
  292. u16 devid;
  293. err = superio_enter(addr);
  294. if (err)
  295. return err;
  296. err = -ENODEV;
  297. devid = superio_inw(addr, SIO_MANID);
  298. if (devid != SIO_FINTEK_ID) {
  299. pr_debug(DRVNAME ": Not a Fintek device at 0x%08x\n", addr);
  300. goto err;
  301. }
  302. devid = superio_inw(addr, SIO_DEVID);
  303. switch (devid) {
  304. case SIO_F71882_ID:
  305. sio->type = f71882fg;
  306. break;
  307. case SIO_F71889_ID:
  308. sio->type = f71889f;
  309. break;
  310. default:
  311. pr_info(DRVNAME ": Unsupported Fintek device 0x%04x\n", devid);
  312. goto err;
  313. }
  314. sio->addr = addr;
  315. err = 0;
  316. pr_info(DRVNAME ": Found %s at %#x, revision %d\n",
  317. f7188x_names[sio->type],
  318. (unsigned int) addr,
  319. (int) superio_inb(addr, SIO_DEVREV));
  320. err:
  321. superio_exit(addr);
  322. return err;
  323. }
  324. static struct platform_device *f7188x_gpio_pdev;
  325. static int __init
  326. f7188x_gpio_device_add(const struct f7188x_sio *sio)
  327. {
  328. int err;
  329. f7188x_gpio_pdev = platform_device_alloc(DRVNAME, -1);
  330. if (!f7188x_gpio_pdev)
  331. return -ENOMEM;
  332. err = platform_device_add_data(f7188x_gpio_pdev,
  333. sio, sizeof(*sio));
  334. if (err) {
  335. pr_err(DRVNAME "Platform data allocation failed\n");
  336. goto err;
  337. }
  338. err = platform_device_add(f7188x_gpio_pdev);
  339. if (err) {
  340. pr_err(DRVNAME "Device addition failed\n");
  341. goto err;
  342. }
  343. return 0;
  344. err:
  345. platform_device_put(f7188x_gpio_pdev);
  346. return err;
  347. }
  348. /*
  349. * Try to match a supported Fintech device by reading the (hard-wired)
  350. * configuration I/O ports. If available, then register both the platform
  351. * device and driver to support the GPIOs.
  352. */
  353. static struct platform_driver f7188x_gpio_driver = {
  354. .driver = {
  355. .owner = THIS_MODULE,
  356. .name = DRVNAME,
  357. },
  358. .probe = f7188x_gpio_probe,
  359. .remove = f7188x_gpio_remove,
  360. };
  361. static int __init f7188x_gpio_init(void)
  362. {
  363. int err;
  364. struct f7188x_sio sio;
  365. if (f7188x_find(0x2e, &sio) &&
  366. f7188x_find(0x4e, &sio))
  367. return -ENODEV;
  368. err = platform_driver_register(&f7188x_gpio_driver);
  369. if (!err) {
  370. err = f7188x_gpio_device_add(&sio);
  371. if (err)
  372. platform_driver_unregister(&f7188x_gpio_driver);
  373. }
  374. return err;
  375. }
  376. subsys_initcall(f7188x_gpio_init);
  377. static void __exit f7188x_gpio_exit(void)
  378. {
  379. platform_device_unregister(f7188x_gpio_pdev);
  380. platform_driver_unregister(&f7188x_gpio_driver);
  381. }
  382. module_exit(f7188x_gpio_exit);
  383. MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71882FG and F71889F");
  384. MODULE_AUTHOR("Simon Guinot <simon.guinot@sequanux.org>");
  385. MODULE_LICENSE("GPL");