Thomas Gleixner 449437778b clk: spear3xx: Set proper clock parent of uart1/2 11 rokov pred
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Makefile 0b928af1f4 SPEAr13xx: Add common clock framework support 13 rokov pred
clk-aux-synth.c 1249979242 CLK: SPEAr: Set CLK_SET_RATE_PARENT for few clocks 12 rokov pred
clk-frac-synth.c 3c9210bd3a clk: SPEAr: Staticize clk_frac_ops 11 rokov pred
clk-gpt-synth.c 10d8935f46 Viresh has moved 13 rokov pred
clk-vco-pll.c 7d4998f71b clk: SPEAr: Vco-pll: Fix compilation warning 13 rokov pred
clk.c 1b2d4ad585 CLK: SPEAr: Correct index scanning done for clock synths 12 rokov pred
clk.h 10d8935f46 Viresh has moved 13 rokov pred
spear1310_clock.c 819c1de344 clk: add CLK_SET_RATE_NO_REPARENT flag 12 rokov pred
spear1340_clock.c 819c1de344 clk: add CLK_SET_RATE_NO_REPARENT flag 12 rokov pred
spear3xx_clock.c 449437778b clk: spear3xx: Set proper clock parent of uart1/2 11 rokov pred
spear6xx_clock.c 819c1de344 clk: add CLK_SET_RATE_NO_REPARENT flag 12 rokov pred