clk-peripheral.c 9.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410
  1. /*
  2. * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. */
  10. #include <linux/clk-provider.h>
  11. #include <linux/clkdev.h>
  12. #include <linux/clk/at91_pmc.h>
  13. #include <linux/of.h>
  14. #include <linux/of_address.h>
  15. #include <linux/io.h>
  16. #include "pmc.h"
  17. #define PERIPHERAL_MAX 64
  18. #define PERIPHERAL_AT91RM9200 0
  19. #define PERIPHERAL_AT91SAM9X5 1
  20. #define PERIPHERAL_ID_MIN 2
  21. #define PERIPHERAL_ID_MAX 31
  22. #define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
  23. #define PERIPHERAL_RSHIFT_MASK 0x3
  24. #define PERIPHERAL_RSHIFT(val) (((val) >> 16) & PERIPHERAL_RSHIFT_MASK)
  25. #define PERIPHERAL_MAX_SHIFT 4
  26. struct clk_peripheral {
  27. struct clk_hw hw;
  28. struct at91_pmc *pmc;
  29. u32 id;
  30. };
  31. #define to_clk_peripheral(hw) container_of(hw, struct clk_peripheral, hw)
  32. struct clk_sam9x5_peripheral {
  33. struct clk_hw hw;
  34. struct at91_pmc *pmc;
  35. struct clk_range range;
  36. u32 id;
  37. u32 div;
  38. bool auto_div;
  39. };
  40. #define to_clk_sam9x5_peripheral(hw) \
  41. container_of(hw, struct clk_sam9x5_peripheral, hw)
  42. static int clk_peripheral_enable(struct clk_hw *hw)
  43. {
  44. struct clk_peripheral *periph = to_clk_peripheral(hw);
  45. struct at91_pmc *pmc = periph->pmc;
  46. int offset = AT91_PMC_PCER;
  47. u32 id = periph->id;
  48. if (id < PERIPHERAL_ID_MIN)
  49. return 0;
  50. if (id > PERIPHERAL_ID_MAX)
  51. offset = AT91_PMC_PCER1;
  52. pmc_write(pmc, offset, PERIPHERAL_MASK(id));
  53. return 0;
  54. }
  55. static void clk_peripheral_disable(struct clk_hw *hw)
  56. {
  57. struct clk_peripheral *periph = to_clk_peripheral(hw);
  58. struct at91_pmc *pmc = periph->pmc;
  59. int offset = AT91_PMC_PCDR;
  60. u32 id = periph->id;
  61. if (id < PERIPHERAL_ID_MIN)
  62. return;
  63. if (id > PERIPHERAL_ID_MAX)
  64. offset = AT91_PMC_PCDR1;
  65. pmc_write(pmc, offset, PERIPHERAL_MASK(id));
  66. }
  67. static int clk_peripheral_is_enabled(struct clk_hw *hw)
  68. {
  69. struct clk_peripheral *periph = to_clk_peripheral(hw);
  70. struct at91_pmc *pmc = periph->pmc;
  71. int offset = AT91_PMC_PCSR;
  72. u32 id = periph->id;
  73. if (id < PERIPHERAL_ID_MIN)
  74. return 1;
  75. if (id > PERIPHERAL_ID_MAX)
  76. offset = AT91_PMC_PCSR1;
  77. return !!(pmc_read(pmc, offset) & PERIPHERAL_MASK(id));
  78. }
  79. static const struct clk_ops peripheral_ops = {
  80. .enable = clk_peripheral_enable,
  81. .disable = clk_peripheral_disable,
  82. .is_enabled = clk_peripheral_is_enabled,
  83. };
  84. static struct clk * __init
  85. at91_clk_register_peripheral(struct at91_pmc *pmc, const char *name,
  86. const char *parent_name, u32 id)
  87. {
  88. struct clk_peripheral *periph;
  89. struct clk *clk = NULL;
  90. struct clk_init_data init;
  91. if (!pmc || !name || !parent_name || id > PERIPHERAL_ID_MAX)
  92. return ERR_PTR(-EINVAL);
  93. periph = kzalloc(sizeof(*periph), GFP_KERNEL);
  94. if (!periph)
  95. return ERR_PTR(-ENOMEM);
  96. init.name = name;
  97. init.ops = &peripheral_ops;
  98. init.parent_names = (parent_name ? &parent_name : NULL);
  99. init.num_parents = (parent_name ? 1 : 0);
  100. init.flags = 0;
  101. periph->id = id;
  102. periph->hw.init = &init;
  103. periph->pmc = pmc;
  104. clk = clk_register(NULL, &periph->hw);
  105. if (IS_ERR(clk))
  106. kfree(periph);
  107. return clk;
  108. }
  109. static void clk_sam9x5_peripheral_autodiv(struct clk_sam9x5_peripheral *periph)
  110. {
  111. struct clk *parent;
  112. unsigned long parent_rate;
  113. int shift = 0;
  114. if (!periph->auto_div)
  115. return;
  116. if (periph->range.max) {
  117. parent = clk_get_parent_by_index(periph->hw.clk, 0);
  118. parent_rate = __clk_get_rate(parent);
  119. if (!parent_rate)
  120. return;
  121. for (; shift < PERIPHERAL_MAX_SHIFT; shift++) {
  122. if (parent_rate >> shift <= periph->range.max)
  123. break;
  124. }
  125. }
  126. periph->auto_div = false;
  127. periph->div = shift;
  128. }
  129. static int clk_sam9x5_peripheral_enable(struct clk_hw *hw)
  130. {
  131. struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
  132. struct at91_pmc *pmc = periph->pmc;
  133. if (periph->id < PERIPHERAL_ID_MIN)
  134. return 0;
  135. pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID) |
  136. AT91_PMC_PCR_CMD |
  137. AT91_PMC_PCR_DIV(periph->div) |
  138. AT91_PMC_PCR_EN);
  139. return 0;
  140. }
  141. static void clk_sam9x5_peripheral_disable(struct clk_hw *hw)
  142. {
  143. struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
  144. struct at91_pmc *pmc = periph->pmc;
  145. if (periph->id < PERIPHERAL_ID_MIN)
  146. return;
  147. pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID) |
  148. AT91_PMC_PCR_CMD);
  149. }
  150. static int clk_sam9x5_peripheral_is_enabled(struct clk_hw *hw)
  151. {
  152. struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
  153. struct at91_pmc *pmc = periph->pmc;
  154. int ret;
  155. if (periph->id < PERIPHERAL_ID_MIN)
  156. return 1;
  157. pmc_lock(pmc);
  158. pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID));
  159. ret = !!(pmc_read(pmc, AT91_PMC_PCR) & AT91_PMC_PCR_EN);
  160. pmc_unlock(pmc);
  161. return ret;
  162. }
  163. static unsigned long
  164. clk_sam9x5_peripheral_recalc_rate(struct clk_hw *hw,
  165. unsigned long parent_rate)
  166. {
  167. struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
  168. struct at91_pmc *pmc = periph->pmc;
  169. u32 tmp;
  170. if (periph->id < PERIPHERAL_ID_MIN)
  171. return parent_rate;
  172. pmc_lock(pmc);
  173. pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID));
  174. tmp = pmc_read(pmc, AT91_PMC_PCR);
  175. pmc_unlock(pmc);
  176. if (tmp & AT91_PMC_PCR_EN) {
  177. periph->div = PERIPHERAL_RSHIFT(tmp);
  178. periph->auto_div = false;
  179. } else {
  180. clk_sam9x5_peripheral_autodiv(periph);
  181. }
  182. return parent_rate >> periph->div;
  183. }
  184. static long clk_sam9x5_peripheral_round_rate(struct clk_hw *hw,
  185. unsigned long rate,
  186. unsigned long *parent_rate)
  187. {
  188. int shift = 0;
  189. unsigned long best_rate;
  190. unsigned long best_diff;
  191. unsigned long cur_rate = *parent_rate;
  192. unsigned long cur_diff;
  193. struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
  194. if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max)
  195. return *parent_rate;
  196. if (periph->range.max) {
  197. for (; shift < PERIPHERAL_MAX_SHIFT; shift++) {
  198. cur_rate = *parent_rate >> shift;
  199. if (cur_rate <= periph->range.max)
  200. break;
  201. }
  202. }
  203. if (rate >= cur_rate)
  204. return cur_rate;
  205. best_diff = cur_rate - rate;
  206. best_rate = cur_rate;
  207. for (; shift < PERIPHERAL_MAX_SHIFT; shift++) {
  208. cur_rate = *parent_rate >> shift;
  209. if (cur_rate < rate)
  210. cur_diff = rate - cur_rate;
  211. else
  212. cur_diff = cur_rate - rate;
  213. if (cur_diff < best_diff) {
  214. best_diff = cur_diff;
  215. best_rate = cur_rate;
  216. }
  217. if (!best_diff || cur_rate < rate)
  218. break;
  219. }
  220. return best_rate;
  221. }
  222. static int clk_sam9x5_peripheral_set_rate(struct clk_hw *hw,
  223. unsigned long rate,
  224. unsigned long parent_rate)
  225. {
  226. int shift;
  227. struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
  228. if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max) {
  229. if (parent_rate == rate)
  230. return 0;
  231. else
  232. return -EINVAL;
  233. }
  234. if (periph->range.max && rate > periph->range.max)
  235. return -EINVAL;
  236. for (shift = 0; shift < PERIPHERAL_MAX_SHIFT; shift++) {
  237. if (parent_rate >> shift == rate) {
  238. periph->auto_div = false;
  239. periph->div = shift;
  240. return 0;
  241. }
  242. }
  243. return -EINVAL;
  244. }
  245. static const struct clk_ops sam9x5_peripheral_ops = {
  246. .enable = clk_sam9x5_peripheral_enable,
  247. .disable = clk_sam9x5_peripheral_disable,
  248. .is_enabled = clk_sam9x5_peripheral_is_enabled,
  249. .recalc_rate = clk_sam9x5_peripheral_recalc_rate,
  250. .round_rate = clk_sam9x5_peripheral_round_rate,
  251. .set_rate = clk_sam9x5_peripheral_set_rate,
  252. };
  253. static struct clk * __init
  254. at91_clk_register_sam9x5_peripheral(struct at91_pmc *pmc, const char *name,
  255. const char *parent_name, u32 id,
  256. const struct clk_range *range)
  257. {
  258. struct clk_sam9x5_peripheral *periph;
  259. struct clk *clk = NULL;
  260. struct clk_init_data init;
  261. if (!pmc || !name || !parent_name)
  262. return ERR_PTR(-EINVAL);
  263. periph = kzalloc(sizeof(*periph), GFP_KERNEL);
  264. if (!periph)
  265. return ERR_PTR(-ENOMEM);
  266. init.name = name;
  267. init.ops = &sam9x5_peripheral_ops;
  268. init.parent_names = (parent_name ? &parent_name : NULL);
  269. init.num_parents = (parent_name ? 1 : 0);
  270. init.flags = 0;
  271. periph->id = id;
  272. periph->hw.init = &init;
  273. periph->div = 0;
  274. periph->pmc = pmc;
  275. periph->auto_div = true;
  276. periph->range = *range;
  277. clk = clk_register(NULL, &periph->hw);
  278. if (IS_ERR(clk))
  279. kfree(periph);
  280. else
  281. clk_sam9x5_peripheral_autodiv(periph);
  282. return clk;
  283. }
  284. static void __init
  285. of_at91_clk_periph_setup(struct device_node *np, struct at91_pmc *pmc, u8 type)
  286. {
  287. int num;
  288. u32 id;
  289. struct clk *clk;
  290. const char *parent_name;
  291. const char *name;
  292. struct device_node *periphclknp;
  293. parent_name = of_clk_get_parent_name(np, 0);
  294. if (!parent_name)
  295. return;
  296. num = of_get_child_count(np);
  297. if (!num || num > PERIPHERAL_MAX)
  298. return;
  299. for_each_child_of_node(np, periphclknp) {
  300. if (of_property_read_u32(periphclknp, "reg", &id))
  301. continue;
  302. if (id >= PERIPHERAL_MAX)
  303. continue;
  304. if (of_property_read_string(np, "clock-output-names", &name))
  305. name = periphclknp->name;
  306. if (type == PERIPHERAL_AT91RM9200) {
  307. clk = at91_clk_register_peripheral(pmc, name,
  308. parent_name, id);
  309. } else {
  310. struct clk_range range = CLK_RANGE(0, 0);
  311. of_at91_get_clk_range(periphclknp,
  312. "atmel,clk-output-range",
  313. &range);
  314. clk = at91_clk_register_sam9x5_peripheral(pmc, name,
  315. parent_name,
  316. id, &range);
  317. }
  318. if (IS_ERR(clk))
  319. continue;
  320. of_clk_add_provider(periphclknp, of_clk_src_simple_get, clk);
  321. }
  322. }
  323. void __init of_at91rm9200_clk_periph_setup(struct device_node *np,
  324. struct at91_pmc *pmc)
  325. {
  326. of_at91_clk_periph_setup(np, pmc, PERIPHERAL_AT91RM9200);
  327. }
  328. void __init of_at91sam9x5_clk_periph_setup(struct device_node *np,
  329. struct at91_pmc *pmc)
  330. {
  331. of_at91_clk_periph_setup(np, pmc, PERIPHERAL_AT91SAM9X5);
  332. }