cache.c 6.4 KB

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  1. /*
  2. * arch/xtensa/mm/cache.c
  3. *
  4. * This file is subject to the terms and conditions of the GNU General Public
  5. * License. See the file "COPYING" in the main directory of this archive
  6. * for more details.
  7. *
  8. * Copyright (C) 2001-2006 Tensilica Inc.
  9. *
  10. * Chris Zankel <chris@zankel.net>
  11. * Joe Taylor
  12. * Marc Gauthier
  13. *
  14. */
  15. #include <linux/init.h>
  16. #include <linux/signal.h>
  17. #include <linux/sched.h>
  18. #include <linux/kernel.h>
  19. #include <linux/errno.h>
  20. #include <linux/string.h>
  21. #include <linux/types.h>
  22. #include <linux/ptrace.h>
  23. #include <linux/bootmem.h>
  24. #include <linux/swap.h>
  25. #include <linux/pagemap.h>
  26. #include <asm/bootparam.h>
  27. #include <asm/mmu_context.h>
  28. #include <asm/tlb.h>
  29. #include <asm/tlbflush.h>
  30. #include <asm/page.h>
  31. #include <asm/pgalloc.h>
  32. #include <asm/pgtable.h>
  33. //#define printd(x...) printk(x)
  34. #define printd(x...) do { } while(0)
  35. /*
  36. * Note:
  37. * The kernel provides one architecture bit PG_arch_1 in the page flags that
  38. * can be used for cache coherency.
  39. *
  40. * I$-D$ coherency.
  41. *
  42. * The Xtensa architecture doesn't keep the instruction cache coherent with
  43. * the data cache. We use the architecture bit to indicate if the caches
  44. * are coherent. The kernel clears this bit whenever a page is added to the
  45. * page cache. At that time, the caches might not be in sync. We, therefore,
  46. * define this flag as 'clean' if set.
  47. *
  48. * D-cache aliasing.
  49. *
  50. * With cache aliasing, we have to always flush the cache when pages are
  51. * unmapped (see tlb_start_vma(). So, we use this flag to indicate a dirty
  52. * page.
  53. *
  54. *
  55. *
  56. */
  57. #if (DCACHE_WAY_SIZE > PAGE_SIZE) && defined(CONFIG_HIGHMEM)
  58. #error "HIGHMEM is not supported on cores with aliasing cache."
  59. #endif
  60. #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
  61. /*
  62. * Any time the kernel writes to a user page cache page, or it is about to
  63. * read from a page cache page this routine is called.
  64. *
  65. */
  66. void flush_dcache_page(struct page *page)
  67. {
  68. struct address_space *mapping = page_mapping(page);
  69. /*
  70. * If we have a mapping but the page is not mapped to user-space
  71. * yet, we simply mark this page dirty and defer flushing the
  72. * caches until update_mmu().
  73. */
  74. if (mapping && !mapping_mapped(mapping)) {
  75. if (!test_bit(PG_arch_1, &page->flags))
  76. set_bit(PG_arch_1, &page->flags);
  77. return;
  78. } else {
  79. unsigned long phys = page_to_phys(page);
  80. unsigned long temp = page->index << PAGE_SHIFT;
  81. unsigned long alias = !(DCACHE_ALIAS_EQ(temp, phys));
  82. unsigned long virt;
  83. /*
  84. * Flush the page in kernel space and user space.
  85. * Note that we can omit that step if aliasing is not
  86. * an issue, but we do have to synchronize I$ and D$
  87. * if we have a mapping.
  88. */
  89. if (!alias && !mapping)
  90. return;
  91. __flush_invalidate_dcache_page((long)page_address(page));
  92. virt = TLBTEMP_BASE_1 + (temp & DCACHE_ALIAS_MASK);
  93. if (alias)
  94. __flush_invalidate_dcache_page_alias(virt, phys);
  95. if (mapping)
  96. __invalidate_icache_page_alias(virt, phys);
  97. }
  98. /* There shouldn't be an entry in the cache for this page anymore. */
  99. }
  100. /*
  101. * For now, flush the whole cache. FIXME??
  102. */
  103. void local_flush_cache_range(struct vm_area_struct *vma,
  104. unsigned long start, unsigned long end)
  105. {
  106. __flush_invalidate_dcache_all();
  107. __invalidate_icache_all();
  108. }
  109. /*
  110. * Remove any entry in the cache for this page.
  111. *
  112. * Note that this function is only called for user pages, so use the
  113. * alias versions of the cache flush functions.
  114. */
  115. void local_flush_cache_page(struct vm_area_struct *vma, unsigned long address,
  116. unsigned long pfn)
  117. {
  118. /* Note that we have to use the 'alias' address to avoid multi-hit */
  119. unsigned long phys = page_to_phys(pfn_to_page(pfn));
  120. unsigned long virt = TLBTEMP_BASE_1 + (address & DCACHE_ALIAS_MASK);
  121. __flush_invalidate_dcache_page_alias(virt, phys);
  122. __invalidate_icache_page_alias(virt, phys);
  123. }
  124. #endif
  125. void
  126. update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t *ptep)
  127. {
  128. unsigned long pfn = pte_pfn(*ptep);
  129. struct page *page;
  130. if (!pfn_valid(pfn))
  131. return;
  132. page = pfn_to_page(pfn);
  133. /* Invalidate old entry in TLBs */
  134. flush_tlb_page(vma, addr);
  135. #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
  136. if (!PageReserved(page) && test_bit(PG_arch_1, &page->flags)) {
  137. unsigned long paddr = (unsigned long) page_address(page);
  138. unsigned long phys = page_to_phys(page);
  139. unsigned long tmp = TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK);
  140. __flush_invalidate_dcache_page(paddr);
  141. __flush_invalidate_dcache_page_alias(tmp, phys);
  142. __invalidate_icache_page_alias(tmp, phys);
  143. clear_bit(PG_arch_1, &page->flags);
  144. }
  145. #else
  146. if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags)
  147. && (vma->vm_flags & VM_EXEC) != 0) {
  148. unsigned long paddr = (unsigned long)kmap_atomic(page);
  149. __flush_dcache_page(paddr);
  150. __invalidate_icache_page(paddr);
  151. set_bit(PG_arch_1, &page->flags);
  152. kunmap_atomic((void *)paddr);
  153. }
  154. #endif
  155. }
  156. /*
  157. * access_process_vm() has called get_user_pages(), which has done a
  158. * flush_dcache_page() on the page.
  159. */
  160. #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
  161. void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
  162. unsigned long vaddr, void *dst, const void *src,
  163. unsigned long len)
  164. {
  165. unsigned long phys = page_to_phys(page);
  166. unsigned long alias = !(DCACHE_ALIAS_EQ(vaddr, phys));
  167. /* Flush and invalidate user page if aliased. */
  168. if (alias) {
  169. unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
  170. __flush_invalidate_dcache_page_alias(t, phys);
  171. }
  172. /* Copy data */
  173. memcpy(dst, src, len);
  174. /*
  175. * Flush and invalidate kernel page if aliased and synchronize
  176. * data and instruction caches for executable pages.
  177. */
  178. if (alias) {
  179. unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
  180. __flush_invalidate_dcache_range((unsigned long) dst, len);
  181. if ((vma->vm_flags & VM_EXEC) != 0)
  182. __invalidate_icache_page_alias(t, phys);
  183. } else if ((vma->vm_flags & VM_EXEC) != 0) {
  184. __flush_dcache_range((unsigned long)dst,len);
  185. __invalidate_icache_range((unsigned long) dst, len);
  186. }
  187. }
  188. extern void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
  189. unsigned long vaddr, void *dst, const void *src,
  190. unsigned long len)
  191. {
  192. unsigned long phys = page_to_phys(page);
  193. unsigned long alias = !(DCACHE_ALIAS_EQ(vaddr, phys));
  194. /*
  195. * Flush user page if aliased.
  196. * (Note: a simply flush would be sufficient)
  197. */
  198. if (alias) {
  199. unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
  200. __flush_invalidate_dcache_page_alias(t, phys);
  201. }
  202. memcpy(dst, src, len);
  203. }
  204. #endif