eeh.c 32 KB

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  1. /*
  2. * Copyright IBM Corporation 2001, 2005, 2006
  3. * Copyright Dave Engebretsen & Todd Inglett 2001
  4. * Copyright Linas Vepstas 2005, 2006
  5. * Copyright 2001-2012 IBM Corporation.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. *
  21. * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com>
  22. */
  23. #include <linux/delay.h>
  24. #include <linux/debugfs.h>
  25. #include <linux/sched.h>
  26. #include <linux/init.h>
  27. #include <linux/list.h>
  28. #include <linux/pci.h>
  29. #include <linux/proc_fs.h>
  30. #include <linux/rbtree.h>
  31. #include <linux/reboot.h>
  32. #include <linux/seq_file.h>
  33. #include <linux/spinlock.h>
  34. #include <linux/export.h>
  35. #include <linux/of.h>
  36. #include <linux/atomic.h>
  37. #include <asm/debug.h>
  38. #include <asm/eeh.h>
  39. #include <asm/eeh_event.h>
  40. #include <asm/io.h>
  41. #include <asm/machdep.h>
  42. #include <asm/ppc-pci.h>
  43. #include <asm/rtas.h>
  44. /** Overview:
  45. * EEH, or "Extended Error Handling" is a PCI bridge technology for
  46. * dealing with PCI bus errors that can't be dealt with within the
  47. * usual PCI framework, except by check-stopping the CPU. Systems
  48. * that are designed for high-availability/reliability cannot afford
  49. * to crash due to a "mere" PCI error, thus the need for EEH.
  50. * An EEH-capable bridge operates by converting a detected error
  51. * into a "slot freeze", taking the PCI adapter off-line, making
  52. * the slot behave, from the OS'es point of view, as if the slot
  53. * were "empty": all reads return 0xff's and all writes are silently
  54. * ignored. EEH slot isolation events can be triggered by parity
  55. * errors on the address or data busses (e.g. during posted writes),
  56. * which in turn might be caused by low voltage on the bus, dust,
  57. * vibration, humidity, radioactivity or plain-old failed hardware.
  58. *
  59. * Note, however, that one of the leading causes of EEH slot
  60. * freeze events are buggy device drivers, buggy device microcode,
  61. * or buggy device hardware. This is because any attempt by the
  62. * device to bus-master data to a memory address that is not
  63. * assigned to the device will trigger a slot freeze. (The idea
  64. * is to prevent devices-gone-wild from corrupting system memory).
  65. * Buggy hardware/drivers will have a miserable time co-existing
  66. * with EEH.
  67. *
  68. * Ideally, a PCI device driver, when suspecting that an isolation
  69. * event has occurred (e.g. by reading 0xff's), will then ask EEH
  70. * whether this is the case, and then take appropriate steps to
  71. * reset the PCI slot, the PCI device, and then resume operations.
  72. * However, until that day, the checking is done here, with the
  73. * eeh_check_failure() routine embedded in the MMIO macros. If
  74. * the slot is found to be isolated, an "EEH Event" is synthesized
  75. * and sent out for processing.
  76. */
  77. /* If a device driver keeps reading an MMIO register in an interrupt
  78. * handler after a slot isolation event, it might be broken.
  79. * This sets the threshold for how many read attempts we allow
  80. * before printing an error message.
  81. */
  82. #define EEH_MAX_FAILS 2100000
  83. /* Time to wait for a PCI slot to report status, in milliseconds */
  84. #define PCI_BUS_RESET_WAIT_MSEC (5*60*1000)
  85. /*
  86. * EEH probe mode support, which is part of the flags,
  87. * is to support multiple platforms for EEH. Some platforms
  88. * like pSeries do PCI emunation based on device tree.
  89. * However, other platforms like powernv probe PCI devices
  90. * from hardware. The flag is used to distinguish that.
  91. * In addition, struct eeh_ops::probe would be invoked for
  92. * particular OF node or PCI device so that the corresponding
  93. * PE would be created there.
  94. */
  95. int eeh_subsystem_flags;
  96. EXPORT_SYMBOL(eeh_subsystem_flags);
  97. /* Platform dependent EEH operations */
  98. struct eeh_ops *eeh_ops = NULL;
  99. /* Lock to avoid races due to multiple reports of an error */
  100. DEFINE_RAW_SPINLOCK(confirm_error_lock);
  101. /* Buffer for reporting pci register dumps. Its here in BSS, and
  102. * not dynamically alloced, so that it ends up in RMO where RTAS
  103. * can access it.
  104. */
  105. #define EEH_PCI_REGS_LOG_LEN 4096
  106. static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN];
  107. /*
  108. * The struct is used to maintain the EEH global statistic
  109. * information. Besides, the EEH global statistics will be
  110. * exported to user space through procfs
  111. */
  112. struct eeh_stats {
  113. u64 no_device; /* PCI device not found */
  114. u64 no_dn; /* OF node not found */
  115. u64 no_cfg_addr; /* Config address not found */
  116. u64 ignored_check; /* EEH check skipped */
  117. u64 total_mmio_ffs; /* Total EEH checks */
  118. u64 false_positives; /* Unnecessary EEH checks */
  119. u64 slot_resets; /* PE reset */
  120. };
  121. static struct eeh_stats eeh_stats;
  122. #define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE)
  123. static int __init eeh_setup(char *str)
  124. {
  125. if (!strcmp(str, "off"))
  126. eeh_subsystem_flags |= EEH_FORCE_DISABLED;
  127. return 1;
  128. }
  129. __setup("eeh=", eeh_setup);
  130. /**
  131. * eeh_gather_pci_data - Copy assorted PCI config space registers to buff
  132. * @edev: device to report data for
  133. * @buf: point to buffer in which to log
  134. * @len: amount of room in buffer
  135. *
  136. * This routine captures assorted PCI configuration space data,
  137. * and puts them into a buffer for RTAS error logging.
  138. */
  139. static size_t eeh_gather_pci_data(struct eeh_dev *edev, char * buf, size_t len)
  140. {
  141. struct device_node *dn = eeh_dev_to_of_node(edev);
  142. u32 cfg;
  143. int cap, i;
  144. int n = 0;
  145. n += scnprintf(buf+n, len-n, "%s\n", dn->full_name);
  146. pr_warn("EEH: of node=%s\n", dn->full_name);
  147. eeh_ops->read_config(dn, PCI_VENDOR_ID, 4, &cfg);
  148. n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg);
  149. pr_warn("EEH: PCI device/vendor: %08x\n", cfg);
  150. eeh_ops->read_config(dn, PCI_COMMAND, 4, &cfg);
  151. n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg);
  152. pr_warn("EEH: PCI cmd/status register: %08x\n", cfg);
  153. /* Gather bridge-specific registers */
  154. if (edev->mode & EEH_DEV_BRIDGE) {
  155. eeh_ops->read_config(dn, PCI_SEC_STATUS, 2, &cfg);
  156. n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg);
  157. pr_warn("EEH: Bridge secondary status: %04x\n", cfg);
  158. eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &cfg);
  159. n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg);
  160. pr_warn("EEH: Bridge control: %04x\n", cfg);
  161. }
  162. /* Dump out the PCI-X command and status regs */
  163. cap = edev->pcix_cap;
  164. if (cap) {
  165. eeh_ops->read_config(dn, cap, 4, &cfg);
  166. n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg);
  167. pr_warn("EEH: PCI-X cmd: %08x\n", cfg);
  168. eeh_ops->read_config(dn, cap+4, 4, &cfg);
  169. n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg);
  170. pr_warn("EEH: PCI-X status: %08x\n", cfg);
  171. }
  172. /* If PCI-E capable, dump PCI-E cap 10 */
  173. cap = edev->pcie_cap;
  174. if (cap) {
  175. n += scnprintf(buf+n, len-n, "pci-e cap10:\n");
  176. pr_warn("EEH: PCI-E capabilities and status follow:\n");
  177. for (i=0; i<=8; i++) {
  178. eeh_ops->read_config(dn, cap+4*i, 4, &cfg);
  179. n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
  180. pr_warn("EEH: PCI-E %02x: %08x\n", i, cfg);
  181. }
  182. }
  183. /* If AER capable, dump it */
  184. cap = edev->aer_cap;
  185. if (cap) {
  186. n += scnprintf(buf+n, len-n, "pci-e AER:\n");
  187. pr_warn("EEH: PCI-E AER capability register set follows:\n");
  188. for (i=0; i<14; i++) {
  189. eeh_ops->read_config(dn, cap+4*i, 4, &cfg);
  190. n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
  191. pr_warn("EEH: PCI-E AER %02x: %08x\n", i, cfg);
  192. }
  193. }
  194. return n;
  195. }
  196. /**
  197. * eeh_slot_error_detail - Generate combined log including driver log and error log
  198. * @pe: EEH PE
  199. * @severity: temporary or permanent error log
  200. *
  201. * This routine should be called to generate the combined log, which
  202. * is comprised of driver log and error log. The driver log is figured
  203. * out from the config space of the corresponding PCI device, while
  204. * the error log is fetched through platform dependent function call.
  205. */
  206. void eeh_slot_error_detail(struct eeh_pe *pe, int severity)
  207. {
  208. size_t loglen = 0;
  209. struct eeh_dev *edev, *tmp;
  210. /*
  211. * When the PHB is fenced or dead, it's pointless to collect
  212. * the data from PCI config space because it should return
  213. * 0xFF's. For ER, we still retrieve the data from the PCI
  214. * config space.
  215. *
  216. * For pHyp, we have to enable IO for log retrieval. Otherwise,
  217. * 0xFF's is always returned from PCI config space.
  218. */
  219. if (!(pe->type & EEH_PE_PHB)) {
  220. if (eeh_probe_mode_devtree())
  221. eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
  222. eeh_ops->configure_bridge(pe);
  223. eeh_pe_restore_bars(pe);
  224. pci_regs_buf[0] = 0;
  225. eeh_pe_for_each_dev(pe, edev, tmp) {
  226. loglen += eeh_gather_pci_data(edev, pci_regs_buf + loglen,
  227. EEH_PCI_REGS_LOG_LEN - loglen);
  228. }
  229. }
  230. eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);
  231. }
  232. /**
  233. * eeh_token_to_phys - Convert EEH address token to phys address
  234. * @token: I/O token, should be address in the form 0xA....
  235. *
  236. * This routine should be called to convert virtual I/O address
  237. * to physical one.
  238. */
  239. static inline unsigned long eeh_token_to_phys(unsigned long token)
  240. {
  241. pte_t *ptep;
  242. unsigned long pa;
  243. int hugepage_shift;
  244. /*
  245. * We won't find hugepages here, iomem
  246. */
  247. ptep = find_linux_pte_or_hugepte(init_mm.pgd, token, &hugepage_shift);
  248. if (!ptep)
  249. return token;
  250. WARN_ON(hugepage_shift);
  251. pa = pte_pfn(*ptep) << PAGE_SHIFT;
  252. return pa | (token & (PAGE_SIZE-1));
  253. }
  254. /*
  255. * On PowerNV platform, we might already have fenced PHB there.
  256. * For that case, it's meaningless to recover frozen PE. Intead,
  257. * We have to handle fenced PHB firstly.
  258. */
  259. static int eeh_phb_check_failure(struct eeh_pe *pe)
  260. {
  261. struct eeh_pe *phb_pe;
  262. unsigned long flags;
  263. int ret;
  264. if (!eeh_probe_mode_dev())
  265. return -EPERM;
  266. /* Find the PHB PE */
  267. phb_pe = eeh_phb_pe_get(pe->phb);
  268. if (!phb_pe) {
  269. pr_warning("%s Can't find PE for PHB#%d\n",
  270. __func__, pe->phb->global_number);
  271. return -EEXIST;
  272. }
  273. /* If the PHB has been in problematic state */
  274. eeh_serialize_lock(&flags);
  275. if (phb_pe->state & EEH_PE_ISOLATED) {
  276. ret = 0;
  277. goto out;
  278. }
  279. /* Check PHB state */
  280. ret = eeh_ops->get_state(phb_pe, NULL);
  281. if ((ret < 0) ||
  282. (ret == EEH_STATE_NOT_SUPPORT) ||
  283. (ret & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) ==
  284. (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) {
  285. ret = 0;
  286. goto out;
  287. }
  288. /* Isolate the PHB and send event */
  289. eeh_pe_state_mark(phb_pe, EEH_PE_ISOLATED);
  290. eeh_serialize_unlock(flags);
  291. pr_err("EEH: PHB#%x failure detected, location: %s\n",
  292. phb_pe->phb->global_number, eeh_pe_loc_get(phb_pe));
  293. dump_stack();
  294. eeh_send_failure_event(phb_pe);
  295. return 1;
  296. out:
  297. eeh_serialize_unlock(flags);
  298. return ret;
  299. }
  300. /**
  301. * eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze
  302. * @edev: eeh device
  303. *
  304. * Check for an EEH failure for the given device node. Call this
  305. * routine if the result of a read was all 0xff's and you want to
  306. * find out if this is due to an EEH slot freeze. This routine
  307. * will query firmware for the EEH status.
  308. *
  309. * Returns 0 if there has not been an EEH error; otherwise returns
  310. * a non-zero value and queues up a slot isolation event notification.
  311. *
  312. * It is safe to call this routine in an interrupt context.
  313. */
  314. int eeh_dev_check_failure(struct eeh_dev *edev)
  315. {
  316. int ret;
  317. int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
  318. unsigned long flags;
  319. struct device_node *dn;
  320. struct pci_dev *dev;
  321. struct eeh_pe *pe, *parent_pe, *phb_pe;
  322. int rc = 0;
  323. const char *location;
  324. eeh_stats.total_mmio_ffs++;
  325. if (!eeh_enabled())
  326. return 0;
  327. if (!edev) {
  328. eeh_stats.no_dn++;
  329. return 0;
  330. }
  331. dn = eeh_dev_to_of_node(edev);
  332. dev = eeh_dev_to_pci_dev(edev);
  333. pe = edev->pe;
  334. /* Access to IO BARs might get this far and still not want checking. */
  335. if (!pe) {
  336. eeh_stats.ignored_check++;
  337. pr_debug("EEH: Ignored check for %s %s\n",
  338. eeh_pci_name(dev), dn->full_name);
  339. return 0;
  340. }
  341. if (!pe->addr && !pe->config_addr) {
  342. eeh_stats.no_cfg_addr++;
  343. return 0;
  344. }
  345. /*
  346. * On PowerNV platform, we might already have fenced PHB
  347. * there and we need take care of that firstly.
  348. */
  349. ret = eeh_phb_check_failure(pe);
  350. if (ret > 0)
  351. return ret;
  352. /* If we already have a pending isolation event for this
  353. * slot, we know it's bad already, we don't need to check.
  354. * Do this checking under a lock; as multiple PCI devices
  355. * in one slot might report errors simultaneously, and we
  356. * only want one error recovery routine running.
  357. */
  358. eeh_serialize_lock(&flags);
  359. rc = 1;
  360. if (pe->state & EEH_PE_ISOLATED) {
  361. pe->check_count++;
  362. if (pe->check_count % EEH_MAX_FAILS == 0) {
  363. location = of_get_property(dn, "ibm,loc-code", NULL);
  364. printk(KERN_ERR "EEH: %d reads ignored for recovering device at "
  365. "location=%s driver=%s pci addr=%s\n",
  366. pe->check_count, location,
  367. eeh_driver_name(dev), eeh_pci_name(dev));
  368. printk(KERN_ERR "EEH: Might be infinite loop in %s driver\n",
  369. eeh_driver_name(dev));
  370. dump_stack();
  371. }
  372. goto dn_unlock;
  373. }
  374. /*
  375. * Now test for an EEH failure. This is VERY expensive.
  376. * Note that the eeh_config_addr may be a parent device
  377. * in the case of a device behind a bridge, or it may be
  378. * function zero of a multi-function device.
  379. * In any case they must share a common PHB.
  380. */
  381. ret = eeh_ops->get_state(pe, NULL);
  382. /* Note that config-io to empty slots may fail;
  383. * they are empty when they don't have children.
  384. * We will punt with the following conditions: Failure to get
  385. * PE's state, EEH not support and Permanently unavailable
  386. * state, PE is in good state.
  387. */
  388. if ((ret < 0) ||
  389. (ret == EEH_STATE_NOT_SUPPORT) ||
  390. ((ret & active_flags) == active_flags)) {
  391. eeh_stats.false_positives++;
  392. pe->false_positives++;
  393. rc = 0;
  394. goto dn_unlock;
  395. }
  396. /*
  397. * It should be corner case that the parent PE has been
  398. * put into frozen state as well. We should take care
  399. * that at first.
  400. */
  401. parent_pe = pe->parent;
  402. while (parent_pe) {
  403. /* Hit the ceiling ? */
  404. if (parent_pe->type & EEH_PE_PHB)
  405. break;
  406. /* Frozen parent PE ? */
  407. ret = eeh_ops->get_state(parent_pe, NULL);
  408. if (ret > 0 &&
  409. (ret & active_flags) != active_flags)
  410. pe = parent_pe;
  411. /* Next parent level */
  412. parent_pe = parent_pe->parent;
  413. }
  414. eeh_stats.slot_resets++;
  415. /* Avoid repeated reports of this failure, including problems
  416. * with other functions on this device, and functions under
  417. * bridges.
  418. */
  419. eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
  420. eeh_serialize_unlock(flags);
  421. /* Most EEH events are due to device driver bugs. Having
  422. * a stack trace will help the device-driver authors figure
  423. * out what happened. So print that out.
  424. */
  425. phb_pe = eeh_phb_pe_get(pe->phb);
  426. pr_err("EEH: Frozen PHB#%x-PE#%x detected\n",
  427. pe->phb->global_number, pe->addr);
  428. pr_err("EEH: PE location: %s, PHB location: %s\n",
  429. eeh_pe_loc_get(pe), eeh_pe_loc_get(phb_pe));
  430. dump_stack();
  431. eeh_send_failure_event(pe);
  432. return 1;
  433. dn_unlock:
  434. eeh_serialize_unlock(flags);
  435. return rc;
  436. }
  437. EXPORT_SYMBOL_GPL(eeh_dev_check_failure);
  438. /**
  439. * eeh_check_failure - Check if all 1's data is due to EEH slot freeze
  440. * @token: I/O token, should be address in the form 0xA....
  441. * @val: value, should be all 1's (XXX why do we need this arg??)
  442. *
  443. * Check for an EEH failure at the given token address. Call this
  444. * routine if the result of a read was all 0xff's and you want to
  445. * find out if this is due to an EEH slot freeze event. This routine
  446. * will query firmware for the EEH status.
  447. *
  448. * Note this routine is safe to call in an interrupt context.
  449. */
  450. unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
  451. {
  452. unsigned long addr;
  453. struct eeh_dev *edev;
  454. /* Finding the phys addr + pci device; this is pretty quick. */
  455. addr = eeh_token_to_phys((unsigned long __force) token);
  456. edev = eeh_addr_cache_get_dev(addr);
  457. if (!edev) {
  458. eeh_stats.no_device++;
  459. return val;
  460. }
  461. eeh_dev_check_failure(edev);
  462. return val;
  463. }
  464. EXPORT_SYMBOL(eeh_check_failure);
  465. /**
  466. * eeh_pci_enable - Enable MMIO or DMA transfers for this slot
  467. * @pe: EEH PE
  468. *
  469. * This routine should be called to reenable frozen MMIO or DMA
  470. * so that it would work correctly again. It's useful while doing
  471. * recovery or log collection on the indicated device.
  472. */
  473. int eeh_pci_enable(struct eeh_pe *pe, int function)
  474. {
  475. int rc, flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
  476. /*
  477. * pHyp doesn't allow to enable IO or DMA on unfrozen PE.
  478. * Also, it's pointless to enable them on unfrozen PE. So
  479. * we have the check here.
  480. */
  481. if (function == EEH_OPT_THAW_MMIO ||
  482. function == EEH_OPT_THAW_DMA) {
  483. rc = eeh_ops->get_state(pe, NULL);
  484. if (rc < 0)
  485. return rc;
  486. /* Needn't to enable or already enabled */
  487. if ((rc == EEH_STATE_NOT_SUPPORT) ||
  488. ((rc & flags) == flags))
  489. return 0;
  490. }
  491. rc = eeh_ops->set_option(pe, function);
  492. if (rc)
  493. pr_warn("%s: Unexpected state change %d on "
  494. "PHB#%d-PE#%x, err=%d\n",
  495. __func__, function, pe->phb->global_number,
  496. pe->addr, rc);
  497. rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
  498. if (rc <= 0)
  499. return rc;
  500. if ((function == EEH_OPT_THAW_MMIO) &&
  501. (rc & EEH_STATE_MMIO_ENABLED))
  502. return 0;
  503. if ((function == EEH_OPT_THAW_DMA) &&
  504. (rc & EEH_STATE_DMA_ENABLED))
  505. return 0;
  506. return rc;
  507. }
  508. /**
  509. * pcibios_set_pcie_slot_reset - Set PCI-E reset state
  510. * @dev: pci device struct
  511. * @state: reset state to enter
  512. *
  513. * Return value:
  514. * 0 if success
  515. */
  516. int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
  517. {
  518. struct eeh_dev *edev = pci_dev_to_eeh_dev(dev);
  519. struct eeh_pe *pe = edev->pe;
  520. if (!pe) {
  521. pr_err("%s: No PE found on PCI device %s\n",
  522. __func__, pci_name(dev));
  523. return -EINVAL;
  524. }
  525. switch (state) {
  526. case pcie_deassert_reset:
  527. eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
  528. break;
  529. case pcie_hot_reset:
  530. eeh_ops->reset(pe, EEH_RESET_HOT);
  531. break;
  532. case pcie_warm_reset:
  533. eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
  534. break;
  535. default:
  536. return -EINVAL;
  537. };
  538. return 0;
  539. }
  540. /**
  541. * eeh_set_pe_freset - Check the required reset for the indicated device
  542. * @data: EEH device
  543. * @flag: return value
  544. *
  545. * Each device might have its preferred reset type: fundamental or
  546. * hot reset. The routine is used to collected the information for
  547. * the indicated device and its children so that the bunch of the
  548. * devices could be reset properly.
  549. */
  550. static void *eeh_set_dev_freset(void *data, void *flag)
  551. {
  552. struct pci_dev *dev;
  553. unsigned int *freset = (unsigned int *)flag;
  554. struct eeh_dev *edev = (struct eeh_dev *)data;
  555. dev = eeh_dev_to_pci_dev(edev);
  556. if (dev)
  557. *freset |= dev->needs_freset;
  558. return NULL;
  559. }
  560. /**
  561. * eeh_reset_pe_once - Assert the pci #RST line for 1/4 second
  562. * @pe: EEH PE
  563. *
  564. * Assert the PCI #RST line for 1/4 second.
  565. */
  566. static void eeh_reset_pe_once(struct eeh_pe *pe)
  567. {
  568. unsigned int freset = 0;
  569. /* Determine type of EEH reset required for
  570. * Partitionable Endpoint, a hot-reset (1)
  571. * or a fundamental reset (3).
  572. * A fundamental reset required by any device under
  573. * Partitionable Endpoint trumps hot-reset.
  574. */
  575. eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset);
  576. if (freset)
  577. eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
  578. else
  579. eeh_ops->reset(pe, EEH_RESET_HOT);
  580. eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
  581. }
  582. /**
  583. * eeh_reset_pe - Reset the indicated PE
  584. * @pe: EEH PE
  585. *
  586. * This routine should be called to reset indicated device, including
  587. * PE. A PE might include multiple PCI devices and sometimes PCI bridges
  588. * might be involved as well.
  589. */
  590. int eeh_reset_pe(struct eeh_pe *pe)
  591. {
  592. int flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
  593. int i, rc;
  594. /* Take three shots at resetting the bus */
  595. for (i=0; i<3; i++) {
  596. eeh_reset_pe_once(pe);
  597. /*
  598. * EEH_PE_ISOLATED is expected to be removed after
  599. * BAR restore.
  600. */
  601. rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
  602. if ((rc & flags) == flags)
  603. return 0;
  604. if (rc < 0) {
  605. pr_err("%s: Unrecoverable slot failure on PHB#%d-PE#%x",
  606. __func__, pe->phb->global_number, pe->addr);
  607. return -1;
  608. }
  609. pr_err("EEH: bus reset %d failed on PHB#%d-PE#%x, rc=%d\n",
  610. i+1, pe->phb->global_number, pe->addr, rc);
  611. }
  612. return -1;
  613. }
  614. /**
  615. * eeh_save_bars - Save device bars
  616. * @edev: PCI device associated EEH device
  617. *
  618. * Save the values of the device bars. Unlike the restore
  619. * routine, this routine is *not* recursive. This is because
  620. * PCI devices are added individually; but, for the restore,
  621. * an entire slot is reset at a time.
  622. */
  623. void eeh_save_bars(struct eeh_dev *edev)
  624. {
  625. int i;
  626. struct device_node *dn;
  627. if (!edev)
  628. return;
  629. dn = eeh_dev_to_of_node(edev);
  630. for (i = 0; i < 16; i++)
  631. eeh_ops->read_config(dn, i * 4, 4, &edev->config_space[i]);
  632. /*
  633. * For PCI bridges including root port, we need enable bus
  634. * master explicitly. Otherwise, it can't fetch IODA table
  635. * entries correctly. So we cache the bit in advance so that
  636. * we can restore it after reset, either PHB range or PE range.
  637. */
  638. if (edev->mode & EEH_DEV_BRIDGE)
  639. edev->config_space[1] |= PCI_COMMAND_MASTER;
  640. }
  641. /**
  642. * eeh_ops_register - Register platform dependent EEH operations
  643. * @ops: platform dependent EEH operations
  644. *
  645. * Register the platform dependent EEH operation callback
  646. * functions. The platform should call this function before
  647. * any other EEH operations.
  648. */
  649. int __init eeh_ops_register(struct eeh_ops *ops)
  650. {
  651. if (!ops->name) {
  652. pr_warning("%s: Invalid EEH ops name for %p\n",
  653. __func__, ops);
  654. return -EINVAL;
  655. }
  656. if (eeh_ops && eeh_ops != ops) {
  657. pr_warning("%s: EEH ops of platform %s already existing (%s)\n",
  658. __func__, eeh_ops->name, ops->name);
  659. return -EEXIST;
  660. }
  661. eeh_ops = ops;
  662. return 0;
  663. }
  664. /**
  665. * eeh_ops_unregister - Unreigster platform dependent EEH operations
  666. * @name: name of EEH platform operations
  667. *
  668. * Unregister the platform dependent EEH operation callback
  669. * functions.
  670. */
  671. int __exit eeh_ops_unregister(const char *name)
  672. {
  673. if (!name || !strlen(name)) {
  674. pr_warning("%s: Invalid EEH ops name\n",
  675. __func__);
  676. return -EINVAL;
  677. }
  678. if (eeh_ops && !strcmp(eeh_ops->name, name)) {
  679. eeh_ops = NULL;
  680. return 0;
  681. }
  682. return -EEXIST;
  683. }
  684. static int eeh_reboot_notifier(struct notifier_block *nb,
  685. unsigned long action, void *unused)
  686. {
  687. eeh_set_enable(false);
  688. return NOTIFY_DONE;
  689. }
  690. static struct notifier_block eeh_reboot_nb = {
  691. .notifier_call = eeh_reboot_notifier,
  692. };
  693. /**
  694. * eeh_init - EEH initialization
  695. *
  696. * Initialize EEH by trying to enable it for all of the adapters in the system.
  697. * As a side effect we can determine here if eeh is supported at all.
  698. * Note that we leave EEH on so failed config cycles won't cause a machine
  699. * check. If a user turns off EEH for a particular adapter they are really
  700. * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't
  701. * grant access to a slot if EEH isn't enabled, and so we always enable
  702. * EEH for all slots/all devices.
  703. *
  704. * The eeh-force-off option disables EEH checking globally, for all slots.
  705. * Even if force-off is set, the EEH hardware is still enabled, so that
  706. * newer systems can boot.
  707. */
  708. int eeh_init(void)
  709. {
  710. struct pci_controller *hose, *tmp;
  711. struct device_node *phb;
  712. static int cnt = 0;
  713. int ret = 0;
  714. /*
  715. * We have to delay the initialization on PowerNV after
  716. * the PCI hierarchy tree has been built because the PEs
  717. * are figured out based on PCI devices instead of device
  718. * tree nodes
  719. */
  720. if (machine_is(powernv) && cnt++ <= 0)
  721. return ret;
  722. /* Register reboot notifier */
  723. ret = register_reboot_notifier(&eeh_reboot_nb);
  724. if (ret) {
  725. pr_warn("%s: Failed to register notifier (%d)\n",
  726. __func__, ret);
  727. return ret;
  728. }
  729. /* call platform initialization function */
  730. if (!eeh_ops) {
  731. pr_warning("%s: Platform EEH operation not found\n",
  732. __func__);
  733. return -EEXIST;
  734. } else if ((ret = eeh_ops->init())) {
  735. pr_warning("%s: Failed to call platform init function (%d)\n",
  736. __func__, ret);
  737. return ret;
  738. }
  739. /* Initialize EEH event */
  740. ret = eeh_event_init();
  741. if (ret)
  742. return ret;
  743. /* Enable EEH for all adapters */
  744. if (eeh_probe_mode_devtree()) {
  745. list_for_each_entry_safe(hose, tmp,
  746. &hose_list, list_node) {
  747. phb = hose->dn;
  748. traverse_pci_devices(phb, eeh_ops->of_probe, NULL);
  749. }
  750. } else if (eeh_probe_mode_dev()) {
  751. list_for_each_entry_safe(hose, tmp,
  752. &hose_list, list_node)
  753. pci_walk_bus(hose->bus, eeh_ops->dev_probe, NULL);
  754. } else {
  755. pr_warn("%s: Invalid probe mode %x",
  756. __func__, eeh_subsystem_flags);
  757. return -EINVAL;
  758. }
  759. /*
  760. * Call platform post-initialization. Actually, It's good chance
  761. * to inform platform that EEH is ready to supply service if the
  762. * I/O cache stuff has been built up.
  763. */
  764. if (eeh_ops->post_init) {
  765. ret = eeh_ops->post_init();
  766. if (ret)
  767. return ret;
  768. }
  769. if (eeh_enabled())
  770. pr_info("EEH: PCI Enhanced I/O Error Handling Enabled\n");
  771. else
  772. pr_warning("EEH: No capable adapters found\n");
  773. return ret;
  774. }
  775. core_initcall_sync(eeh_init);
  776. /**
  777. * eeh_add_device_early - Enable EEH for the indicated device_node
  778. * @dn: device node for which to set up EEH
  779. *
  780. * This routine must be used to perform EEH initialization for PCI
  781. * devices that were added after system boot (e.g. hotplug, dlpar).
  782. * This routine must be called before any i/o is performed to the
  783. * adapter (inluding any config-space i/o).
  784. * Whether this actually enables EEH or not for this device depends
  785. * on the CEC architecture, type of the device, on earlier boot
  786. * command-line arguments & etc.
  787. */
  788. void eeh_add_device_early(struct device_node *dn)
  789. {
  790. struct pci_controller *phb;
  791. /*
  792. * If we're doing EEH probe based on PCI device, we
  793. * would delay the probe until late stage because
  794. * the PCI device isn't available this moment.
  795. */
  796. if (!eeh_probe_mode_devtree())
  797. return;
  798. if (!of_node_to_eeh_dev(dn))
  799. return;
  800. phb = of_node_to_eeh_dev(dn)->phb;
  801. /* USB Bus children of PCI devices will not have BUID's */
  802. if (NULL == phb || 0 == phb->buid)
  803. return;
  804. eeh_ops->of_probe(dn, NULL);
  805. }
  806. /**
  807. * eeh_add_device_tree_early - Enable EEH for the indicated device
  808. * @dn: device node
  809. *
  810. * This routine must be used to perform EEH initialization for the
  811. * indicated PCI device that was added after system boot (e.g.
  812. * hotplug, dlpar).
  813. */
  814. void eeh_add_device_tree_early(struct device_node *dn)
  815. {
  816. struct device_node *sib;
  817. for_each_child_of_node(dn, sib)
  818. eeh_add_device_tree_early(sib);
  819. eeh_add_device_early(dn);
  820. }
  821. EXPORT_SYMBOL_GPL(eeh_add_device_tree_early);
  822. /**
  823. * eeh_add_device_late - Perform EEH initialization for the indicated pci device
  824. * @dev: pci device for which to set up EEH
  825. *
  826. * This routine must be used to complete EEH initialization for PCI
  827. * devices that were added after system boot (e.g. hotplug, dlpar).
  828. */
  829. void eeh_add_device_late(struct pci_dev *dev)
  830. {
  831. struct device_node *dn;
  832. struct eeh_dev *edev;
  833. if (!dev || !eeh_enabled())
  834. return;
  835. pr_debug("EEH: Adding device %s\n", pci_name(dev));
  836. dn = pci_device_to_OF_node(dev);
  837. edev = of_node_to_eeh_dev(dn);
  838. if (edev->pdev == dev) {
  839. pr_debug("EEH: Already referenced !\n");
  840. return;
  841. }
  842. /*
  843. * The EEH cache might not be removed correctly because of
  844. * unbalanced kref to the device during unplug time, which
  845. * relies on pcibios_release_device(). So we have to remove
  846. * that here explicitly.
  847. */
  848. if (edev->pdev) {
  849. eeh_rmv_from_parent_pe(edev);
  850. eeh_addr_cache_rmv_dev(edev->pdev);
  851. eeh_sysfs_remove_device(edev->pdev);
  852. edev->mode &= ~EEH_DEV_SYSFS;
  853. /*
  854. * We definitely should have the PCI device removed
  855. * though it wasn't correctly. So we needn't call
  856. * into error handler afterwards.
  857. */
  858. edev->mode |= EEH_DEV_NO_HANDLER;
  859. edev->pdev = NULL;
  860. dev->dev.archdata.edev = NULL;
  861. }
  862. edev->pdev = dev;
  863. dev->dev.archdata.edev = edev;
  864. /*
  865. * We have to do the EEH probe here because the PCI device
  866. * hasn't been created yet in the early stage.
  867. */
  868. if (eeh_probe_mode_dev())
  869. eeh_ops->dev_probe(dev, NULL);
  870. eeh_addr_cache_insert_dev(dev);
  871. }
  872. /**
  873. * eeh_add_device_tree_late - Perform EEH initialization for the indicated PCI bus
  874. * @bus: PCI bus
  875. *
  876. * This routine must be used to perform EEH initialization for PCI
  877. * devices which are attached to the indicated PCI bus. The PCI bus
  878. * is added after system boot through hotplug or dlpar.
  879. */
  880. void eeh_add_device_tree_late(struct pci_bus *bus)
  881. {
  882. struct pci_dev *dev;
  883. list_for_each_entry(dev, &bus->devices, bus_list) {
  884. eeh_add_device_late(dev);
  885. if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
  886. struct pci_bus *subbus = dev->subordinate;
  887. if (subbus)
  888. eeh_add_device_tree_late(subbus);
  889. }
  890. }
  891. }
  892. EXPORT_SYMBOL_GPL(eeh_add_device_tree_late);
  893. /**
  894. * eeh_add_sysfs_files - Add EEH sysfs files for the indicated PCI bus
  895. * @bus: PCI bus
  896. *
  897. * This routine must be used to add EEH sysfs files for PCI
  898. * devices which are attached to the indicated PCI bus. The PCI bus
  899. * is added after system boot through hotplug or dlpar.
  900. */
  901. void eeh_add_sysfs_files(struct pci_bus *bus)
  902. {
  903. struct pci_dev *dev;
  904. list_for_each_entry(dev, &bus->devices, bus_list) {
  905. eeh_sysfs_add_device(dev);
  906. if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
  907. struct pci_bus *subbus = dev->subordinate;
  908. if (subbus)
  909. eeh_add_sysfs_files(subbus);
  910. }
  911. }
  912. }
  913. EXPORT_SYMBOL_GPL(eeh_add_sysfs_files);
  914. /**
  915. * eeh_remove_device - Undo EEH setup for the indicated pci device
  916. * @dev: pci device to be removed
  917. *
  918. * This routine should be called when a device is removed from
  919. * a running system (e.g. by hotplug or dlpar). It unregisters
  920. * the PCI device from the EEH subsystem. I/O errors affecting
  921. * this device will no longer be detected after this call; thus,
  922. * i/o errors affecting this slot may leave this device unusable.
  923. */
  924. void eeh_remove_device(struct pci_dev *dev)
  925. {
  926. struct eeh_dev *edev;
  927. if (!dev || !eeh_enabled())
  928. return;
  929. edev = pci_dev_to_eeh_dev(dev);
  930. /* Unregister the device with the EEH/PCI address search system */
  931. pr_debug("EEH: Removing device %s\n", pci_name(dev));
  932. if (!edev || !edev->pdev || !edev->pe) {
  933. pr_debug("EEH: Not referenced !\n");
  934. return;
  935. }
  936. /*
  937. * During the hotplug for EEH error recovery, we need the EEH
  938. * device attached to the parent PE in order for BAR restore
  939. * a bit later. So we keep it for BAR restore and remove it
  940. * from the parent PE during the BAR resotre.
  941. */
  942. edev->pdev = NULL;
  943. dev->dev.archdata.edev = NULL;
  944. if (!(edev->pe->state & EEH_PE_KEEP))
  945. eeh_rmv_from_parent_pe(edev);
  946. else
  947. edev->mode |= EEH_DEV_DISCONNECTED;
  948. /*
  949. * We're removing from the PCI subsystem, that means
  950. * the PCI device driver can't support EEH or not
  951. * well. So we rely on hotplug completely to do recovery
  952. * for the specific PCI device.
  953. */
  954. edev->mode |= EEH_DEV_NO_HANDLER;
  955. eeh_addr_cache_rmv_dev(dev);
  956. eeh_sysfs_remove_device(dev);
  957. edev->mode &= ~EEH_DEV_SYSFS;
  958. }
  959. static int proc_eeh_show(struct seq_file *m, void *v)
  960. {
  961. if (!eeh_enabled()) {
  962. seq_printf(m, "EEH Subsystem is globally disabled\n");
  963. seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs);
  964. } else {
  965. seq_printf(m, "EEH Subsystem is enabled\n");
  966. seq_printf(m,
  967. "no device=%llu\n"
  968. "no device node=%llu\n"
  969. "no config address=%llu\n"
  970. "check not wanted=%llu\n"
  971. "eeh_total_mmio_ffs=%llu\n"
  972. "eeh_false_positives=%llu\n"
  973. "eeh_slot_resets=%llu\n",
  974. eeh_stats.no_device,
  975. eeh_stats.no_dn,
  976. eeh_stats.no_cfg_addr,
  977. eeh_stats.ignored_check,
  978. eeh_stats.total_mmio_ffs,
  979. eeh_stats.false_positives,
  980. eeh_stats.slot_resets);
  981. }
  982. return 0;
  983. }
  984. static int proc_eeh_open(struct inode *inode, struct file *file)
  985. {
  986. return single_open(file, proc_eeh_show, NULL);
  987. }
  988. static const struct file_operations proc_eeh_operations = {
  989. .open = proc_eeh_open,
  990. .read = seq_read,
  991. .llseek = seq_lseek,
  992. .release = single_release,
  993. };
  994. #ifdef CONFIG_DEBUG_FS
  995. static int eeh_enable_dbgfs_set(void *data, u64 val)
  996. {
  997. if (val)
  998. eeh_subsystem_flags &= ~EEH_FORCE_DISABLED;
  999. else
  1000. eeh_subsystem_flags |= EEH_FORCE_DISABLED;
  1001. /* Notify the backend */
  1002. if (eeh_ops->post_init)
  1003. eeh_ops->post_init();
  1004. return 0;
  1005. }
  1006. static int eeh_enable_dbgfs_get(void *data, u64 *val)
  1007. {
  1008. if (eeh_enabled())
  1009. *val = 0x1ul;
  1010. else
  1011. *val = 0x0ul;
  1012. return 0;
  1013. }
  1014. DEFINE_SIMPLE_ATTRIBUTE(eeh_enable_dbgfs_ops, eeh_enable_dbgfs_get,
  1015. eeh_enable_dbgfs_set, "0x%llx\n");
  1016. #endif
  1017. static int __init eeh_init_proc(void)
  1018. {
  1019. if (machine_is(pseries) || machine_is(powernv)) {
  1020. proc_create("powerpc/eeh", 0, NULL, &proc_eeh_operations);
  1021. #ifdef CONFIG_DEBUG_FS
  1022. debugfs_create_file("eeh_enable", 0600,
  1023. powerpc_debugfs_root, NULL,
  1024. &eeh_enable_dbgfs_ops);
  1025. #endif
  1026. }
  1027. return 0;
  1028. }
  1029. __initcall(eeh_init_proc);