cputable.c 68 KB

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  1. /*
  2. * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  3. *
  4. * Modifications for ppc64:
  5. * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/string.h>
  13. #include <linux/sched.h>
  14. #include <linux/threads.h>
  15. #include <linux/init.h>
  16. #include <linux/export.h>
  17. #include <asm/oprofile_impl.h>
  18. #include <asm/cputable.h>
  19. #include <asm/prom.h> /* for PTRRELOC on ARCH=ppc */
  20. #include <asm/mmu.h>
  21. #include <asm/setup.h>
  22. struct cpu_spec* cur_cpu_spec = NULL;
  23. EXPORT_SYMBOL(cur_cpu_spec);
  24. /* The platform string corresponding to the real PVR */
  25. const char *powerpc_base_platform;
  26. /* NOTE:
  27. * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  28. * the responsibility of the appropriate CPU save/restore functions to
  29. * eventually copy these settings over. Those save/restore aren't yet
  30. * part of the cputable though. That has to be fixed for both ppc32
  31. * and ppc64
  32. */
  33. #ifdef CONFIG_PPC32
  34. extern void __setup_cpu_e200(unsigned long offset, struct cpu_spec* spec);
  35. extern void __setup_cpu_e500v1(unsigned long offset, struct cpu_spec* spec);
  36. extern void __setup_cpu_e500v2(unsigned long offset, struct cpu_spec* spec);
  37. extern void __setup_cpu_e500mc(unsigned long offset, struct cpu_spec* spec);
  38. extern void __setup_cpu_440ep(unsigned long offset, struct cpu_spec* spec);
  39. extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec);
  40. extern void __setup_cpu_440gx(unsigned long offset, struct cpu_spec* spec);
  41. extern void __setup_cpu_440grx(unsigned long offset, struct cpu_spec* spec);
  42. extern void __setup_cpu_440spe(unsigned long offset, struct cpu_spec* spec);
  43. extern void __setup_cpu_440x5(unsigned long offset, struct cpu_spec* spec);
  44. extern void __setup_cpu_460ex(unsigned long offset, struct cpu_spec* spec);
  45. extern void __setup_cpu_460gt(unsigned long offset, struct cpu_spec* spec);
  46. extern void __setup_cpu_460sx(unsigned long offset, struct cpu_spec *spec);
  47. extern void __setup_cpu_apm821xx(unsigned long offset, struct cpu_spec *spec);
  48. extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
  49. extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
  50. extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
  51. extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
  52. extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
  53. extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
  54. extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
  55. extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
  56. #endif /* CONFIG_PPC32 */
  57. #ifdef CONFIG_PPC64
  58. extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  59. extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec);
  60. extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec);
  61. extern void __setup_cpu_a2(unsigned long offset, struct cpu_spec* spec);
  62. extern void __restore_cpu_pa6t(void);
  63. extern void __restore_cpu_ppc970(void);
  64. extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec);
  65. extern void __restore_cpu_power7(void);
  66. extern void __setup_cpu_power8(unsigned long offset, struct cpu_spec* spec);
  67. extern void __restore_cpu_power8(void);
  68. extern void __restore_cpu_a2(void);
  69. extern void __flush_tlb_power7(unsigned long inval_selector);
  70. extern void __flush_tlb_power8(unsigned long inval_selector);
  71. extern long __machine_check_early_realmode_p7(struct pt_regs *regs);
  72. extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
  73. #endif /* CONFIG_PPC64 */
  74. #if defined(CONFIG_E500)
  75. extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
  76. extern void __setup_cpu_e6500(unsigned long offset, struct cpu_spec* spec);
  77. extern void __restore_cpu_e5500(void);
  78. extern void __restore_cpu_e6500(void);
  79. #endif /* CONFIG_E500 */
  80. /* This table only contains "desktop" CPUs, it need to be filled with embedded
  81. * ones as well...
  82. */
  83. #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  84. PPC_FEATURE_HAS_MMU)
  85. #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
  86. #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
  87. #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\
  88. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  89. #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\
  90. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  91. #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\
  92. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  93. PPC_FEATURE_TRUE_LE | \
  94. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  95. #define COMMON_USER_POWER7 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\
  96. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  97. PPC_FEATURE_TRUE_LE | \
  98. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  99. #define COMMON_USER2_POWER7 (PPC_FEATURE2_DSCR)
  100. #define COMMON_USER_POWER8 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\
  101. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  102. PPC_FEATURE_TRUE_LE | \
  103. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  104. #define COMMON_USER2_POWER8 (PPC_FEATURE2_ARCH_2_07 | \
  105. PPC_FEATURE2_HTM_COMP | PPC_FEATURE2_DSCR | \
  106. PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | \
  107. PPC_FEATURE2_VEC_CRYPTO)
  108. #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
  109. PPC_FEATURE_TRUE_LE | \
  110. PPC_FEATURE_HAS_ALTIVEC_COMP)
  111. #ifdef CONFIG_PPC_BOOK3E_64
  112. #define COMMON_USER_BOOKE (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE)
  113. #else
  114. #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
  115. PPC_FEATURE_BOOKE)
  116. #endif
  117. static struct cpu_spec __initdata cpu_specs[] = {
  118. #ifdef CONFIG_PPC_BOOK3S_64
  119. { /* Power3 */
  120. .pvr_mask = 0xffff0000,
  121. .pvr_value = 0x00400000,
  122. .cpu_name = "POWER3 (630)",
  123. .cpu_features = CPU_FTRS_POWER3,
  124. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  125. .mmu_features = MMU_FTR_HPTE_TABLE,
  126. .icache_bsize = 128,
  127. .dcache_bsize = 128,
  128. .num_pmcs = 8,
  129. .pmc_type = PPC_PMC_IBM,
  130. .oprofile_cpu_type = "ppc64/power3",
  131. .oprofile_type = PPC_OPROFILE_RS64,
  132. .platform = "power3",
  133. },
  134. { /* Power3+ */
  135. .pvr_mask = 0xffff0000,
  136. .pvr_value = 0x00410000,
  137. .cpu_name = "POWER3 (630+)",
  138. .cpu_features = CPU_FTRS_POWER3,
  139. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  140. .mmu_features = MMU_FTR_HPTE_TABLE,
  141. .icache_bsize = 128,
  142. .dcache_bsize = 128,
  143. .num_pmcs = 8,
  144. .pmc_type = PPC_PMC_IBM,
  145. .oprofile_cpu_type = "ppc64/power3",
  146. .oprofile_type = PPC_OPROFILE_RS64,
  147. .platform = "power3",
  148. },
  149. { /* Northstar */
  150. .pvr_mask = 0xffff0000,
  151. .pvr_value = 0x00330000,
  152. .cpu_name = "RS64-II (northstar)",
  153. .cpu_features = CPU_FTRS_RS64,
  154. .cpu_user_features = COMMON_USER_PPC64,
  155. .mmu_features = MMU_FTR_HPTE_TABLE,
  156. .icache_bsize = 128,
  157. .dcache_bsize = 128,
  158. .num_pmcs = 8,
  159. .pmc_type = PPC_PMC_IBM,
  160. .oprofile_cpu_type = "ppc64/rs64",
  161. .oprofile_type = PPC_OPROFILE_RS64,
  162. .platform = "rs64",
  163. },
  164. { /* Pulsar */
  165. .pvr_mask = 0xffff0000,
  166. .pvr_value = 0x00340000,
  167. .cpu_name = "RS64-III (pulsar)",
  168. .cpu_features = CPU_FTRS_RS64,
  169. .cpu_user_features = COMMON_USER_PPC64,
  170. .mmu_features = MMU_FTR_HPTE_TABLE,
  171. .icache_bsize = 128,
  172. .dcache_bsize = 128,
  173. .num_pmcs = 8,
  174. .pmc_type = PPC_PMC_IBM,
  175. .oprofile_cpu_type = "ppc64/rs64",
  176. .oprofile_type = PPC_OPROFILE_RS64,
  177. .platform = "rs64",
  178. },
  179. { /* I-star */
  180. .pvr_mask = 0xffff0000,
  181. .pvr_value = 0x00360000,
  182. .cpu_name = "RS64-III (icestar)",
  183. .cpu_features = CPU_FTRS_RS64,
  184. .cpu_user_features = COMMON_USER_PPC64,
  185. .mmu_features = MMU_FTR_HPTE_TABLE,
  186. .icache_bsize = 128,
  187. .dcache_bsize = 128,
  188. .num_pmcs = 8,
  189. .pmc_type = PPC_PMC_IBM,
  190. .oprofile_cpu_type = "ppc64/rs64",
  191. .oprofile_type = PPC_OPROFILE_RS64,
  192. .platform = "rs64",
  193. },
  194. { /* S-star */
  195. .pvr_mask = 0xffff0000,
  196. .pvr_value = 0x00370000,
  197. .cpu_name = "RS64-IV (sstar)",
  198. .cpu_features = CPU_FTRS_RS64,
  199. .cpu_user_features = COMMON_USER_PPC64,
  200. .mmu_features = MMU_FTR_HPTE_TABLE,
  201. .icache_bsize = 128,
  202. .dcache_bsize = 128,
  203. .num_pmcs = 8,
  204. .pmc_type = PPC_PMC_IBM,
  205. .oprofile_cpu_type = "ppc64/rs64",
  206. .oprofile_type = PPC_OPROFILE_RS64,
  207. .platform = "rs64",
  208. },
  209. { /* Power4 */
  210. .pvr_mask = 0xffff0000,
  211. .pvr_value = 0x00350000,
  212. .cpu_name = "POWER4 (gp)",
  213. .cpu_features = CPU_FTRS_POWER4,
  214. .cpu_user_features = COMMON_USER_POWER4,
  215. .mmu_features = MMU_FTRS_POWER4,
  216. .icache_bsize = 128,
  217. .dcache_bsize = 128,
  218. .num_pmcs = 8,
  219. .pmc_type = PPC_PMC_IBM,
  220. .oprofile_cpu_type = "ppc64/power4",
  221. .oprofile_type = PPC_OPROFILE_POWER4,
  222. .platform = "power4",
  223. },
  224. { /* Power4+ */
  225. .pvr_mask = 0xffff0000,
  226. .pvr_value = 0x00380000,
  227. .cpu_name = "POWER4+ (gq)",
  228. .cpu_features = CPU_FTRS_POWER4,
  229. .cpu_user_features = COMMON_USER_POWER4,
  230. .mmu_features = MMU_FTRS_POWER4,
  231. .icache_bsize = 128,
  232. .dcache_bsize = 128,
  233. .num_pmcs = 8,
  234. .pmc_type = PPC_PMC_IBM,
  235. .oprofile_cpu_type = "ppc64/power4",
  236. .oprofile_type = PPC_OPROFILE_POWER4,
  237. .platform = "power4",
  238. },
  239. { /* PPC970 */
  240. .pvr_mask = 0xffff0000,
  241. .pvr_value = 0x00390000,
  242. .cpu_name = "PPC970",
  243. .cpu_features = CPU_FTRS_PPC970,
  244. .cpu_user_features = COMMON_USER_POWER4 |
  245. PPC_FEATURE_HAS_ALTIVEC_COMP,
  246. .mmu_features = MMU_FTRS_PPC970,
  247. .icache_bsize = 128,
  248. .dcache_bsize = 128,
  249. .num_pmcs = 8,
  250. .pmc_type = PPC_PMC_IBM,
  251. .cpu_setup = __setup_cpu_ppc970,
  252. .cpu_restore = __restore_cpu_ppc970,
  253. .oprofile_cpu_type = "ppc64/970",
  254. .oprofile_type = PPC_OPROFILE_POWER4,
  255. .platform = "ppc970",
  256. },
  257. { /* PPC970FX */
  258. .pvr_mask = 0xffff0000,
  259. .pvr_value = 0x003c0000,
  260. .cpu_name = "PPC970FX",
  261. .cpu_features = CPU_FTRS_PPC970,
  262. .cpu_user_features = COMMON_USER_POWER4 |
  263. PPC_FEATURE_HAS_ALTIVEC_COMP,
  264. .mmu_features = MMU_FTRS_PPC970,
  265. .icache_bsize = 128,
  266. .dcache_bsize = 128,
  267. .num_pmcs = 8,
  268. .pmc_type = PPC_PMC_IBM,
  269. .cpu_setup = __setup_cpu_ppc970,
  270. .cpu_restore = __restore_cpu_ppc970,
  271. .oprofile_cpu_type = "ppc64/970",
  272. .oprofile_type = PPC_OPROFILE_POWER4,
  273. .platform = "ppc970",
  274. },
  275. { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */
  276. .pvr_mask = 0xffffffff,
  277. .pvr_value = 0x00440100,
  278. .cpu_name = "PPC970MP",
  279. .cpu_features = CPU_FTRS_PPC970,
  280. .cpu_user_features = COMMON_USER_POWER4 |
  281. PPC_FEATURE_HAS_ALTIVEC_COMP,
  282. .mmu_features = MMU_FTRS_PPC970,
  283. .icache_bsize = 128,
  284. .dcache_bsize = 128,
  285. .num_pmcs = 8,
  286. .pmc_type = PPC_PMC_IBM,
  287. .cpu_setup = __setup_cpu_ppc970,
  288. .cpu_restore = __restore_cpu_ppc970,
  289. .oprofile_cpu_type = "ppc64/970MP",
  290. .oprofile_type = PPC_OPROFILE_POWER4,
  291. .platform = "ppc970",
  292. },
  293. { /* PPC970MP */
  294. .pvr_mask = 0xffff0000,
  295. .pvr_value = 0x00440000,
  296. .cpu_name = "PPC970MP",
  297. .cpu_features = CPU_FTRS_PPC970,
  298. .cpu_user_features = COMMON_USER_POWER4 |
  299. PPC_FEATURE_HAS_ALTIVEC_COMP,
  300. .mmu_features = MMU_FTRS_PPC970,
  301. .icache_bsize = 128,
  302. .dcache_bsize = 128,
  303. .num_pmcs = 8,
  304. .pmc_type = PPC_PMC_IBM,
  305. .cpu_setup = __setup_cpu_ppc970MP,
  306. .cpu_restore = __restore_cpu_ppc970,
  307. .oprofile_cpu_type = "ppc64/970MP",
  308. .oprofile_type = PPC_OPROFILE_POWER4,
  309. .platform = "ppc970",
  310. },
  311. { /* PPC970GX */
  312. .pvr_mask = 0xffff0000,
  313. .pvr_value = 0x00450000,
  314. .cpu_name = "PPC970GX",
  315. .cpu_features = CPU_FTRS_PPC970,
  316. .cpu_user_features = COMMON_USER_POWER4 |
  317. PPC_FEATURE_HAS_ALTIVEC_COMP,
  318. .mmu_features = MMU_FTRS_PPC970,
  319. .icache_bsize = 128,
  320. .dcache_bsize = 128,
  321. .num_pmcs = 8,
  322. .pmc_type = PPC_PMC_IBM,
  323. .cpu_setup = __setup_cpu_ppc970,
  324. .oprofile_cpu_type = "ppc64/970",
  325. .oprofile_type = PPC_OPROFILE_POWER4,
  326. .platform = "ppc970",
  327. },
  328. { /* Power5 GR */
  329. .pvr_mask = 0xffff0000,
  330. .pvr_value = 0x003a0000,
  331. .cpu_name = "POWER5 (gr)",
  332. .cpu_features = CPU_FTRS_POWER5,
  333. .cpu_user_features = COMMON_USER_POWER5,
  334. .mmu_features = MMU_FTRS_POWER5,
  335. .icache_bsize = 128,
  336. .dcache_bsize = 128,
  337. .num_pmcs = 6,
  338. .pmc_type = PPC_PMC_IBM,
  339. .oprofile_cpu_type = "ppc64/power5",
  340. .oprofile_type = PPC_OPROFILE_POWER4,
  341. /* SIHV / SIPR bits are implemented on POWER4+ (GQ)
  342. * and above but only works on POWER5 and above
  343. */
  344. .oprofile_mmcra_sihv = MMCRA_SIHV,
  345. .oprofile_mmcra_sipr = MMCRA_SIPR,
  346. .platform = "power5",
  347. },
  348. { /* Power5++ */
  349. .pvr_mask = 0xffffff00,
  350. .pvr_value = 0x003b0300,
  351. .cpu_name = "POWER5+ (gs)",
  352. .cpu_features = CPU_FTRS_POWER5,
  353. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  354. .mmu_features = MMU_FTRS_POWER5,
  355. .icache_bsize = 128,
  356. .dcache_bsize = 128,
  357. .num_pmcs = 6,
  358. .oprofile_cpu_type = "ppc64/power5++",
  359. .oprofile_type = PPC_OPROFILE_POWER4,
  360. .oprofile_mmcra_sihv = MMCRA_SIHV,
  361. .oprofile_mmcra_sipr = MMCRA_SIPR,
  362. .platform = "power5+",
  363. },
  364. { /* Power5 GS */
  365. .pvr_mask = 0xffff0000,
  366. .pvr_value = 0x003b0000,
  367. .cpu_name = "POWER5+ (gs)",
  368. .cpu_features = CPU_FTRS_POWER5,
  369. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  370. .mmu_features = MMU_FTRS_POWER5,
  371. .icache_bsize = 128,
  372. .dcache_bsize = 128,
  373. .num_pmcs = 6,
  374. .pmc_type = PPC_PMC_IBM,
  375. .oprofile_cpu_type = "ppc64/power5+",
  376. .oprofile_type = PPC_OPROFILE_POWER4,
  377. .oprofile_mmcra_sihv = MMCRA_SIHV,
  378. .oprofile_mmcra_sipr = MMCRA_SIPR,
  379. .platform = "power5+",
  380. },
  381. { /* POWER6 in P5+ mode; 2.04-compliant processor */
  382. .pvr_mask = 0xffffffff,
  383. .pvr_value = 0x0f000001,
  384. .cpu_name = "POWER5+",
  385. .cpu_features = CPU_FTRS_POWER5,
  386. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  387. .mmu_features = MMU_FTRS_POWER5,
  388. .icache_bsize = 128,
  389. .dcache_bsize = 128,
  390. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  391. .oprofile_type = PPC_OPROFILE_POWER4,
  392. .platform = "power5+",
  393. },
  394. { /* Power6 */
  395. .pvr_mask = 0xffff0000,
  396. .pvr_value = 0x003e0000,
  397. .cpu_name = "POWER6 (raw)",
  398. .cpu_features = CPU_FTRS_POWER6,
  399. .cpu_user_features = COMMON_USER_POWER6 |
  400. PPC_FEATURE_POWER6_EXT,
  401. .mmu_features = MMU_FTRS_POWER6,
  402. .icache_bsize = 128,
  403. .dcache_bsize = 128,
  404. .num_pmcs = 6,
  405. .pmc_type = PPC_PMC_IBM,
  406. .oprofile_cpu_type = "ppc64/power6",
  407. .oprofile_type = PPC_OPROFILE_POWER4,
  408. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  409. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  410. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  411. POWER6_MMCRA_OTHER,
  412. .platform = "power6x",
  413. },
  414. { /* 2.05-compliant processor, i.e. Power6 "architected" mode */
  415. .pvr_mask = 0xffffffff,
  416. .pvr_value = 0x0f000002,
  417. .cpu_name = "POWER6 (architected)",
  418. .cpu_features = CPU_FTRS_POWER6,
  419. .cpu_user_features = COMMON_USER_POWER6,
  420. .mmu_features = MMU_FTRS_POWER6,
  421. .icache_bsize = 128,
  422. .dcache_bsize = 128,
  423. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  424. .oprofile_type = PPC_OPROFILE_POWER4,
  425. .platform = "power6",
  426. },
  427. { /* 2.06-compliant processor, i.e. Power7 "architected" mode */
  428. .pvr_mask = 0xffffffff,
  429. .pvr_value = 0x0f000003,
  430. .cpu_name = "POWER7 (architected)",
  431. .cpu_features = CPU_FTRS_POWER7,
  432. .cpu_user_features = COMMON_USER_POWER7,
  433. .cpu_user_features2 = COMMON_USER2_POWER7,
  434. .mmu_features = MMU_FTRS_POWER7,
  435. .icache_bsize = 128,
  436. .dcache_bsize = 128,
  437. .oprofile_type = PPC_OPROFILE_POWER4,
  438. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  439. .cpu_setup = __setup_cpu_power7,
  440. .cpu_restore = __restore_cpu_power7,
  441. .flush_tlb = __flush_tlb_power7,
  442. .machine_check_early = __machine_check_early_realmode_p7,
  443. .platform = "power7",
  444. },
  445. { /* 2.07-compliant processor, i.e. Power8 "architected" mode */
  446. .pvr_mask = 0xffffffff,
  447. .pvr_value = 0x0f000004,
  448. .cpu_name = "POWER8 (architected)",
  449. .cpu_features = CPU_FTRS_POWER8,
  450. .cpu_user_features = COMMON_USER_POWER8,
  451. .cpu_user_features2 = COMMON_USER2_POWER8,
  452. .mmu_features = MMU_FTRS_POWER8,
  453. .icache_bsize = 128,
  454. .dcache_bsize = 128,
  455. .oprofile_type = PPC_OPROFILE_INVALID,
  456. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  457. .cpu_setup = __setup_cpu_power8,
  458. .cpu_restore = __restore_cpu_power8,
  459. .flush_tlb = __flush_tlb_power8,
  460. .machine_check_early = __machine_check_early_realmode_p8,
  461. .platform = "power8",
  462. },
  463. { /* Power7 */
  464. .pvr_mask = 0xffff0000,
  465. .pvr_value = 0x003f0000,
  466. .cpu_name = "POWER7 (raw)",
  467. .cpu_features = CPU_FTRS_POWER7,
  468. .cpu_user_features = COMMON_USER_POWER7,
  469. .cpu_user_features2 = COMMON_USER2_POWER7,
  470. .mmu_features = MMU_FTRS_POWER7,
  471. .icache_bsize = 128,
  472. .dcache_bsize = 128,
  473. .num_pmcs = 6,
  474. .pmc_type = PPC_PMC_IBM,
  475. .oprofile_cpu_type = "ppc64/power7",
  476. .oprofile_type = PPC_OPROFILE_POWER4,
  477. .cpu_setup = __setup_cpu_power7,
  478. .cpu_restore = __restore_cpu_power7,
  479. .flush_tlb = __flush_tlb_power7,
  480. .machine_check_early = __machine_check_early_realmode_p7,
  481. .platform = "power7",
  482. },
  483. { /* Power7+ */
  484. .pvr_mask = 0xffff0000,
  485. .pvr_value = 0x004A0000,
  486. .cpu_name = "POWER7+ (raw)",
  487. .cpu_features = CPU_FTRS_POWER7,
  488. .cpu_user_features = COMMON_USER_POWER7,
  489. .cpu_user_features2 = COMMON_USER2_POWER7,
  490. .mmu_features = MMU_FTRS_POWER7,
  491. .icache_bsize = 128,
  492. .dcache_bsize = 128,
  493. .num_pmcs = 6,
  494. .pmc_type = PPC_PMC_IBM,
  495. .oprofile_cpu_type = "ppc64/power7",
  496. .oprofile_type = PPC_OPROFILE_POWER4,
  497. .cpu_setup = __setup_cpu_power7,
  498. .cpu_restore = __restore_cpu_power7,
  499. .flush_tlb = __flush_tlb_power7,
  500. .machine_check_early = __machine_check_early_realmode_p7,
  501. .platform = "power7+",
  502. },
  503. { /* Power8E */
  504. .pvr_mask = 0xffff0000,
  505. .pvr_value = 0x004b0000,
  506. .cpu_name = "POWER8E (raw)",
  507. .cpu_features = CPU_FTRS_POWER8E,
  508. .cpu_user_features = COMMON_USER_POWER8,
  509. .cpu_user_features2 = COMMON_USER2_POWER8,
  510. .mmu_features = MMU_FTRS_POWER8,
  511. .icache_bsize = 128,
  512. .dcache_bsize = 128,
  513. .num_pmcs = 6,
  514. .pmc_type = PPC_PMC_IBM,
  515. .oprofile_cpu_type = "ppc64/power8",
  516. .oprofile_type = PPC_OPROFILE_INVALID,
  517. .cpu_setup = __setup_cpu_power8,
  518. .cpu_restore = __restore_cpu_power8,
  519. .flush_tlb = __flush_tlb_power8,
  520. .machine_check_early = __machine_check_early_realmode_p8,
  521. .platform = "power8",
  522. },
  523. { /* Power8 DD1: Does not support doorbell IPIs */
  524. .pvr_mask = 0xffffff00,
  525. .pvr_value = 0x004d0100,
  526. .cpu_name = "POWER8 (raw)",
  527. .cpu_features = CPU_FTRS_POWER8_DD1,
  528. .cpu_user_features = COMMON_USER_POWER8,
  529. .cpu_user_features2 = COMMON_USER2_POWER8,
  530. .mmu_features = MMU_FTRS_POWER8,
  531. .icache_bsize = 128,
  532. .dcache_bsize = 128,
  533. .num_pmcs = 6,
  534. .pmc_type = PPC_PMC_IBM,
  535. .oprofile_cpu_type = "ppc64/power8",
  536. .oprofile_type = PPC_OPROFILE_INVALID,
  537. .cpu_setup = __setup_cpu_power8,
  538. .cpu_restore = __restore_cpu_power8,
  539. .flush_tlb = __flush_tlb_power8,
  540. .machine_check_early = __machine_check_early_realmode_p8,
  541. .platform = "power8",
  542. },
  543. { /* Power8 */
  544. .pvr_mask = 0xffff0000,
  545. .pvr_value = 0x004d0000,
  546. .cpu_name = "POWER8 (raw)",
  547. .cpu_features = CPU_FTRS_POWER8,
  548. .cpu_user_features = COMMON_USER_POWER8,
  549. .cpu_user_features2 = COMMON_USER2_POWER8,
  550. .mmu_features = MMU_FTRS_POWER8,
  551. .icache_bsize = 128,
  552. .dcache_bsize = 128,
  553. .num_pmcs = 6,
  554. .pmc_type = PPC_PMC_IBM,
  555. .oprofile_cpu_type = "ppc64/power8",
  556. .oprofile_type = PPC_OPROFILE_INVALID,
  557. .cpu_setup = __setup_cpu_power8,
  558. .cpu_restore = __restore_cpu_power8,
  559. .flush_tlb = __flush_tlb_power8,
  560. .machine_check_early = __machine_check_early_realmode_p8,
  561. .platform = "power8",
  562. },
  563. { /* Cell Broadband Engine */
  564. .pvr_mask = 0xffff0000,
  565. .pvr_value = 0x00700000,
  566. .cpu_name = "Cell Broadband Engine",
  567. .cpu_features = CPU_FTRS_CELL,
  568. .cpu_user_features = COMMON_USER_PPC64 |
  569. PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
  570. PPC_FEATURE_SMT,
  571. .mmu_features = MMU_FTRS_CELL,
  572. .icache_bsize = 128,
  573. .dcache_bsize = 128,
  574. .num_pmcs = 4,
  575. .pmc_type = PPC_PMC_IBM,
  576. .oprofile_cpu_type = "ppc64/cell-be",
  577. .oprofile_type = PPC_OPROFILE_CELL,
  578. .platform = "ppc-cell-be",
  579. },
  580. { /* PA Semi PA6T */
  581. .pvr_mask = 0x7fff0000,
  582. .pvr_value = 0x00900000,
  583. .cpu_name = "PA6T",
  584. .cpu_features = CPU_FTRS_PA6T,
  585. .cpu_user_features = COMMON_USER_PA6T,
  586. .mmu_features = MMU_FTRS_PA6T,
  587. .icache_bsize = 64,
  588. .dcache_bsize = 64,
  589. .num_pmcs = 6,
  590. .pmc_type = PPC_PMC_PA6T,
  591. .cpu_setup = __setup_cpu_pa6t,
  592. .cpu_restore = __restore_cpu_pa6t,
  593. .oprofile_cpu_type = "ppc64/pa6t",
  594. .oprofile_type = PPC_OPROFILE_PA6T,
  595. .platform = "pa6t",
  596. },
  597. { /* default match */
  598. .pvr_mask = 0x00000000,
  599. .pvr_value = 0x00000000,
  600. .cpu_name = "POWER4 (compatible)",
  601. .cpu_features = CPU_FTRS_COMPATIBLE,
  602. .cpu_user_features = COMMON_USER_PPC64,
  603. .mmu_features = MMU_FTRS_DEFAULT_HPTE_ARCH_V2,
  604. .icache_bsize = 128,
  605. .dcache_bsize = 128,
  606. .num_pmcs = 6,
  607. .pmc_type = PPC_PMC_IBM,
  608. .platform = "power4",
  609. }
  610. #endif /* CONFIG_PPC_BOOK3S_64 */
  611. #ifdef CONFIG_PPC32
  612. #if CLASSIC_PPC
  613. { /* 601 */
  614. .pvr_mask = 0xffff0000,
  615. .pvr_value = 0x00010000,
  616. .cpu_name = "601",
  617. .cpu_features = CPU_FTRS_PPC601,
  618. .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
  619. PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
  620. .mmu_features = MMU_FTR_HPTE_TABLE,
  621. .icache_bsize = 32,
  622. .dcache_bsize = 32,
  623. .machine_check = machine_check_generic,
  624. .platform = "ppc601",
  625. },
  626. { /* 603 */
  627. .pvr_mask = 0xffff0000,
  628. .pvr_value = 0x00030000,
  629. .cpu_name = "603",
  630. .cpu_features = CPU_FTRS_603,
  631. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  632. .mmu_features = 0,
  633. .icache_bsize = 32,
  634. .dcache_bsize = 32,
  635. .cpu_setup = __setup_cpu_603,
  636. .machine_check = machine_check_generic,
  637. .platform = "ppc603",
  638. },
  639. { /* 603e */
  640. .pvr_mask = 0xffff0000,
  641. .pvr_value = 0x00060000,
  642. .cpu_name = "603e",
  643. .cpu_features = CPU_FTRS_603,
  644. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  645. .mmu_features = 0,
  646. .icache_bsize = 32,
  647. .dcache_bsize = 32,
  648. .cpu_setup = __setup_cpu_603,
  649. .machine_check = machine_check_generic,
  650. .platform = "ppc603",
  651. },
  652. { /* 603ev */
  653. .pvr_mask = 0xffff0000,
  654. .pvr_value = 0x00070000,
  655. .cpu_name = "603ev",
  656. .cpu_features = CPU_FTRS_603,
  657. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  658. .mmu_features = 0,
  659. .icache_bsize = 32,
  660. .dcache_bsize = 32,
  661. .cpu_setup = __setup_cpu_603,
  662. .machine_check = machine_check_generic,
  663. .platform = "ppc603",
  664. },
  665. { /* 604 */
  666. .pvr_mask = 0xffff0000,
  667. .pvr_value = 0x00040000,
  668. .cpu_name = "604",
  669. .cpu_features = CPU_FTRS_604,
  670. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  671. .mmu_features = MMU_FTR_HPTE_TABLE,
  672. .icache_bsize = 32,
  673. .dcache_bsize = 32,
  674. .num_pmcs = 2,
  675. .cpu_setup = __setup_cpu_604,
  676. .machine_check = machine_check_generic,
  677. .platform = "ppc604",
  678. },
  679. { /* 604e */
  680. .pvr_mask = 0xfffff000,
  681. .pvr_value = 0x00090000,
  682. .cpu_name = "604e",
  683. .cpu_features = CPU_FTRS_604,
  684. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  685. .mmu_features = MMU_FTR_HPTE_TABLE,
  686. .icache_bsize = 32,
  687. .dcache_bsize = 32,
  688. .num_pmcs = 4,
  689. .cpu_setup = __setup_cpu_604,
  690. .machine_check = machine_check_generic,
  691. .platform = "ppc604",
  692. },
  693. { /* 604r */
  694. .pvr_mask = 0xffff0000,
  695. .pvr_value = 0x00090000,
  696. .cpu_name = "604r",
  697. .cpu_features = CPU_FTRS_604,
  698. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  699. .mmu_features = MMU_FTR_HPTE_TABLE,
  700. .icache_bsize = 32,
  701. .dcache_bsize = 32,
  702. .num_pmcs = 4,
  703. .cpu_setup = __setup_cpu_604,
  704. .machine_check = machine_check_generic,
  705. .platform = "ppc604",
  706. },
  707. { /* 604ev */
  708. .pvr_mask = 0xffff0000,
  709. .pvr_value = 0x000a0000,
  710. .cpu_name = "604ev",
  711. .cpu_features = CPU_FTRS_604,
  712. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  713. .mmu_features = MMU_FTR_HPTE_TABLE,
  714. .icache_bsize = 32,
  715. .dcache_bsize = 32,
  716. .num_pmcs = 4,
  717. .cpu_setup = __setup_cpu_604,
  718. .machine_check = machine_check_generic,
  719. .platform = "ppc604",
  720. },
  721. { /* 740/750 (0x4202, don't support TAU ?) */
  722. .pvr_mask = 0xffffffff,
  723. .pvr_value = 0x00084202,
  724. .cpu_name = "740/750",
  725. .cpu_features = CPU_FTRS_740_NOTAU,
  726. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  727. .mmu_features = MMU_FTR_HPTE_TABLE,
  728. .icache_bsize = 32,
  729. .dcache_bsize = 32,
  730. .num_pmcs = 4,
  731. .cpu_setup = __setup_cpu_750,
  732. .machine_check = machine_check_generic,
  733. .platform = "ppc750",
  734. },
  735. { /* 750CX (80100 and 8010x?) */
  736. .pvr_mask = 0xfffffff0,
  737. .pvr_value = 0x00080100,
  738. .cpu_name = "750CX",
  739. .cpu_features = CPU_FTRS_750,
  740. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  741. .mmu_features = MMU_FTR_HPTE_TABLE,
  742. .icache_bsize = 32,
  743. .dcache_bsize = 32,
  744. .num_pmcs = 4,
  745. .cpu_setup = __setup_cpu_750cx,
  746. .machine_check = machine_check_generic,
  747. .platform = "ppc750",
  748. },
  749. { /* 750CX (82201 and 82202) */
  750. .pvr_mask = 0xfffffff0,
  751. .pvr_value = 0x00082200,
  752. .cpu_name = "750CX",
  753. .cpu_features = CPU_FTRS_750,
  754. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  755. .mmu_features = MMU_FTR_HPTE_TABLE,
  756. .icache_bsize = 32,
  757. .dcache_bsize = 32,
  758. .num_pmcs = 4,
  759. .pmc_type = PPC_PMC_IBM,
  760. .cpu_setup = __setup_cpu_750cx,
  761. .machine_check = machine_check_generic,
  762. .platform = "ppc750",
  763. },
  764. { /* 750CXe (82214) */
  765. .pvr_mask = 0xfffffff0,
  766. .pvr_value = 0x00082210,
  767. .cpu_name = "750CXe",
  768. .cpu_features = CPU_FTRS_750,
  769. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  770. .mmu_features = MMU_FTR_HPTE_TABLE,
  771. .icache_bsize = 32,
  772. .dcache_bsize = 32,
  773. .num_pmcs = 4,
  774. .pmc_type = PPC_PMC_IBM,
  775. .cpu_setup = __setup_cpu_750cx,
  776. .machine_check = machine_check_generic,
  777. .platform = "ppc750",
  778. },
  779. { /* 750CXe "Gekko" (83214) */
  780. .pvr_mask = 0xffffffff,
  781. .pvr_value = 0x00083214,
  782. .cpu_name = "750CXe",
  783. .cpu_features = CPU_FTRS_750,
  784. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  785. .mmu_features = MMU_FTR_HPTE_TABLE,
  786. .icache_bsize = 32,
  787. .dcache_bsize = 32,
  788. .num_pmcs = 4,
  789. .pmc_type = PPC_PMC_IBM,
  790. .cpu_setup = __setup_cpu_750cx,
  791. .machine_check = machine_check_generic,
  792. .platform = "ppc750",
  793. },
  794. { /* 750CL (and "Broadway") */
  795. .pvr_mask = 0xfffff0e0,
  796. .pvr_value = 0x00087000,
  797. .cpu_name = "750CL",
  798. .cpu_features = CPU_FTRS_750CL,
  799. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  800. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  801. .icache_bsize = 32,
  802. .dcache_bsize = 32,
  803. .num_pmcs = 4,
  804. .pmc_type = PPC_PMC_IBM,
  805. .cpu_setup = __setup_cpu_750,
  806. .machine_check = machine_check_generic,
  807. .platform = "ppc750",
  808. .oprofile_cpu_type = "ppc/750",
  809. .oprofile_type = PPC_OPROFILE_G4,
  810. },
  811. { /* 745/755 */
  812. .pvr_mask = 0xfffff000,
  813. .pvr_value = 0x00083000,
  814. .cpu_name = "745/755",
  815. .cpu_features = CPU_FTRS_750,
  816. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  817. .mmu_features = MMU_FTR_HPTE_TABLE,
  818. .icache_bsize = 32,
  819. .dcache_bsize = 32,
  820. .num_pmcs = 4,
  821. .pmc_type = PPC_PMC_IBM,
  822. .cpu_setup = __setup_cpu_750,
  823. .machine_check = machine_check_generic,
  824. .platform = "ppc750",
  825. },
  826. { /* 750FX rev 1.x */
  827. .pvr_mask = 0xffffff00,
  828. .pvr_value = 0x70000100,
  829. .cpu_name = "750FX",
  830. .cpu_features = CPU_FTRS_750FX1,
  831. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  832. .mmu_features = MMU_FTR_HPTE_TABLE,
  833. .icache_bsize = 32,
  834. .dcache_bsize = 32,
  835. .num_pmcs = 4,
  836. .pmc_type = PPC_PMC_IBM,
  837. .cpu_setup = __setup_cpu_750,
  838. .machine_check = machine_check_generic,
  839. .platform = "ppc750",
  840. .oprofile_cpu_type = "ppc/750",
  841. .oprofile_type = PPC_OPROFILE_G4,
  842. },
  843. { /* 750FX rev 2.0 must disable HID0[DPM] */
  844. .pvr_mask = 0xffffffff,
  845. .pvr_value = 0x70000200,
  846. .cpu_name = "750FX",
  847. .cpu_features = CPU_FTRS_750FX2,
  848. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  849. .mmu_features = MMU_FTR_HPTE_TABLE,
  850. .icache_bsize = 32,
  851. .dcache_bsize = 32,
  852. .num_pmcs = 4,
  853. .pmc_type = PPC_PMC_IBM,
  854. .cpu_setup = __setup_cpu_750,
  855. .machine_check = machine_check_generic,
  856. .platform = "ppc750",
  857. .oprofile_cpu_type = "ppc/750",
  858. .oprofile_type = PPC_OPROFILE_G4,
  859. },
  860. { /* 750FX (All revs except 2.0) */
  861. .pvr_mask = 0xffff0000,
  862. .pvr_value = 0x70000000,
  863. .cpu_name = "750FX",
  864. .cpu_features = CPU_FTRS_750FX,
  865. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  866. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  867. .icache_bsize = 32,
  868. .dcache_bsize = 32,
  869. .num_pmcs = 4,
  870. .pmc_type = PPC_PMC_IBM,
  871. .cpu_setup = __setup_cpu_750fx,
  872. .machine_check = machine_check_generic,
  873. .platform = "ppc750",
  874. .oprofile_cpu_type = "ppc/750",
  875. .oprofile_type = PPC_OPROFILE_G4,
  876. },
  877. { /* 750GX */
  878. .pvr_mask = 0xffff0000,
  879. .pvr_value = 0x70020000,
  880. .cpu_name = "750GX",
  881. .cpu_features = CPU_FTRS_750GX,
  882. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  883. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  884. .icache_bsize = 32,
  885. .dcache_bsize = 32,
  886. .num_pmcs = 4,
  887. .pmc_type = PPC_PMC_IBM,
  888. .cpu_setup = __setup_cpu_750fx,
  889. .machine_check = machine_check_generic,
  890. .platform = "ppc750",
  891. .oprofile_cpu_type = "ppc/750",
  892. .oprofile_type = PPC_OPROFILE_G4,
  893. },
  894. { /* 740/750 (L2CR bit need fixup for 740) */
  895. .pvr_mask = 0xffff0000,
  896. .pvr_value = 0x00080000,
  897. .cpu_name = "740/750",
  898. .cpu_features = CPU_FTRS_740,
  899. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  900. .mmu_features = MMU_FTR_HPTE_TABLE,
  901. .icache_bsize = 32,
  902. .dcache_bsize = 32,
  903. .num_pmcs = 4,
  904. .pmc_type = PPC_PMC_IBM,
  905. .cpu_setup = __setup_cpu_750,
  906. .machine_check = machine_check_generic,
  907. .platform = "ppc750",
  908. },
  909. { /* 7400 rev 1.1 ? (no TAU) */
  910. .pvr_mask = 0xffffffff,
  911. .pvr_value = 0x000c1101,
  912. .cpu_name = "7400 (1.1)",
  913. .cpu_features = CPU_FTRS_7400_NOTAU,
  914. .cpu_user_features = COMMON_USER |
  915. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  916. .mmu_features = MMU_FTR_HPTE_TABLE,
  917. .icache_bsize = 32,
  918. .dcache_bsize = 32,
  919. .num_pmcs = 4,
  920. .pmc_type = PPC_PMC_G4,
  921. .cpu_setup = __setup_cpu_7400,
  922. .machine_check = machine_check_generic,
  923. .platform = "ppc7400",
  924. },
  925. { /* 7400 */
  926. .pvr_mask = 0xffff0000,
  927. .pvr_value = 0x000c0000,
  928. .cpu_name = "7400",
  929. .cpu_features = CPU_FTRS_7400,
  930. .cpu_user_features = COMMON_USER |
  931. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  932. .mmu_features = MMU_FTR_HPTE_TABLE,
  933. .icache_bsize = 32,
  934. .dcache_bsize = 32,
  935. .num_pmcs = 4,
  936. .pmc_type = PPC_PMC_G4,
  937. .cpu_setup = __setup_cpu_7400,
  938. .machine_check = machine_check_generic,
  939. .platform = "ppc7400",
  940. },
  941. { /* 7410 */
  942. .pvr_mask = 0xffff0000,
  943. .pvr_value = 0x800c0000,
  944. .cpu_name = "7410",
  945. .cpu_features = CPU_FTRS_7400,
  946. .cpu_user_features = COMMON_USER |
  947. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  948. .mmu_features = MMU_FTR_HPTE_TABLE,
  949. .icache_bsize = 32,
  950. .dcache_bsize = 32,
  951. .num_pmcs = 4,
  952. .pmc_type = PPC_PMC_G4,
  953. .cpu_setup = __setup_cpu_7410,
  954. .machine_check = machine_check_generic,
  955. .platform = "ppc7400",
  956. },
  957. { /* 7450 2.0 - no doze/nap */
  958. .pvr_mask = 0xffffffff,
  959. .pvr_value = 0x80000200,
  960. .cpu_name = "7450",
  961. .cpu_features = CPU_FTRS_7450_20,
  962. .cpu_user_features = COMMON_USER |
  963. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  964. .mmu_features = MMU_FTR_HPTE_TABLE,
  965. .icache_bsize = 32,
  966. .dcache_bsize = 32,
  967. .num_pmcs = 6,
  968. .pmc_type = PPC_PMC_G4,
  969. .cpu_setup = __setup_cpu_745x,
  970. .oprofile_cpu_type = "ppc/7450",
  971. .oprofile_type = PPC_OPROFILE_G4,
  972. .machine_check = machine_check_generic,
  973. .platform = "ppc7450",
  974. },
  975. { /* 7450 2.1 */
  976. .pvr_mask = 0xffffffff,
  977. .pvr_value = 0x80000201,
  978. .cpu_name = "7450",
  979. .cpu_features = CPU_FTRS_7450_21,
  980. .cpu_user_features = COMMON_USER |
  981. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  982. .mmu_features = MMU_FTR_HPTE_TABLE,
  983. .icache_bsize = 32,
  984. .dcache_bsize = 32,
  985. .num_pmcs = 6,
  986. .pmc_type = PPC_PMC_G4,
  987. .cpu_setup = __setup_cpu_745x,
  988. .oprofile_cpu_type = "ppc/7450",
  989. .oprofile_type = PPC_OPROFILE_G4,
  990. .machine_check = machine_check_generic,
  991. .platform = "ppc7450",
  992. },
  993. { /* 7450 2.3 and newer */
  994. .pvr_mask = 0xffff0000,
  995. .pvr_value = 0x80000000,
  996. .cpu_name = "7450",
  997. .cpu_features = CPU_FTRS_7450_23,
  998. .cpu_user_features = COMMON_USER |
  999. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1000. .mmu_features = MMU_FTR_HPTE_TABLE,
  1001. .icache_bsize = 32,
  1002. .dcache_bsize = 32,
  1003. .num_pmcs = 6,
  1004. .pmc_type = PPC_PMC_G4,
  1005. .cpu_setup = __setup_cpu_745x,
  1006. .oprofile_cpu_type = "ppc/7450",
  1007. .oprofile_type = PPC_OPROFILE_G4,
  1008. .machine_check = machine_check_generic,
  1009. .platform = "ppc7450",
  1010. },
  1011. { /* 7455 rev 1.x */
  1012. .pvr_mask = 0xffffff00,
  1013. .pvr_value = 0x80010100,
  1014. .cpu_name = "7455",
  1015. .cpu_features = CPU_FTRS_7455_1,
  1016. .cpu_user_features = COMMON_USER |
  1017. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1018. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1019. .icache_bsize = 32,
  1020. .dcache_bsize = 32,
  1021. .num_pmcs = 6,
  1022. .pmc_type = PPC_PMC_G4,
  1023. .cpu_setup = __setup_cpu_745x,
  1024. .oprofile_cpu_type = "ppc/7450",
  1025. .oprofile_type = PPC_OPROFILE_G4,
  1026. .machine_check = machine_check_generic,
  1027. .platform = "ppc7450",
  1028. },
  1029. { /* 7455 rev 2.0 */
  1030. .pvr_mask = 0xffffffff,
  1031. .pvr_value = 0x80010200,
  1032. .cpu_name = "7455",
  1033. .cpu_features = CPU_FTRS_7455_20,
  1034. .cpu_user_features = COMMON_USER |
  1035. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1036. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1037. .icache_bsize = 32,
  1038. .dcache_bsize = 32,
  1039. .num_pmcs = 6,
  1040. .pmc_type = PPC_PMC_G4,
  1041. .cpu_setup = __setup_cpu_745x,
  1042. .oprofile_cpu_type = "ppc/7450",
  1043. .oprofile_type = PPC_OPROFILE_G4,
  1044. .machine_check = machine_check_generic,
  1045. .platform = "ppc7450",
  1046. },
  1047. { /* 7455 others */
  1048. .pvr_mask = 0xffff0000,
  1049. .pvr_value = 0x80010000,
  1050. .cpu_name = "7455",
  1051. .cpu_features = CPU_FTRS_7455,
  1052. .cpu_user_features = COMMON_USER |
  1053. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1054. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1055. .icache_bsize = 32,
  1056. .dcache_bsize = 32,
  1057. .num_pmcs = 6,
  1058. .pmc_type = PPC_PMC_G4,
  1059. .cpu_setup = __setup_cpu_745x,
  1060. .oprofile_cpu_type = "ppc/7450",
  1061. .oprofile_type = PPC_OPROFILE_G4,
  1062. .machine_check = machine_check_generic,
  1063. .platform = "ppc7450",
  1064. },
  1065. { /* 7447/7457 Rev 1.0 */
  1066. .pvr_mask = 0xffffffff,
  1067. .pvr_value = 0x80020100,
  1068. .cpu_name = "7447/7457",
  1069. .cpu_features = CPU_FTRS_7447_10,
  1070. .cpu_user_features = COMMON_USER |
  1071. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1072. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1073. .icache_bsize = 32,
  1074. .dcache_bsize = 32,
  1075. .num_pmcs = 6,
  1076. .pmc_type = PPC_PMC_G4,
  1077. .cpu_setup = __setup_cpu_745x,
  1078. .oprofile_cpu_type = "ppc/7450",
  1079. .oprofile_type = PPC_OPROFILE_G4,
  1080. .machine_check = machine_check_generic,
  1081. .platform = "ppc7450",
  1082. },
  1083. { /* 7447/7457 Rev 1.1 */
  1084. .pvr_mask = 0xffffffff,
  1085. .pvr_value = 0x80020101,
  1086. .cpu_name = "7447/7457",
  1087. .cpu_features = CPU_FTRS_7447_10,
  1088. .cpu_user_features = COMMON_USER |
  1089. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1090. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1091. .icache_bsize = 32,
  1092. .dcache_bsize = 32,
  1093. .num_pmcs = 6,
  1094. .pmc_type = PPC_PMC_G4,
  1095. .cpu_setup = __setup_cpu_745x,
  1096. .oprofile_cpu_type = "ppc/7450",
  1097. .oprofile_type = PPC_OPROFILE_G4,
  1098. .machine_check = machine_check_generic,
  1099. .platform = "ppc7450",
  1100. },
  1101. { /* 7447/7457 Rev 1.2 and later */
  1102. .pvr_mask = 0xffff0000,
  1103. .pvr_value = 0x80020000,
  1104. .cpu_name = "7447/7457",
  1105. .cpu_features = CPU_FTRS_7447,
  1106. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1107. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1108. .icache_bsize = 32,
  1109. .dcache_bsize = 32,
  1110. .num_pmcs = 6,
  1111. .pmc_type = PPC_PMC_G4,
  1112. .cpu_setup = __setup_cpu_745x,
  1113. .oprofile_cpu_type = "ppc/7450",
  1114. .oprofile_type = PPC_OPROFILE_G4,
  1115. .machine_check = machine_check_generic,
  1116. .platform = "ppc7450",
  1117. },
  1118. { /* 7447A */
  1119. .pvr_mask = 0xffff0000,
  1120. .pvr_value = 0x80030000,
  1121. .cpu_name = "7447A",
  1122. .cpu_features = CPU_FTRS_7447A,
  1123. .cpu_user_features = COMMON_USER |
  1124. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1125. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1126. .icache_bsize = 32,
  1127. .dcache_bsize = 32,
  1128. .num_pmcs = 6,
  1129. .pmc_type = PPC_PMC_G4,
  1130. .cpu_setup = __setup_cpu_745x,
  1131. .oprofile_cpu_type = "ppc/7450",
  1132. .oprofile_type = PPC_OPROFILE_G4,
  1133. .machine_check = machine_check_generic,
  1134. .platform = "ppc7450",
  1135. },
  1136. { /* 7448 */
  1137. .pvr_mask = 0xffff0000,
  1138. .pvr_value = 0x80040000,
  1139. .cpu_name = "7448",
  1140. .cpu_features = CPU_FTRS_7448,
  1141. .cpu_user_features = COMMON_USER |
  1142. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1143. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1144. .icache_bsize = 32,
  1145. .dcache_bsize = 32,
  1146. .num_pmcs = 6,
  1147. .pmc_type = PPC_PMC_G4,
  1148. .cpu_setup = __setup_cpu_745x,
  1149. .oprofile_cpu_type = "ppc/7450",
  1150. .oprofile_type = PPC_OPROFILE_G4,
  1151. .machine_check = machine_check_generic,
  1152. .platform = "ppc7450",
  1153. },
  1154. { /* 82xx (8240, 8245, 8260 are all 603e cores) */
  1155. .pvr_mask = 0x7fff0000,
  1156. .pvr_value = 0x00810000,
  1157. .cpu_name = "82xx",
  1158. .cpu_features = CPU_FTRS_82XX,
  1159. .cpu_user_features = COMMON_USER,
  1160. .mmu_features = 0,
  1161. .icache_bsize = 32,
  1162. .dcache_bsize = 32,
  1163. .cpu_setup = __setup_cpu_603,
  1164. .machine_check = machine_check_generic,
  1165. .platform = "ppc603",
  1166. },
  1167. { /* All G2_LE (603e core, plus some) have the same pvr */
  1168. .pvr_mask = 0x7fff0000,
  1169. .pvr_value = 0x00820000,
  1170. .cpu_name = "G2_LE",
  1171. .cpu_features = CPU_FTRS_G2_LE,
  1172. .cpu_user_features = COMMON_USER,
  1173. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1174. .icache_bsize = 32,
  1175. .dcache_bsize = 32,
  1176. .cpu_setup = __setup_cpu_603,
  1177. .machine_check = machine_check_generic,
  1178. .platform = "ppc603",
  1179. },
  1180. { /* e300c1 (a 603e core, plus some) on 83xx */
  1181. .pvr_mask = 0x7fff0000,
  1182. .pvr_value = 0x00830000,
  1183. .cpu_name = "e300c1",
  1184. .cpu_features = CPU_FTRS_E300,
  1185. .cpu_user_features = COMMON_USER,
  1186. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1187. .icache_bsize = 32,
  1188. .dcache_bsize = 32,
  1189. .cpu_setup = __setup_cpu_603,
  1190. .machine_check = machine_check_generic,
  1191. .platform = "ppc603",
  1192. },
  1193. { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
  1194. .pvr_mask = 0x7fff0000,
  1195. .pvr_value = 0x00840000,
  1196. .cpu_name = "e300c2",
  1197. .cpu_features = CPU_FTRS_E300C2,
  1198. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1199. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1200. MMU_FTR_NEED_DTLB_SW_LRU,
  1201. .icache_bsize = 32,
  1202. .dcache_bsize = 32,
  1203. .cpu_setup = __setup_cpu_603,
  1204. .machine_check = machine_check_generic,
  1205. .platform = "ppc603",
  1206. },
  1207. { /* e300c3 (e300c1, plus one IU, half cache size) on 83xx */
  1208. .pvr_mask = 0x7fff0000,
  1209. .pvr_value = 0x00850000,
  1210. .cpu_name = "e300c3",
  1211. .cpu_features = CPU_FTRS_E300,
  1212. .cpu_user_features = COMMON_USER,
  1213. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1214. MMU_FTR_NEED_DTLB_SW_LRU,
  1215. .icache_bsize = 32,
  1216. .dcache_bsize = 32,
  1217. .cpu_setup = __setup_cpu_603,
  1218. .num_pmcs = 4,
  1219. .oprofile_cpu_type = "ppc/e300",
  1220. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1221. .platform = "ppc603",
  1222. },
  1223. { /* e300c4 (e300c1, plus one IU) */
  1224. .pvr_mask = 0x7fff0000,
  1225. .pvr_value = 0x00860000,
  1226. .cpu_name = "e300c4",
  1227. .cpu_features = CPU_FTRS_E300,
  1228. .cpu_user_features = COMMON_USER,
  1229. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1230. MMU_FTR_NEED_DTLB_SW_LRU,
  1231. .icache_bsize = 32,
  1232. .dcache_bsize = 32,
  1233. .cpu_setup = __setup_cpu_603,
  1234. .machine_check = machine_check_generic,
  1235. .num_pmcs = 4,
  1236. .oprofile_cpu_type = "ppc/e300",
  1237. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1238. .platform = "ppc603",
  1239. },
  1240. { /* default match, we assume split I/D cache & TB (non-601)... */
  1241. .pvr_mask = 0x00000000,
  1242. .pvr_value = 0x00000000,
  1243. .cpu_name = "(generic PPC)",
  1244. .cpu_features = CPU_FTRS_CLASSIC32,
  1245. .cpu_user_features = COMMON_USER,
  1246. .mmu_features = MMU_FTR_HPTE_TABLE,
  1247. .icache_bsize = 32,
  1248. .dcache_bsize = 32,
  1249. .machine_check = machine_check_generic,
  1250. .platform = "ppc603",
  1251. },
  1252. #endif /* CLASSIC_PPC */
  1253. #ifdef CONFIG_8xx
  1254. { /* 8xx */
  1255. .pvr_mask = 0xffff0000,
  1256. .pvr_value = 0x00500000,
  1257. .cpu_name = "8xx",
  1258. /* CPU_FTR_MAYBE_CAN_DOZE is possible,
  1259. * if the 8xx code is there.... */
  1260. .cpu_features = CPU_FTRS_8XX,
  1261. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1262. .mmu_features = MMU_FTR_TYPE_8xx,
  1263. .icache_bsize = 16,
  1264. .dcache_bsize = 16,
  1265. .platform = "ppc823",
  1266. },
  1267. #endif /* CONFIG_8xx */
  1268. #ifdef CONFIG_40x
  1269. { /* 403GC */
  1270. .pvr_mask = 0xffffff00,
  1271. .pvr_value = 0x00200200,
  1272. .cpu_name = "403GC",
  1273. .cpu_features = CPU_FTRS_40X,
  1274. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1275. .mmu_features = MMU_FTR_TYPE_40x,
  1276. .icache_bsize = 16,
  1277. .dcache_bsize = 16,
  1278. .machine_check = machine_check_4xx,
  1279. .platform = "ppc403",
  1280. },
  1281. { /* 403GCX */
  1282. .pvr_mask = 0xffffff00,
  1283. .pvr_value = 0x00201400,
  1284. .cpu_name = "403GCX",
  1285. .cpu_features = CPU_FTRS_40X,
  1286. .cpu_user_features = PPC_FEATURE_32 |
  1287. PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
  1288. .mmu_features = MMU_FTR_TYPE_40x,
  1289. .icache_bsize = 16,
  1290. .dcache_bsize = 16,
  1291. .machine_check = machine_check_4xx,
  1292. .platform = "ppc403",
  1293. },
  1294. { /* 403G ?? */
  1295. .pvr_mask = 0xffff0000,
  1296. .pvr_value = 0x00200000,
  1297. .cpu_name = "403G ??",
  1298. .cpu_features = CPU_FTRS_40X,
  1299. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1300. .mmu_features = MMU_FTR_TYPE_40x,
  1301. .icache_bsize = 16,
  1302. .dcache_bsize = 16,
  1303. .machine_check = machine_check_4xx,
  1304. .platform = "ppc403",
  1305. },
  1306. { /* 405GP */
  1307. .pvr_mask = 0xffff0000,
  1308. .pvr_value = 0x40110000,
  1309. .cpu_name = "405GP",
  1310. .cpu_features = CPU_FTRS_40X,
  1311. .cpu_user_features = PPC_FEATURE_32 |
  1312. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1313. .mmu_features = MMU_FTR_TYPE_40x,
  1314. .icache_bsize = 32,
  1315. .dcache_bsize = 32,
  1316. .machine_check = machine_check_4xx,
  1317. .platform = "ppc405",
  1318. },
  1319. { /* STB 03xxx */
  1320. .pvr_mask = 0xffff0000,
  1321. .pvr_value = 0x40130000,
  1322. .cpu_name = "STB03xxx",
  1323. .cpu_features = CPU_FTRS_40X,
  1324. .cpu_user_features = PPC_FEATURE_32 |
  1325. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1326. .mmu_features = MMU_FTR_TYPE_40x,
  1327. .icache_bsize = 32,
  1328. .dcache_bsize = 32,
  1329. .machine_check = machine_check_4xx,
  1330. .platform = "ppc405",
  1331. },
  1332. { /* STB 04xxx */
  1333. .pvr_mask = 0xffff0000,
  1334. .pvr_value = 0x41810000,
  1335. .cpu_name = "STB04xxx",
  1336. .cpu_features = CPU_FTRS_40X,
  1337. .cpu_user_features = PPC_FEATURE_32 |
  1338. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1339. .mmu_features = MMU_FTR_TYPE_40x,
  1340. .icache_bsize = 32,
  1341. .dcache_bsize = 32,
  1342. .machine_check = machine_check_4xx,
  1343. .platform = "ppc405",
  1344. },
  1345. { /* NP405L */
  1346. .pvr_mask = 0xffff0000,
  1347. .pvr_value = 0x41610000,
  1348. .cpu_name = "NP405L",
  1349. .cpu_features = CPU_FTRS_40X,
  1350. .cpu_user_features = PPC_FEATURE_32 |
  1351. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1352. .mmu_features = MMU_FTR_TYPE_40x,
  1353. .icache_bsize = 32,
  1354. .dcache_bsize = 32,
  1355. .machine_check = machine_check_4xx,
  1356. .platform = "ppc405",
  1357. },
  1358. { /* NP4GS3 */
  1359. .pvr_mask = 0xffff0000,
  1360. .pvr_value = 0x40B10000,
  1361. .cpu_name = "NP4GS3",
  1362. .cpu_features = CPU_FTRS_40X,
  1363. .cpu_user_features = PPC_FEATURE_32 |
  1364. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1365. .mmu_features = MMU_FTR_TYPE_40x,
  1366. .icache_bsize = 32,
  1367. .dcache_bsize = 32,
  1368. .machine_check = machine_check_4xx,
  1369. .platform = "ppc405",
  1370. },
  1371. { /* NP405H */
  1372. .pvr_mask = 0xffff0000,
  1373. .pvr_value = 0x41410000,
  1374. .cpu_name = "NP405H",
  1375. .cpu_features = CPU_FTRS_40X,
  1376. .cpu_user_features = PPC_FEATURE_32 |
  1377. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1378. .mmu_features = MMU_FTR_TYPE_40x,
  1379. .icache_bsize = 32,
  1380. .dcache_bsize = 32,
  1381. .machine_check = machine_check_4xx,
  1382. .platform = "ppc405",
  1383. },
  1384. { /* 405GPr */
  1385. .pvr_mask = 0xffff0000,
  1386. .pvr_value = 0x50910000,
  1387. .cpu_name = "405GPr",
  1388. .cpu_features = CPU_FTRS_40X,
  1389. .cpu_user_features = PPC_FEATURE_32 |
  1390. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1391. .mmu_features = MMU_FTR_TYPE_40x,
  1392. .icache_bsize = 32,
  1393. .dcache_bsize = 32,
  1394. .machine_check = machine_check_4xx,
  1395. .platform = "ppc405",
  1396. },
  1397. { /* STBx25xx */
  1398. .pvr_mask = 0xffff0000,
  1399. .pvr_value = 0x51510000,
  1400. .cpu_name = "STBx25xx",
  1401. .cpu_features = CPU_FTRS_40X,
  1402. .cpu_user_features = PPC_FEATURE_32 |
  1403. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1404. .mmu_features = MMU_FTR_TYPE_40x,
  1405. .icache_bsize = 32,
  1406. .dcache_bsize = 32,
  1407. .machine_check = machine_check_4xx,
  1408. .platform = "ppc405",
  1409. },
  1410. { /* 405LP */
  1411. .pvr_mask = 0xffff0000,
  1412. .pvr_value = 0x41F10000,
  1413. .cpu_name = "405LP",
  1414. .cpu_features = CPU_FTRS_40X,
  1415. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1416. .mmu_features = MMU_FTR_TYPE_40x,
  1417. .icache_bsize = 32,
  1418. .dcache_bsize = 32,
  1419. .machine_check = machine_check_4xx,
  1420. .platform = "ppc405",
  1421. },
  1422. { /* Xilinx Virtex-II Pro */
  1423. .pvr_mask = 0xfffff000,
  1424. .pvr_value = 0x20010000,
  1425. .cpu_name = "Virtex-II Pro",
  1426. .cpu_features = CPU_FTRS_40X,
  1427. .cpu_user_features = PPC_FEATURE_32 |
  1428. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1429. .mmu_features = MMU_FTR_TYPE_40x,
  1430. .icache_bsize = 32,
  1431. .dcache_bsize = 32,
  1432. .machine_check = machine_check_4xx,
  1433. .platform = "ppc405",
  1434. },
  1435. { /* Xilinx Virtex-4 FX */
  1436. .pvr_mask = 0xfffff000,
  1437. .pvr_value = 0x20011000,
  1438. .cpu_name = "Virtex-4 FX",
  1439. .cpu_features = CPU_FTRS_40X,
  1440. .cpu_user_features = PPC_FEATURE_32 |
  1441. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1442. .mmu_features = MMU_FTR_TYPE_40x,
  1443. .icache_bsize = 32,
  1444. .dcache_bsize = 32,
  1445. .machine_check = machine_check_4xx,
  1446. .platform = "ppc405",
  1447. },
  1448. { /* 405EP */
  1449. .pvr_mask = 0xffff0000,
  1450. .pvr_value = 0x51210000,
  1451. .cpu_name = "405EP",
  1452. .cpu_features = CPU_FTRS_40X,
  1453. .cpu_user_features = PPC_FEATURE_32 |
  1454. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1455. .mmu_features = MMU_FTR_TYPE_40x,
  1456. .icache_bsize = 32,
  1457. .dcache_bsize = 32,
  1458. .machine_check = machine_check_4xx,
  1459. .platform = "ppc405",
  1460. },
  1461. { /* 405EX Rev. A/B with Security */
  1462. .pvr_mask = 0xffff000f,
  1463. .pvr_value = 0x12910007,
  1464. .cpu_name = "405EX Rev. A/B",
  1465. .cpu_features = CPU_FTRS_40X,
  1466. .cpu_user_features = PPC_FEATURE_32 |
  1467. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1468. .mmu_features = MMU_FTR_TYPE_40x,
  1469. .icache_bsize = 32,
  1470. .dcache_bsize = 32,
  1471. .machine_check = machine_check_4xx,
  1472. .platform = "ppc405",
  1473. },
  1474. { /* 405EX Rev. C without Security */
  1475. .pvr_mask = 0xffff000f,
  1476. .pvr_value = 0x1291000d,
  1477. .cpu_name = "405EX Rev. C",
  1478. .cpu_features = CPU_FTRS_40X,
  1479. .cpu_user_features = PPC_FEATURE_32 |
  1480. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1481. .mmu_features = MMU_FTR_TYPE_40x,
  1482. .icache_bsize = 32,
  1483. .dcache_bsize = 32,
  1484. .machine_check = machine_check_4xx,
  1485. .platform = "ppc405",
  1486. },
  1487. { /* 405EX Rev. C with Security */
  1488. .pvr_mask = 0xffff000f,
  1489. .pvr_value = 0x1291000f,
  1490. .cpu_name = "405EX Rev. C",
  1491. .cpu_features = CPU_FTRS_40X,
  1492. .cpu_user_features = PPC_FEATURE_32 |
  1493. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1494. .mmu_features = MMU_FTR_TYPE_40x,
  1495. .icache_bsize = 32,
  1496. .dcache_bsize = 32,
  1497. .machine_check = machine_check_4xx,
  1498. .platform = "ppc405",
  1499. },
  1500. { /* 405EX Rev. D without Security */
  1501. .pvr_mask = 0xffff000f,
  1502. .pvr_value = 0x12910003,
  1503. .cpu_name = "405EX Rev. D",
  1504. .cpu_features = CPU_FTRS_40X,
  1505. .cpu_user_features = PPC_FEATURE_32 |
  1506. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1507. .mmu_features = MMU_FTR_TYPE_40x,
  1508. .icache_bsize = 32,
  1509. .dcache_bsize = 32,
  1510. .machine_check = machine_check_4xx,
  1511. .platform = "ppc405",
  1512. },
  1513. { /* 405EX Rev. D with Security */
  1514. .pvr_mask = 0xffff000f,
  1515. .pvr_value = 0x12910005,
  1516. .cpu_name = "405EX Rev. D",
  1517. .cpu_features = CPU_FTRS_40X,
  1518. .cpu_user_features = PPC_FEATURE_32 |
  1519. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1520. .mmu_features = MMU_FTR_TYPE_40x,
  1521. .icache_bsize = 32,
  1522. .dcache_bsize = 32,
  1523. .machine_check = machine_check_4xx,
  1524. .platform = "ppc405",
  1525. },
  1526. { /* 405EXr Rev. A/B without Security */
  1527. .pvr_mask = 0xffff000f,
  1528. .pvr_value = 0x12910001,
  1529. .cpu_name = "405EXr Rev. A/B",
  1530. .cpu_features = CPU_FTRS_40X,
  1531. .cpu_user_features = PPC_FEATURE_32 |
  1532. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1533. .mmu_features = MMU_FTR_TYPE_40x,
  1534. .icache_bsize = 32,
  1535. .dcache_bsize = 32,
  1536. .machine_check = machine_check_4xx,
  1537. .platform = "ppc405",
  1538. },
  1539. { /* 405EXr Rev. C without Security */
  1540. .pvr_mask = 0xffff000f,
  1541. .pvr_value = 0x12910009,
  1542. .cpu_name = "405EXr Rev. C",
  1543. .cpu_features = CPU_FTRS_40X,
  1544. .cpu_user_features = PPC_FEATURE_32 |
  1545. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1546. .mmu_features = MMU_FTR_TYPE_40x,
  1547. .icache_bsize = 32,
  1548. .dcache_bsize = 32,
  1549. .machine_check = machine_check_4xx,
  1550. .platform = "ppc405",
  1551. },
  1552. { /* 405EXr Rev. C with Security */
  1553. .pvr_mask = 0xffff000f,
  1554. .pvr_value = 0x1291000b,
  1555. .cpu_name = "405EXr Rev. C",
  1556. .cpu_features = CPU_FTRS_40X,
  1557. .cpu_user_features = PPC_FEATURE_32 |
  1558. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1559. .mmu_features = MMU_FTR_TYPE_40x,
  1560. .icache_bsize = 32,
  1561. .dcache_bsize = 32,
  1562. .machine_check = machine_check_4xx,
  1563. .platform = "ppc405",
  1564. },
  1565. { /* 405EXr Rev. D without Security */
  1566. .pvr_mask = 0xffff000f,
  1567. .pvr_value = 0x12910000,
  1568. .cpu_name = "405EXr Rev. D",
  1569. .cpu_features = CPU_FTRS_40X,
  1570. .cpu_user_features = PPC_FEATURE_32 |
  1571. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1572. .mmu_features = MMU_FTR_TYPE_40x,
  1573. .icache_bsize = 32,
  1574. .dcache_bsize = 32,
  1575. .machine_check = machine_check_4xx,
  1576. .platform = "ppc405",
  1577. },
  1578. { /* 405EXr Rev. D with Security */
  1579. .pvr_mask = 0xffff000f,
  1580. .pvr_value = 0x12910002,
  1581. .cpu_name = "405EXr Rev. D",
  1582. .cpu_features = CPU_FTRS_40X,
  1583. .cpu_user_features = PPC_FEATURE_32 |
  1584. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1585. .mmu_features = MMU_FTR_TYPE_40x,
  1586. .icache_bsize = 32,
  1587. .dcache_bsize = 32,
  1588. .machine_check = machine_check_4xx,
  1589. .platform = "ppc405",
  1590. },
  1591. {
  1592. /* 405EZ */
  1593. .pvr_mask = 0xffff0000,
  1594. .pvr_value = 0x41510000,
  1595. .cpu_name = "405EZ",
  1596. .cpu_features = CPU_FTRS_40X,
  1597. .cpu_user_features = PPC_FEATURE_32 |
  1598. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1599. .mmu_features = MMU_FTR_TYPE_40x,
  1600. .icache_bsize = 32,
  1601. .dcache_bsize = 32,
  1602. .machine_check = machine_check_4xx,
  1603. .platform = "ppc405",
  1604. },
  1605. { /* APM8018X */
  1606. .pvr_mask = 0xffff0000,
  1607. .pvr_value = 0x7ff11432,
  1608. .cpu_name = "APM8018X",
  1609. .cpu_features = CPU_FTRS_40X,
  1610. .cpu_user_features = PPC_FEATURE_32 |
  1611. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1612. .mmu_features = MMU_FTR_TYPE_40x,
  1613. .icache_bsize = 32,
  1614. .dcache_bsize = 32,
  1615. .machine_check = machine_check_4xx,
  1616. .platform = "ppc405",
  1617. },
  1618. { /* default match */
  1619. .pvr_mask = 0x00000000,
  1620. .pvr_value = 0x00000000,
  1621. .cpu_name = "(generic 40x PPC)",
  1622. .cpu_features = CPU_FTRS_40X,
  1623. .cpu_user_features = PPC_FEATURE_32 |
  1624. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1625. .mmu_features = MMU_FTR_TYPE_40x,
  1626. .icache_bsize = 32,
  1627. .dcache_bsize = 32,
  1628. .machine_check = machine_check_4xx,
  1629. .platform = "ppc405",
  1630. }
  1631. #endif /* CONFIG_40x */
  1632. #ifdef CONFIG_44x
  1633. {
  1634. .pvr_mask = 0xf0000fff,
  1635. .pvr_value = 0x40000850,
  1636. .cpu_name = "440GR Rev. A",
  1637. .cpu_features = CPU_FTRS_44X,
  1638. .cpu_user_features = COMMON_USER_BOOKE,
  1639. .mmu_features = MMU_FTR_TYPE_44x,
  1640. .icache_bsize = 32,
  1641. .dcache_bsize = 32,
  1642. .machine_check = machine_check_4xx,
  1643. .platform = "ppc440",
  1644. },
  1645. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1646. .pvr_mask = 0xf0000fff,
  1647. .pvr_value = 0x40000858,
  1648. .cpu_name = "440EP Rev. A",
  1649. .cpu_features = CPU_FTRS_44X,
  1650. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1651. .mmu_features = MMU_FTR_TYPE_44x,
  1652. .icache_bsize = 32,
  1653. .dcache_bsize = 32,
  1654. .cpu_setup = __setup_cpu_440ep,
  1655. .machine_check = machine_check_4xx,
  1656. .platform = "ppc440",
  1657. },
  1658. {
  1659. .pvr_mask = 0xf0000fff,
  1660. .pvr_value = 0x400008d3,
  1661. .cpu_name = "440GR Rev. B",
  1662. .cpu_features = CPU_FTRS_44X,
  1663. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1664. .mmu_features = MMU_FTR_TYPE_44x,
  1665. .icache_bsize = 32,
  1666. .dcache_bsize = 32,
  1667. .machine_check = machine_check_4xx,
  1668. .platform = "ppc440",
  1669. },
  1670. { /* Matches both physical and logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1671. .pvr_mask = 0xf0000ff7,
  1672. .pvr_value = 0x400008d4,
  1673. .cpu_name = "440EP Rev. C",
  1674. .cpu_features = CPU_FTRS_44X,
  1675. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1676. .mmu_features = MMU_FTR_TYPE_44x,
  1677. .icache_bsize = 32,
  1678. .dcache_bsize = 32,
  1679. .cpu_setup = __setup_cpu_440ep,
  1680. .machine_check = machine_check_4xx,
  1681. .platform = "ppc440",
  1682. },
  1683. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1684. .pvr_mask = 0xf0000fff,
  1685. .pvr_value = 0x400008db,
  1686. .cpu_name = "440EP Rev. B",
  1687. .cpu_features = CPU_FTRS_44X,
  1688. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1689. .mmu_features = MMU_FTR_TYPE_44x,
  1690. .icache_bsize = 32,
  1691. .dcache_bsize = 32,
  1692. .cpu_setup = __setup_cpu_440ep,
  1693. .machine_check = machine_check_4xx,
  1694. .platform = "ppc440",
  1695. },
  1696. { /* 440GRX */
  1697. .pvr_mask = 0xf0000ffb,
  1698. .pvr_value = 0x200008D0,
  1699. .cpu_name = "440GRX",
  1700. .cpu_features = CPU_FTRS_44X,
  1701. .cpu_user_features = COMMON_USER_BOOKE,
  1702. .mmu_features = MMU_FTR_TYPE_44x,
  1703. .icache_bsize = 32,
  1704. .dcache_bsize = 32,
  1705. .cpu_setup = __setup_cpu_440grx,
  1706. .machine_check = machine_check_440A,
  1707. .platform = "ppc440",
  1708. },
  1709. { /* Use logical PVR for 440EPx (logical pvr = pvr | 0x8) */
  1710. .pvr_mask = 0xf0000ffb,
  1711. .pvr_value = 0x200008D8,
  1712. .cpu_name = "440EPX",
  1713. .cpu_features = CPU_FTRS_44X,
  1714. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1715. .mmu_features = MMU_FTR_TYPE_44x,
  1716. .icache_bsize = 32,
  1717. .dcache_bsize = 32,
  1718. .cpu_setup = __setup_cpu_440epx,
  1719. .machine_check = machine_check_440A,
  1720. .platform = "ppc440",
  1721. },
  1722. { /* 440GP Rev. B */
  1723. .pvr_mask = 0xf0000fff,
  1724. .pvr_value = 0x40000440,
  1725. .cpu_name = "440GP Rev. B",
  1726. .cpu_features = CPU_FTRS_44X,
  1727. .cpu_user_features = COMMON_USER_BOOKE,
  1728. .mmu_features = MMU_FTR_TYPE_44x,
  1729. .icache_bsize = 32,
  1730. .dcache_bsize = 32,
  1731. .machine_check = machine_check_4xx,
  1732. .platform = "ppc440gp",
  1733. },
  1734. { /* 440GP Rev. C */
  1735. .pvr_mask = 0xf0000fff,
  1736. .pvr_value = 0x40000481,
  1737. .cpu_name = "440GP Rev. C",
  1738. .cpu_features = CPU_FTRS_44X,
  1739. .cpu_user_features = COMMON_USER_BOOKE,
  1740. .mmu_features = MMU_FTR_TYPE_44x,
  1741. .icache_bsize = 32,
  1742. .dcache_bsize = 32,
  1743. .machine_check = machine_check_4xx,
  1744. .platform = "ppc440gp",
  1745. },
  1746. { /* 440GX Rev. A */
  1747. .pvr_mask = 0xf0000fff,
  1748. .pvr_value = 0x50000850,
  1749. .cpu_name = "440GX Rev. A",
  1750. .cpu_features = CPU_FTRS_44X,
  1751. .cpu_user_features = COMMON_USER_BOOKE,
  1752. .mmu_features = MMU_FTR_TYPE_44x,
  1753. .icache_bsize = 32,
  1754. .dcache_bsize = 32,
  1755. .cpu_setup = __setup_cpu_440gx,
  1756. .machine_check = machine_check_440A,
  1757. .platform = "ppc440",
  1758. },
  1759. { /* 440GX Rev. B */
  1760. .pvr_mask = 0xf0000fff,
  1761. .pvr_value = 0x50000851,
  1762. .cpu_name = "440GX Rev. B",
  1763. .cpu_features = CPU_FTRS_44X,
  1764. .cpu_user_features = COMMON_USER_BOOKE,
  1765. .mmu_features = MMU_FTR_TYPE_44x,
  1766. .icache_bsize = 32,
  1767. .dcache_bsize = 32,
  1768. .cpu_setup = __setup_cpu_440gx,
  1769. .machine_check = machine_check_440A,
  1770. .platform = "ppc440",
  1771. },
  1772. { /* 440GX Rev. C */
  1773. .pvr_mask = 0xf0000fff,
  1774. .pvr_value = 0x50000892,
  1775. .cpu_name = "440GX Rev. C",
  1776. .cpu_features = CPU_FTRS_44X,
  1777. .cpu_user_features = COMMON_USER_BOOKE,
  1778. .mmu_features = MMU_FTR_TYPE_44x,
  1779. .icache_bsize = 32,
  1780. .dcache_bsize = 32,
  1781. .cpu_setup = __setup_cpu_440gx,
  1782. .machine_check = machine_check_440A,
  1783. .platform = "ppc440",
  1784. },
  1785. { /* 440GX Rev. F */
  1786. .pvr_mask = 0xf0000fff,
  1787. .pvr_value = 0x50000894,
  1788. .cpu_name = "440GX Rev. F",
  1789. .cpu_features = CPU_FTRS_44X,
  1790. .cpu_user_features = COMMON_USER_BOOKE,
  1791. .mmu_features = MMU_FTR_TYPE_44x,
  1792. .icache_bsize = 32,
  1793. .dcache_bsize = 32,
  1794. .cpu_setup = __setup_cpu_440gx,
  1795. .machine_check = machine_check_440A,
  1796. .platform = "ppc440",
  1797. },
  1798. { /* 440SP Rev. A */
  1799. .pvr_mask = 0xfff00fff,
  1800. .pvr_value = 0x53200891,
  1801. .cpu_name = "440SP Rev. A",
  1802. .cpu_features = CPU_FTRS_44X,
  1803. .cpu_user_features = COMMON_USER_BOOKE,
  1804. .mmu_features = MMU_FTR_TYPE_44x,
  1805. .icache_bsize = 32,
  1806. .dcache_bsize = 32,
  1807. .machine_check = machine_check_4xx,
  1808. .platform = "ppc440",
  1809. },
  1810. { /* 440SPe Rev. A */
  1811. .pvr_mask = 0xfff00fff,
  1812. .pvr_value = 0x53400890,
  1813. .cpu_name = "440SPe Rev. A",
  1814. .cpu_features = CPU_FTRS_44X,
  1815. .cpu_user_features = COMMON_USER_BOOKE,
  1816. .mmu_features = MMU_FTR_TYPE_44x,
  1817. .icache_bsize = 32,
  1818. .dcache_bsize = 32,
  1819. .cpu_setup = __setup_cpu_440spe,
  1820. .machine_check = machine_check_440A,
  1821. .platform = "ppc440",
  1822. },
  1823. { /* 440SPe Rev. B */
  1824. .pvr_mask = 0xfff00fff,
  1825. .pvr_value = 0x53400891,
  1826. .cpu_name = "440SPe Rev. B",
  1827. .cpu_features = CPU_FTRS_44X,
  1828. .cpu_user_features = COMMON_USER_BOOKE,
  1829. .mmu_features = MMU_FTR_TYPE_44x,
  1830. .icache_bsize = 32,
  1831. .dcache_bsize = 32,
  1832. .cpu_setup = __setup_cpu_440spe,
  1833. .machine_check = machine_check_440A,
  1834. .platform = "ppc440",
  1835. },
  1836. { /* 440 in Xilinx Virtex-5 FXT */
  1837. .pvr_mask = 0xfffffff0,
  1838. .pvr_value = 0x7ff21910,
  1839. .cpu_name = "440 in Virtex-5 FXT",
  1840. .cpu_features = CPU_FTRS_44X,
  1841. .cpu_user_features = COMMON_USER_BOOKE,
  1842. .mmu_features = MMU_FTR_TYPE_44x,
  1843. .icache_bsize = 32,
  1844. .dcache_bsize = 32,
  1845. .cpu_setup = __setup_cpu_440x5,
  1846. .machine_check = machine_check_440A,
  1847. .platform = "ppc440",
  1848. },
  1849. { /* 460EX */
  1850. .pvr_mask = 0xffff0006,
  1851. .pvr_value = 0x13020002,
  1852. .cpu_name = "460EX",
  1853. .cpu_features = CPU_FTRS_440x6,
  1854. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1855. .mmu_features = MMU_FTR_TYPE_44x,
  1856. .icache_bsize = 32,
  1857. .dcache_bsize = 32,
  1858. .cpu_setup = __setup_cpu_460ex,
  1859. .machine_check = machine_check_440A,
  1860. .platform = "ppc440",
  1861. },
  1862. { /* 460EX Rev B */
  1863. .pvr_mask = 0xffff0007,
  1864. .pvr_value = 0x13020004,
  1865. .cpu_name = "460EX Rev. B",
  1866. .cpu_features = CPU_FTRS_440x6,
  1867. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1868. .mmu_features = MMU_FTR_TYPE_44x,
  1869. .icache_bsize = 32,
  1870. .dcache_bsize = 32,
  1871. .cpu_setup = __setup_cpu_460ex,
  1872. .machine_check = machine_check_440A,
  1873. .platform = "ppc440",
  1874. },
  1875. { /* 460GT */
  1876. .pvr_mask = 0xffff0006,
  1877. .pvr_value = 0x13020000,
  1878. .cpu_name = "460GT",
  1879. .cpu_features = CPU_FTRS_440x6,
  1880. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1881. .mmu_features = MMU_FTR_TYPE_44x,
  1882. .icache_bsize = 32,
  1883. .dcache_bsize = 32,
  1884. .cpu_setup = __setup_cpu_460gt,
  1885. .machine_check = machine_check_440A,
  1886. .platform = "ppc440",
  1887. },
  1888. { /* 460GT Rev B */
  1889. .pvr_mask = 0xffff0007,
  1890. .pvr_value = 0x13020005,
  1891. .cpu_name = "460GT Rev. B",
  1892. .cpu_features = CPU_FTRS_440x6,
  1893. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1894. .mmu_features = MMU_FTR_TYPE_44x,
  1895. .icache_bsize = 32,
  1896. .dcache_bsize = 32,
  1897. .cpu_setup = __setup_cpu_460gt,
  1898. .machine_check = machine_check_440A,
  1899. .platform = "ppc440",
  1900. },
  1901. { /* 460SX */
  1902. .pvr_mask = 0xffffff00,
  1903. .pvr_value = 0x13541800,
  1904. .cpu_name = "460SX",
  1905. .cpu_features = CPU_FTRS_44X,
  1906. .cpu_user_features = COMMON_USER_BOOKE,
  1907. .mmu_features = MMU_FTR_TYPE_44x,
  1908. .icache_bsize = 32,
  1909. .dcache_bsize = 32,
  1910. .cpu_setup = __setup_cpu_460sx,
  1911. .machine_check = machine_check_440A,
  1912. .platform = "ppc440",
  1913. },
  1914. { /* 464 in APM821xx */
  1915. .pvr_mask = 0xfffffff0,
  1916. .pvr_value = 0x12C41C80,
  1917. .cpu_name = "APM821XX",
  1918. .cpu_features = CPU_FTRS_44X,
  1919. .cpu_user_features = COMMON_USER_BOOKE |
  1920. PPC_FEATURE_HAS_FPU,
  1921. .mmu_features = MMU_FTR_TYPE_44x,
  1922. .icache_bsize = 32,
  1923. .dcache_bsize = 32,
  1924. .cpu_setup = __setup_cpu_apm821xx,
  1925. .machine_check = machine_check_440A,
  1926. .platform = "ppc440",
  1927. },
  1928. { /* 476 DD2 core */
  1929. .pvr_mask = 0xffffffff,
  1930. .pvr_value = 0x11a52080,
  1931. .cpu_name = "476",
  1932. .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2,
  1933. .cpu_user_features = COMMON_USER_BOOKE |
  1934. PPC_FEATURE_HAS_FPU,
  1935. .mmu_features = MMU_FTR_TYPE_47x |
  1936. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1937. .icache_bsize = 32,
  1938. .dcache_bsize = 128,
  1939. .machine_check = machine_check_47x,
  1940. .platform = "ppc470",
  1941. },
  1942. { /* 476fpe */
  1943. .pvr_mask = 0xffff0000,
  1944. .pvr_value = 0x7ff50000,
  1945. .cpu_name = "476fpe",
  1946. .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2,
  1947. .cpu_user_features = COMMON_USER_BOOKE |
  1948. PPC_FEATURE_HAS_FPU,
  1949. .mmu_features = MMU_FTR_TYPE_47x |
  1950. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1951. .icache_bsize = 32,
  1952. .dcache_bsize = 128,
  1953. .machine_check = machine_check_47x,
  1954. .platform = "ppc470",
  1955. },
  1956. { /* 476 iss */
  1957. .pvr_mask = 0xffff0000,
  1958. .pvr_value = 0x00050000,
  1959. .cpu_name = "476",
  1960. .cpu_features = CPU_FTRS_47X,
  1961. .cpu_user_features = COMMON_USER_BOOKE |
  1962. PPC_FEATURE_HAS_FPU,
  1963. .mmu_features = MMU_FTR_TYPE_47x |
  1964. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1965. .icache_bsize = 32,
  1966. .dcache_bsize = 128,
  1967. .machine_check = machine_check_47x,
  1968. .platform = "ppc470",
  1969. },
  1970. { /* 476 others */
  1971. .pvr_mask = 0xffff0000,
  1972. .pvr_value = 0x11a50000,
  1973. .cpu_name = "476",
  1974. .cpu_features = CPU_FTRS_47X,
  1975. .cpu_user_features = COMMON_USER_BOOKE |
  1976. PPC_FEATURE_HAS_FPU,
  1977. .mmu_features = MMU_FTR_TYPE_47x |
  1978. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1979. .icache_bsize = 32,
  1980. .dcache_bsize = 128,
  1981. .machine_check = machine_check_47x,
  1982. .platform = "ppc470",
  1983. },
  1984. { /* default match */
  1985. .pvr_mask = 0x00000000,
  1986. .pvr_value = 0x00000000,
  1987. .cpu_name = "(generic 44x PPC)",
  1988. .cpu_features = CPU_FTRS_44X,
  1989. .cpu_user_features = COMMON_USER_BOOKE,
  1990. .mmu_features = MMU_FTR_TYPE_44x,
  1991. .icache_bsize = 32,
  1992. .dcache_bsize = 32,
  1993. .machine_check = machine_check_4xx,
  1994. .platform = "ppc440",
  1995. }
  1996. #endif /* CONFIG_44x */
  1997. #ifdef CONFIG_E200
  1998. { /* e200z5 */
  1999. .pvr_mask = 0xfff00000,
  2000. .pvr_value = 0x81000000,
  2001. .cpu_name = "e200z5",
  2002. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  2003. .cpu_features = CPU_FTRS_E200,
  2004. .cpu_user_features = COMMON_USER_BOOKE |
  2005. PPC_FEATURE_HAS_EFP_SINGLE |
  2006. PPC_FEATURE_UNIFIED_CACHE,
  2007. .mmu_features = MMU_FTR_TYPE_FSL_E,
  2008. .dcache_bsize = 32,
  2009. .machine_check = machine_check_e200,
  2010. .platform = "ppc5554",
  2011. },
  2012. { /* e200z6 */
  2013. .pvr_mask = 0xfff00000,
  2014. .pvr_value = 0x81100000,
  2015. .cpu_name = "e200z6",
  2016. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  2017. .cpu_features = CPU_FTRS_E200,
  2018. .cpu_user_features = COMMON_USER_BOOKE |
  2019. PPC_FEATURE_HAS_SPE_COMP |
  2020. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  2021. PPC_FEATURE_UNIFIED_CACHE,
  2022. .mmu_features = MMU_FTR_TYPE_FSL_E,
  2023. .dcache_bsize = 32,
  2024. .machine_check = machine_check_e200,
  2025. .platform = "ppc5554",
  2026. },
  2027. { /* default match */
  2028. .pvr_mask = 0x00000000,
  2029. .pvr_value = 0x00000000,
  2030. .cpu_name = "(generic E200 PPC)",
  2031. .cpu_features = CPU_FTRS_E200,
  2032. .cpu_user_features = COMMON_USER_BOOKE |
  2033. PPC_FEATURE_HAS_EFP_SINGLE |
  2034. PPC_FEATURE_UNIFIED_CACHE,
  2035. .mmu_features = MMU_FTR_TYPE_FSL_E,
  2036. .dcache_bsize = 32,
  2037. .cpu_setup = __setup_cpu_e200,
  2038. .machine_check = machine_check_e200,
  2039. .platform = "ppc5554",
  2040. }
  2041. #endif /* CONFIG_E200 */
  2042. #endif /* CONFIG_PPC32 */
  2043. #ifdef CONFIG_E500
  2044. #ifdef CONFIG_PPC32
  2045. { /* e500 */
  2046. .pvr_mask = 0xffff0000,
  2047. .pvr_value = 0x80200000,
  2048. .cpu_name = "e500",
  2049. .cpu_features = CPU_FTRS_E500,
  2050. .cpu_user_features = COMMON_USER_BOOKE |
  2051. PPC_FEATURE_HAS_SPE_COMP |
  2052. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  2053. .cpu_user_features2 = PPC_FEATURE2_ISEL,
  2054. .mmu_features = MMU_FTR_TYPE_FSL_E,
  2055. .icache_bsize = 32,
  2056. .dcache_bsize = 32,
  2057. .num_pmcs = 4,
  2058. .oprofile_cpu_type = "ppc/e500",
  2059. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2060. .cpu_setup = __setup_cpu_e500v1,
  2061. .machine_check = machine_check_e500,
  2062. .platform = "ppc8540",
  2063. },
  2064. { /* e500v2 */
  2065. .pvr_mask = 0xffff0000,
  2066. .pvr_value = 0x80210000,
  2067. .cpu_name = "e500v2",
  2068. .cpu_features = CPU_FTRS_E500_2,
  2069. .cpu_user_features = COMMON_USER_BOOKE |
  2070. PPC_FEATURE_HAS_SPE_COMP |
  2071. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  2072. PPC_FEATURE_HAS_EFP_DOUBLE_COMP,
  2073. .cpu_user_features2 = PPC_FEATURE2_ISEL,
  2074. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS,
  2075. .icache_bsize = 32,
  2076. .dcache_bsize = 32,
  2077. .num_pmcs = 4,
  2078. .oprofile_cpu_type = "ppc/e500",
  2079. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2080. .cpu_setup = __setup_cpu_e500v2,
  2081. .machine_check = machine_check_e500,
  2082. .platform = "ppc8548",
  2083. },
  2084. { /* e500mc */
  2085. .pvr_mask = 0xffff0000,
  2086. .pvr_value = 0x80230000,
  2087. .cpu_name = "e500mc",
  2088. .cpu_features = CPU_FTRS_E500MC,
  2089. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  2090. .cpu_user_features2 = PPC_FEATURE2_ISEL,
  2091. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  2092. MMU_FTR_USE_TLBILX,
  2093. .icache_bsize = 64,
  2094. .dcache_bsize = 64,
  2095. .num_pmcs = 4,
  2096. .oprofile_cpu_type = "ppc/e500mc",
  2097. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2098. .cpu_setup = __setup_cpu_e500mc,
  2099. .machine_check = machine_check_e500mc,
  2100. .platform = "ppce500mc",
  2101. },
  2102. #endif /* CONFIG_PPC32 */
  2103. { /* e5500 */
  2104. .pvr_mask = 0xffff0000,
  2105. .pvr_value = 0x80240000,
  2106. .cpu_name = "e5500",
  2107. .cpu_features = CPU_FTRS_E5500,
  2108. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  2109. .cpu_user_features2 = PPC_FEATURE2_ISEL,
  2110. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  2111. MMU_FTR_USE_TLBILX,
  2112. .icache_bsize = 64,
  2113. .dcache_bsize = 64,
  2114. .num_pmcs = 4,
  2115. .oprofile_cpu_type = "ppc/e500mc",
  2116. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2117. .cpu_setup = __setup_cpu_e5500,
  2118. #ifndef CONFIG_PPC32
  2119. .cpu_restore = __restore_cpu_e5500,
  2120. #endif
  2121. .machine_check = machine_check_e500mc,
  2122. .platform = "ppce5500",
  2123. },
  2124. { /* e6500 */
  2125. .pvr_mask = 0xffff0000,
  2126. .pvr_value = 0x80400000,
  2127. .cpu_name = "e6500",
  2128. .cpu_features = CPU_FTRS_E6500,
  2129. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU |
  2130. PPC_FEATURE_HAS_ALTIVEC_COMP,
  2131. .cpu_user_features2 = PPC_FEATURE2_ISEL,
  2132. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  2133. MMU_FTR_USE_TLBILX,
  2134. .icache_bsize = 64,
  2135. .dcache_bsize = 64,
  2136. .num_pmcs = 6,
  2137. .oprofile_cpu_type = "ppc/e6500",
  2138. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2139. .cpu_setup = __setup_cpu_e6500,
  2140. #ifndef CONFIG_PPC32
  2141. .cpu_restore = __restore_cpu_e6500,
  2142. #endif
  2143. .machine_check = machine_check_e500mc,
  2144. .platform = "ppce6500",
  2145. },
  2146. #ifdef CONFIG_PPC32
  2147. { /* default match */
  2148. .pvr_mask = 0x00000000,
  2149. .pvr_value = 0x00000000,
  2150. .cpu_name = "(generic E500 PPC)",
  2151. .cpu_features = CPU_FTRS_E500,
  2152. .cpu_user_features = COMMON_USER_BOOKE |
  2153. PPC_FEATURE_HAS_SPE_COMP |
  2154. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  2155. .mmu_features = MMU_FTR_TYPE_FSL_E,
  2156. .icache_bsize = 32,
  2157. .dcache_bsize = 32,
  2158. .machine_check = machine_check_e500,
  2159. .platform = "powerpc",
  2160. }
  2161. #endif /* CONFIG_PPC32 */
  2162. #endif /* CONFIG_E500 */
  2163. };
  2164. static struct cpu_spec the_cpu_spec;
  2165. static struct cpu_spec * __init setup_cpu_spec(unsigned long offset,
  2166. struct cpu_spec *s)
  2167. {
  2168. struct cpu_spec *t = &the_cpu_spec;
  2169. struct cpu_spec old;
  2170. t = PTRRELOC(t);
  2171. old = *t;
  2172. /* Copy everything, then do fixups */
  2173. *t = *s;
  2174. /*
  2175. * If we are overriding a previous value derived from the real
  2176. * PVR with a new value obtained using a logical PVR value,
  2177. * don't modify the performance monitor fields.
  2178. */
  2179. if (old.num_pmcs && !s->num_pmcs) {
  2180. t->num_pmcs = old.num_pmcs;
  2181. t->pmc_type = old.pmc_type;
  2182. t->oprofile_type = old.oprofile_type;
  2183. t->oprofile_mmcra_sihv = old.oprofile_mmcra_sihv;
  2184. t->oprofile_mmcra_sipr = old.oprofile_mmcra_sipr;
  2185. t->oprofile_mmcra_clear = old.oprofile_mmcra_clear;
  2186. /*
  2187. * If we have passed through this logic once before and
  2188. * have pulled the default case because the real PVR was
  2189. * not found inside cpu_specs[], then we are possibly
  2190. * running in compatibility mode. In that case, let the
  2191. * oprofiler know which set of compatibility counters to
  2192. * pull from by making sure the oprofile_cpu_type string
  2193. * is set to that of compatibility mode. If the
  2194. * oprofile_cpu_type already has a value, then we are
  2195. * possibly overriding a real PVR with a logical one,
  2196. * and, in that case, keep the current value for
  2197. * oprofile_cpu_type.
  2198. */
  2199. if (old.oprofile_cpu_type != NULL) {
  2200. t->oprofile_cpu_type = old.oprofile_cpu_type;
  2201. t->oprofile_type = old.oprofile_type;
  2202. }
  2203. }
  2204. *PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;
  2205. /*
  2206. * Set the base platform string once; assumes
  2207. * we're called with real pvr first.
  2208. */
  2209. if (*PTRRELOC(&powerpc_base_platform) == NULL)
  2210. *PTRRELOC(&powerpc_base_platform) = t->platform;
  2211. #if defined(CONFIG_PPC64) || defined(CONFIG_BOOKE)
  2212. /* ppc64 and booke expect identify_cpu to also call setup_cpu for
  2213. * that processor. I will consolidate that at a later time, for now,
  2214. * just use #ifdef. We also don't need to PTRRELOC the function
  2215. * pointer on ppc64 and booke as we are running at 0 in real mode
  2216. * on ppc64 and reloc_offset is always 0 on booke.
  2217. */
  2218. if (t->cpu_setup) {
  2219. t->cpu_setup(offset, t);
  2220. }
  2221. #endif /* CONFIG_PPC64 || CONFIG_BOOKE */
  2222. return t;
  2223. }
  2224. struct cpu_spec * __init identify_cpu(unsigned long offset, unsigned int pvr)
  2225. {
  2226. struct cpu_spec *s = cpu_specs;
  2227. int i;
  2228. s = PTRRELOC(s);
  2229. for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++) {
  2230. if ((pvr & s->pvr_mask) == s->pvr_value)
  2231. return setup_cpu_spec(offset, s);
  2232. }
  2233. BUG();
  2234. return NULL;
  2235. }