r4k_fpu.S 6.8 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 1996, 98, 99, 2000, 01 Ralf Baechle
  7. *
  8. * Multi-arch abstraction and asm macros for easier reading:
  9. * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  10. *
  11. * Carsten Langgaard, carstenl@mips.com
  12. * Copyright (C) 2000 MIPS Technologies, Inc.
  13. * Copyright (C) 1999, 2001 Silicon Graphics, Inc.
  14. */
  15. #include <asm/asm.h>
  16. #include <asm/errno.h>
  17. #include <asm/fpregdef.h>
  18. #include <asm/mipsregs.h>
  19. #include <asm/asm-offsets.h>
  20. #include <asm/regdef.h>
  21. .macro EX insn, reg, src
  22. .set push
  23. .set nomacro
  24. .ex\@: \insn \reg, \src
  25. .set pop
  26. .section __ex_table,"a"
  27. PTR .ex\@, fault
  28. .previous
  29. .endm
  30. .set noreorder
  31. .set arch=r4000
  32. LEAF(_save_fp_context)
  33. cfc1 t1, fcr31
  34. #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
  35. .set push
  36. #ifdef CONFIG_CPU_MIPS32_R2
  37. .set mips64r2
  38. mfc0 t0, CP0_STATUS
  39. sll t0, t0, 5
  40. bgez t0, 1f # skip storing odd if FR=0
  41. nop
  42. #endif
  43. /* Store the 16 odd double precision registers */
  44. EX sdc1 $f1, SC_FPREGS+8(a0)
  45. EX sdc1 $f3, SC_FPREGS+24(a0)
  46. EX sdc1 $f5, SC_FPREGS+40(a0)
  47. EX sdc1 $f7, SC_FPREGS+56(a0)
  48. EX sdc1 $f9, SC_FPREGS+72(a0)
  49. EX sdc1 $f11, SC_FPREGS+88(a0)
  50. EX sdc1 $f13, SC_FPREGS+104(a0)
  51. EX sdc1 $f15, SC_FPREGS+120(a0)
  52. EX sdc1 $f17, SC_FPREGS+136(a0)
  53. EX sdc1 $f19, SC_FPREGS+152(a0)
  54. EX sdc1 $f21, SC_FPREGS+168(a0)
  55. EX sdc1 $f23, SC_FPREGS+184(a0)
  56. EX sdc1 $f25, SC_FPREGS+200(a0)
  57. EX sdc1 $f27, SC_FPREGS+216(a0)
  58. EX sdc1 $f29, SC_FPREGS+232(a0)
  59. EX sdc1 $f31, SC_FPREGS+248(a0)
  60. 1: .set pop
  61. #endif
  62. /* Store the 16 even double precision registers */
  63. EX sdc1 $f0, SC_FPREGS+0(a0)
  64. EX sdc1 $f2, SC_FPREGS+16(a0)
  65. EX sdc1 $f4, SC_FPREGS+32(a0)
  66. EX sdc1 $f6, SC_FPREGS+48(a0)
  67. EX sdc1 $f8, SC_FPREGS+64(a0)
  68. EX sdc1 $f10, SC_FPREGS+80(a0)
  69. EX sdc1 $f12, SC_FPREGS+96(a0)
  70. EX sdc1 $f14, SC_FPREGS+112(a0)
  71. EX sdc1 $f16, SC_FPREGS+128(a0)
  72. EX sdc1 $f18, SC_FPREGS+144(a0)
  73. EX sdc1 $f20, SC_FPREGS+160(a0)
  74. EX sdc1 $f22, SC_FPREGS+176(a0)
  75. EX sdc1 $f24, SC_FPREGS+192(a0)
  76. EX sdc1 $f26, SC_FPREGS+208(a0)
  77. EX sdc1 $f28, SC_FPREGS+224(a0)
  78. EX sdc1 $f30, SC_FPREGS+240(a0)
  79. EX sw t1, SC_FPC_CSR(a0)
  80. jr ra
  81. li v0, 0 # success
  82. END(_save_fp_context)
  83. #ifdef CONFIG_MIPS32_COMPAT
  84. /* Save 32-bit process floating point context */
  85. LEAF(_save_fp_context32)
  86. cfc1 t1, fcr31
  87. mfc0 t0, CP0_STATUS
  88. sll t0, t0, 5
  89. bgez t0, 1f # skip storing odd if FR=0
  90. nop
  91. /* Store the 16 odd double precision registers */
  92. EX sdc1 $f1, SC32_FPREGS+8(a0)
  93. EX sdc1 $f3, SC32_FPREGS+24(a0)
  94. EX sdc1 $f5, SC32_FPREGS+40(a0)
  95. EX sdc1 $f7, SC32_FPREGS+56(a0)
  96. EX sdc1 $f9, SC32_FPREGS+72(a0)
  97. EX sdc1 $f11, SC32_FPREGS+88(a0)
  98. EX sdc1 $f13, SC32_FPREGS+104(a0)
  99. EX sdc1 $f15, SC32_FPREGS+120(a0)
  100. EX sdc1 $f17, SC32_FPREGS+136(a0)
  101. EX sdc1 $f19, SC32_FPREGS+152(a0)
  102. EX sdc1 $f21, SC32_FPREGS+168(a0)
  103. EX sdc1 $f23, SC32_FPREGS+184(a0)
  104. EX sdc1 $f25, SC32_FPREGS+200(a0)
  105. EX sdc1 $f27, SC32_FPREGS+216(a0)
  106. EX sdc1 $f29, SC32_FPREGS+232(a0)
  107. EX sdc1 $f31, SC32_FPREGS+248(a0)
  108. /* Store the 16 even double precision registers */
  109. 1: EX sdc1 $f0, SC32_FPREGS+0(a0)
  110. EX sdc1 $f2, SC32_FPREGS+16(a0)
  111. EX sdc1 $f4, SC32_FPREGS+32(a0)
  112. EX sdc1 $f6, SC32_FPREGS+48(a0)
  113. EX sdc1 $f8, SC32_FPREGS+64(a0)
  114. EX sdc1 $f10, SC32_FPREGS+80(a0)
  115. EX sdc1 $f12, SC32_FPREGS+96(a0)
  116. EX sdc1 $f14, SC32_FPREGS+112(a0)
  117. EX sdc1 $f16, SC32_FPREGS+128(a0)
  118. EX sdc1 $f18, SC32_FPREGS+144(a0)
  119. EX sdc1 $f20, SC32_FPREGS+160(a0)
  120. EX sdc1 $f22, SC32_FPREGS+176(a0)
  121. EX sdc1 $f24, SC32_FPREGS+192(a0)
  122. EX sdc1 $f26, SC32_FPREGS+208(a0)
  123. EX sdc1 $f28, SC32_FPREGS+224(a0)
  124. EX sdc1 $f30, SC32_FPREGS+240(a0)
  125. EX sw t1, SC32_FPC_CSR(a0)
  126. cfc1 t0, $0 # implementation/version
  127. EX sw t0, SC32_FPC_EIR(a0)
  128. jr ra
  129. li v0, 0 # success
  130. END(_save_fp_context32)
  131. #endif
  132. /*
  133. * Restore FPU state:
  134. * - fp gp registers
  135. * - cp1 status/control register
  136. */
  137. LEAF(_restore_fp_context)
  138. EX lw t1, SC_FPC_CSR(a0)
  139. #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
  140. .set push
  141. #ifdef CONFIG_CPU_MIPS32_R2
  142. .set mips64r2
  143. mfc0 t0, CP0_STATUS
  144. sll t0, t0, 5
  145. bgez t0, 1f # skip loading odd if FR=0
  146. nop
  147. #endif
  148. EX ldc1 $f1, SC_FPREGS+8(a0)
  149. EX ldc1 $f3, SC_FPREGS+24(a0)
  150. EX ldc1 $f5, SC_FPREGS+40(a0)
  151. EX ldc1 $f7, SC_FPREGS+56(a0)
  152. EX ldc1 $f9, SC_FPREGS+72(a0)
  153. EX ldc1 $f11, SC_FPREGS+88(a0)
  154. EX ldc1 $f13, SC_FPREGS+104(a0)
  155. EX ldc1 $f15, SC_FPREGS+120(a0)
  156. EX ldc1 $f17, SC_FPREGS+136(a0)
  157. EX ldc1 $f19, SC_FPREGS+152(a0)
  158. EX ldc1 $f21, SC_FPREGS+168(a0)
  159. EX ldc1 $f23, SC_FPREGS+184(a0)
  160. EX ldc1 $f25, SC_FPREGS+200(a0)
  161. EX ldc1 $f27, SC_FPREGS+216(a0)
  162. EX ldc1 $f29, SC_FPREGS+232(a0)
  163. EX ldc1 $f31, SC_FPREGS+248(a0)
  164. 1: .set pop
  165. #endif
  166. EX ldc1 $f0, SC_FPREGS+0(a0)
  167. EX ldc1 $f2, SC_FPREGS+16(a0)
  168. EX ldc1 $f4, SC_FPREGS+32(a0)
  169. EX ldc1 $f6, SC_FPREGS+48(a0)
  170. EX ldc1 $f8, SC_FPREGS+64(a0)
  171. EX ldc1 $f10, SC_FPREGS+80(a0)
  172. EX ldc1 $f12, SC_FPREGS+96(a0)
  173. EX ldc1 $f14, SC_FPREGS+112(a0)
  174. EX ldc1 $f16, SC_FPREGS+128(a0)
  175. EX ldc1 $f18, SC_FPREGS+144(a0)
  176. EX ldc1 $f20, SC_FPREGS+160(a0)
  177. EX ldc1 $f22, SC_FPREGS+176(a0)
  178. EX ldc1 $f24, SC_FPREGS+192(a0)
  179. EX ldc1 $f26, SC_FPREGS+208(a0)
  180. EX ldc1 $f28, SC_FPREGS+224(a0)
  181. EX ldc1 $f30, SC_FPREGS+240(a0)
  182. ctc1 t1, fcr31
  183. jr ra
  184. li v0, 0 # success
  185. END(_restore_fp_context)
  186. #ifdef CONFIG_MIPS32_COMPAT
  187. LEAF(_restore_fp_context32)
  188. /* Restore an o32 sigcontext. */
  189. EX lw t1, SC32_FPC_CSR(a0)
  190. mfc0 t0, CP0_STATUS
  191. sll t0, t0, 5
  192. bgez t0, 1f # skip loading odd if FR=0
  193. nop
  194. EX ldc1 $f1, SC32_FPREGS+8(a0)
  195. EX ldc1 $f3, SC32_FPREGS+24(a0)
  196. EX ldc1 $f5, SC32_FPREGS+40(a0)
  197. EX ldc1 $f7, SC32_FPREGS+56(a0)
  198. EX ldc1 $f9, SC32_FPREGS+72(a0)
  199. EX ldc1 $f11, SC32_FPREGS+88(a0)
  200. EX ldc1 $f13, SC32_FPREGS+104(a0)
  201. EX ldc1 $f15, SC32_FPREGS+120(a0)
  202. EX ldc1 $f17, SC32_FPREGS+136(a0)
  203. EX ldc1 $f19, SC32_FPREGS+152(a0)
  204. EX ldc1 $f21, SC32_FPREGS+168(a0)
  205. EX ldc1 $f23, SC32_FPREGS+184(a0)
  206. EX ldc1 $f25, SC32_FPREGS+200(a0)
  207. EX ldc1 $f27, SC32_FPREGS+216(a0)
  208. EX ldc1 $f29, SC32_FPREGS+232(a0)
  209. EX ldc1 $f31, SC32_FPREGS+248(a0)
  210. 1: EX ldc1 $f0, SC32_FPREGS+0(a0)
  211. EX ldc1 $f2, SC32_FPREGS+16(a0)
  212. EX ldc1 $f4, SC32_FPREGS+32(a0)
  213. EX ldc1 $f6, SC32_FPREGS+48(a0)
  214. EX ldc1 $f8, SC32_FPREGS+64(a0)
  215. EX ldc1 $f10, SC32_FPREGS+80(a0)
  216. EX ldc1 $f12, SC32_FPREGS+96(a0)
  217. EX ldc1 $f14, SC32_FPREGS+112(a0)
  218. EX ldc1 $f16, SC32_FPREGS+128(a0)
  219. EX ldc1 $f18, SC32_FPREGS+144(a0)
  220. EX ldc1 $f20, SC32_FPREGS+160(a0)
  221. EX ldc1 $f22, SC32_FPREGS+176(a0)
  222. EX ldc1 $f24, SC32_FPREGS+192(a0)
  223. EX ldc1 $f26, SC32_FPREGS+208(a0)
  224. EX ldc1 $f28, SC32_FPREGS+224(a0)
  225. EX ldc1 $f30, SC32_FPREGS+240(a0)
  226. ctc1 t1, fcr31
  227. jr ra
  228. li v0, 0 # success
  229. END(_restore_fp_context32)
  230. #endif
  231. .set reorder
  232. .type fault@function
  233. .ent fault
  234. fault: li v0, -EFAULT # failure
  235. jr ra
  236. .end fault