cputable.c 35 KB

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  1. /*
  2. * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  3. *
  4. * Modifications for ppc64:
  5. * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/string.h>
  13. #include <linux/sched.h>
  14. #include <linux/threads.h>
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <asm/oprofile_impl.h>
  18. #include <asm/cputable.h>
  19. #include <asm/prom.h> /* for PTRRELOC on ARCH=ppc */
  20. struct cpu_spec* cur_cpu_spec = NULL;
  21. EXPORT_SYMBOL(cur_cpu_spec);
  22. /* NOTE:
  23. * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  24. * the responsibility of the appropriate CPU save/restore functions to
  25. * eventually copy these settings over. Those save/restore aren't yet
  26. * part of the cputable though. That has to be fixed for both ppc32
  27. * and ppc64
  28. */
  29. #ifdef CONFIG_PPC32
  30. extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
  31. extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
  32. extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
  33. extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
  34. extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
  35. extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
  36. extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
  37. extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
  38. #endif /* CONFIG_PPC32 */
  39. #ifdef CONFIG_PPC64
  40. extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  41. extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec);
  42. extern void __restore_cpu_ppc970(void);
  43. #endif /* CONFIG_PPC64 */
  44. /* This table only contains "desktop" CPUs, it need to be filled with embedded
  45. * ones as well...
  46. */
  47. #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  48. PPC_FEATURE_HAS_MMU)
  49. #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
  50. #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
  51. #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\
  52. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  53. #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\
  54. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  55. #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\
  56. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  57. PPC_FEATURE_TRUE_LE)
  58. #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
  59. PPC_FEATURE_TRUE_LE | \
  60. PPC_FEATURE_HAS_ALTIVEC_COMP)
  61. #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
  62. PPC_FEATURE_BOOKE)
  63. /* We only set the spe features if the kernel was compiled with
  64. * spe support
  65. */
  66. #ifdef CONFIG_SPE
  67. #define PPC_FEATURE_SPE_COMP PPC_FEATURE_HAS_SPE
  68. #else
  69. #define PPC_FEATURE_SPE_COMP 0
  70. #endif
  71. static struct cpu_spec cpu_specs[] = {
  72. #ifdef CONFIG_PPC64
  73. { /* Power3 */
  74. .pvr_mask = 0xffff0000,
  75. .pvr_value = 0x00400000,
  76. .cpu_name = "POWER3 (630)",
  77. .cpu_features = CPU_FTRS_POWER3,
  78. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  79. .icache_bsize = 128,
  80. .dcache_bsize = 128,
  81. .num_pmcs = 8,
  82. .oprofile_cpu_type = "ppc64/power3",
  83. .oprofile_type = PPC_OPROFILE_RS64,
  84. .platform = "power3",
  85. },
  86. { /* Power3+ */
  87. .pvr_mask = 0xffff0000,
  88. .pvr_value = 0x00410000,
  89. .cpu_name = "POWER3 (630+)",
  90. .cpu_features = CPU_FTRS_POWER3,
  91. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  92. .icache_bsize = 128,
  93. .dcache_bsize = 128,
  94. .num_pmcs = 8,
  95. .oprofile_cpu_type = "ppc64/power3",
  96. .oprofile_type = PPC_OPROFILE_RS64,
  97. .platform = "power3",
  98. },
  99. { /* Northstar */
  100. .pvr_mask = 0xffff0000,
  101. .pvr_value = 0x00330000,
  102. .cpu_name = "RS64-II (northstar)",
  103. .cpu_features = CPU_FTRS_RS64,
  104. .cpu_user_features = COMMON_USER_PPC64,
  105. .icache_bsize = 128,
  106. .dcache_bsize = 128,
  107. .num_pmcs = 8,
  108. .oprofile_cpu_type = "ppc64/rs64",
  109. .oprofile_type = PPC_OPROFILE_RS64,
  110. .platform = "rs64",
  111. },
  112. { /* Pulsar */
  113. .pvr_mask = 0xffff0000,
  114. .pvr_value = 0x00340000,
  115. .cpu_name = "RS64-III (pulsar)",
  116. .cpu_features = CPU_FTRS_RS64,
  117. .cpu_user_features = COMMON_USER_PPC64,
  118. .icache_bsize = 128,
  119. .dcache_bsize = 128,
  120. .num_pmcs = 8,
  121. .oprofile_cpu_type = "ppc64/rs64",
  122. .oprofile_type = PPC_OPROFILE_RS64,
  123. .platform = "rs64",
  124. },
  125. { /* I-star */
  126. .pvr_mask = 0xffff0000,
  127. .pvr_value = 0x00360000,
  128. .cpu_name = "RS64-III (icestar)",
  129. .cpu_features = CPU_FTRS_RS64,
  130. .cpu_user_features = COMMON_USER_PPC64,
  131. .icache_bsize = 128,
  132. .dcache_bsize = 128,
  133. .num_pmcs = 8,
  134. .oprofile_cpu_type = "ppc64/rs64",
  135. .oprofile_type = PPC_OPROFILE_RS64,
  136. .platform = "rs64",
  137. },
  138. { /* S-star */
  139. .pvr_mask = 0xffff0000,
  140. .pvr_value = 0x00370000,
  141. .cpu_name = "RS64-IV (sstar)",
  142. .cpu_features = CPU_FTRS_RS64,
  143. .cpu_user_features = COMMON_USER_PPC64,
  144. .icache_bsize = 128,
  145. .dcache_bsize = 128,
  146. .num_pmcs = 8,
  147. .oprofile_cpu_type = "ppc64/rs64",
  148. .oprofile_type = PPC_OPROFILE_RS64,
  149. .platform = "rs64",
  150. },
  151. { /* Power4 */
  152. .pvr_mask = 0xffff0000,
  153. .pvr_value = 0x00350000,
  154. .cpu_name = "POWER4 (gp)",
  155. .cpu_features = CPU_FTRS_POWER4,
  156. .cpu_user_features = COMMON_USER_POWER4,
  157. .icache_bsize = 128,
  158. .dcache_bsize = 128,
  159. .num_pmcs = 8,
  160. .oprofile_cpu_type = "ppc64/power4",
  161. .oprofile_type = PPC_OPROFILE_POWER4,
  162. .platform = "power4",
  163. },
  164. { /* Power4+ */
  165. .pvr_mask = 0xffff0000,
  166. .pvr_value = 0x00380000,
  167. .cpu_name = "POWER4+ (gq)",
  168. .cpu_features = CPU_FTRS_POWER4,
  169. .cpu_user_features = COMMON_USER_POWER4,
  170. .icache_bsize = 128,
  171. .dcache_bsize = 128,
  172. .num_pmcs = 8,
  173. .oprofile_cpu_type = "ppc64/power4",
  174. .oprofile_type = PPC_OPROFILE_POWER4,
  175. .platform = "power4",
  176. },
  177. { /* PPC970 */
  178. .pvr_mask = 0xffff0000,
  179. .pvr_value = 0x00390000,
  180. .cpu_name = "PPC970",
  181. .cpu_features = CPU_FTRS_PPC970,
  182. .cpu_user_features = COMMON_USER_POWER4 |
  183. PPC_FEATURE_HAS_ALTIVEC_COMP,
  184. .icache_bsize = 128,
  185. .dcache_bsize = 128,
  186. .num_pmcs = 8,
  187. .cpu_setup = __setup_cpu_ppc970,
  188. .cpu_restore = __restore_cpu_ppc970,
  189. .oprofile_cpu_type = "ppc64/970",
  190. .oprofile_type = PPC_OPROFILE_POWER4,
  191. .platform = "ppc970",
  192. },
  193. { /* PPC970FX */
  194. .pvr_mask = 0xffff0000,
  195. .pvr_value = 0x003c0000,
  196. .cpu_name = "PPC970FX",
  197. .cpu_features = CPU_FTRS_PPC970,
  198. .cpu_user_features = COMMON_USER_POWER4 |
  199. PPC_FEATURE_HAS_ALTIVEC_COMP,
  200. .icache_bsize = 128,
  201. .dcache_bsize = 128,
  202. .num_pmcs = 8,
  203. .cpu_setup = __setup_cpu_ppc970,
  204. .cpu_restore = __restore_cpu_ppc970,
  205. .oprofile_cpu_type = "ppc64/970",
  206. .oprofile_type = PPC_OPROFILE_POWER4,
  207. .platform = "ppc970",
  208. },
  209. { /* PPC970MP */
  210. .pvr_mask = 0xffff0000,
  211. .pvr_value = 0x00440000,
  212. .cpu_name = "PPC970MP",
  213. .cpu_features = CPU_FTRS_PPC970,
  214. .cpu_user_features = COMMON_USER_POWER4 |
  215. PPC_FEATURE_HAS_ALTIVEC_COMP,
  216. .icache_bsize = 128,
  217. .dcache_bsize = 128,
  218. .num_pmcs = 8,
  219. .cpu_setup = __setup_cpu_ppc970MP,
  220. .cpu_restore = __restore_cpu_ppc970,
  221. .oprofile_cpu_type = "ppc64/970",
  222. .oprofile_type = PPC_OPROFILE_POWER4,
  223. .platform = "ppc970",
  224. },
  225. { /* PPC970GX */
  226. .pvr_mask = 0xffff0000,
  227. .pvr_value = 0x00450000,
  228. .cpu_name = "PPC970GX",
  229. .cpu_features = CPU_FTRS_PPC970,
  230. .cpu_user_features = COMMON_USER_POWER4 |
  231. PPC_FEATURE_HAS_ALTIVEC_COMP,
  232. .icache_bsize = 128,
  233. .dcache_bsize = 128,
  234. .num_pmcs = 8,
  235. .cpu_setup = __setup_cpu_ppc970,
  236. .oprofile_cpu_type = "ppc64/970",
  237. .oprofile_type = PPC_OPROFILE_POWER4,
  238. .platform = "ppc970",
  239. },
  240. { /* Power5 GR */
  241. .pvr_mask = 0xffff0000,
  242. .pvr_value = 0x003a0000,
  243. .cpu_name = "POWER5 (gr)",
  244. .cpu_features = CPU_FTRS_POWER5,
  245. .cpu_user_features = COMMON_USER_POWER5,
  246. .icache_bsize = 128,
  247. .dcache_bsize = 128,
  248. .num_pmcs = 6,
  249. .oprofile_cpu_type = "ppc64/power5",
  250. .oprofile_type = PPC_OPROFILE_POWER4,
  251. /* SIHV / SIPR bits are implemented on POWER4+ (GQ)
  252. * and above but only works on POWER5 and above
  253. */
  254. .oprofile_mmcra_sihv = MMCRA_SIHV,
  255. .oprofile_mmcra_sipr = MMCRA_SIPR,
  256. .platform = "power5",
  257. },
  258. { /* Power5 GS */
  259. .pvr_mask = 0xffff0000,
  260. .pvr_value = 0x003b0000,
  261. .cpu_name = "POWER5+ (gs)",
  262. .cpu_features = CPU_FTRS_POWER5,
  263. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  264. .icache_bsize = 128,
  265. .dcache_bsize = 128,
  266. .num_pmcs = 6,
  267. .oprofile_cpu_type = "ppc64/power5+",
  268. .oprofile_type = PPC_OPROFILE_POWER4,
  269. .oprofile_mmcra_sihv = MMCRA_SIHV,
  270. .oprofile_mmcra_sipr = MMCRA_SIPR,
  271. .platform = "power5+",
  272. },
  273. { /* POWER6 in P5+ mode; 2.04-compliant processor */
  274. .pvr_mask = 0xffffffff,
  275. .pvr_value = 0x0f000001,
  276. .cpu_name = "POWER5+",
  277. .cpu_features = CPU_FTRS_POWER5,
  278. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  279. .icache_bsize = 128,
  280. .dcache_bsize = 128,
  281. .num_pmcs = 6,
  282. .oprofile_cpu_type = "ppc64/power6",
  283. .oprofile_type = PPC_OPROFILE_POWER4,
  284. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  285. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  286. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  287. POWER6_MMCRA_OTHER,
  288. .platform = "power5+",
  289. },
  290. { /* Power6 */
  291. .pvr_mask = 0xffff0000,
  292. .pvr_value = 0x003e0000,
  293. .cpu_name = "POWER6 (raw)",
  294. .cpu_features = CPU_FTRS_POWER6,
  295. .cpu_user_features = COMMON_USER_POWER6 |
  296. PPC_FEATURE_POWER6_EXT,
  297. .icache_bsize = 128,
  298. .dcache_bsize = 128,
  299. .num_pmcs = 6,
  300. .oprofile_cpu_type = "ppc64/power6",
  301. .oprofile_type = PPC_OPROFILE_POWER4,
  302. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  303. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  304. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  305. POWER6_MMCRA_OTHER,
  306. .platform = "power6x",
  307. },
  308. { /* 2.05-compliant processor, i.e. Power6 "architected" mode */
  309. .pvr_mask = 0xffffffff,
  310. .pvr_value = 0x0f000002,
  311. .cpu_name = "POWER6 (architected)",
  312. .cpu_features = CPU_FTRS_POWER6,
  313. .cpu_user_features = COMMON_USER_POWER6,
  314. .icache_bsize = 128,
  315. .dcache_bsize = 128,
  316. .num_pmcs = 6,
  317. .oprofile_cpu_type = "ppc64/power6",
  318. .oprofile_type = PPC_OPROFILE_POWER4,
  319. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  320. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  321. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  322. POWER6_MMCRA_OTHER,
  323. .platform = "power6",
  324. },
  325. { /* Cell Broadband Engine */
  326. .pvr_mask = 0xffff0000,
  327. .pvr_value = 0x00700000,
  328. .cpu_name = "Cell Broadband Engine",
  329. .cpu_features = CPU_FTRS_CELL,
  330. .cpu_user_features = COMMON_USER_PPC64 |
  331. PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
  332. PPC_FEATURE_SMT,
  333. .icache_bsize = 128,
  334. .dcache_bsize = 128,
  335. .num_pmcs = 4,
  336. .oprofile_cpu_type = "ppc64/cell-be",
  337. .oprofile_type = PPC_OPROFILE_CELL,
  338. .platform = "ppc-cell-be",
  339. },
  340. { /* PA Semi PA6T */
  341. .pvr_mask = 0x7fff0000,
  342. .pvr_value = 0x00900000,
  343. .cpu_name = "PA6T",
  344. .cpu_features = CPU_FTRS_PA6T,
  345. .cpu_user_features = COMMON_USER_PA6T,
  346. .icache_bsize = 64,
  347. .dcache_bsize = 64,
  348. .num_pmcs = 6,
  349. .platform = "pa6t",
  350. },
  351. { /* default match */
  352. .pvr_mask = 0x00000000,
  353. .pvr_value = 0x00000000,
  354. .cpu_name = "POWER4 (compatible)",
  355. .cpu_features = CPU_FTRS_COMPATIBLE,
  356. .cpu_user_features = COMMON_USER_PPC64,
  357. .icache_bsize = 128,
  358. .dcache_bsize = 128,
  359. .num_pmcs = 6,
  360. .platform = "power4",
  361. }
  362. #endif /* CONFIG_PPC64 */
  363. #ifdef CONFIG_PPC32
  364. #if CLASSIC_PPC
  365. { /* 601 */
  366. .pvr_mask = 0xffff0000,
  367. .pvr_value = 0x00010000,
  368. .cpu_name = "601",
  369. .cpu_features = CPU_FTRS_PPC601,
  370. .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
  371. PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
  372. .icache_bsize = 32,
  373. .dcache_bsize = 32,
  374. .platform = "ppc601",
  375. },
  376. { /* 603 */
  377. .pvr_mask = 0xffff0000,
  378. .pvr_value = 0x00030000,
  379. .cpu_name = "603",
  380. .cpu_features = CPU_FTRS_603,
  381. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  382. .icache_bsize = 32,
  383. .dcache_bsize = 32,
  384. .cpu_setup = __setup_cpu_603,
  385. .platform = "ppc603",
  386. },
  387. { /* 603e */
  388. .pvr_mask = 0xffff0000,
  389. .pvr_value = 0x00060000,
  390. .cpu_name = "603e",
  391. .cpu_features = CPU_FTRS_603,
  392. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  393. .icache_bsize = 32,
  394. .dcache_bsize = 32,
  395. .cpu_setup = __setup_cpu_603,
  396. .platform = "ppc603",
  397. },
  398. { /* 603ev */
  399. .pvr_mask = 0xffff0000,
  400. .pvr_value = 0x00070000,
  401. .cpu_name = "603ev",
  402. .cpu_features = CPU_FTRS_603,
  403. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  404. .icache_bsize = 32,
  405. .dcache_bsize = 32,
  406. .cpu_setup = __setup_cpu_603,
  407. .platform = "ppc603",
  408. },
  409. { /* 604 */
  410. .pvr_mask = 0xffff0000,
  411. .pvr_value = 0x00040000,
  412. .cpu_name = "604",
  413. .cpu_features = CPU_FTRS_604,
  414. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  415. .icache_bsize = 32,
  416. .dcache_bsize = 32,
  417. .num_pmcs = 2,
  418. .cpu_setup = __setup_cpu_604,
  419. .platform = "ppc604",
  420. },
  421. { /* 604e */
  422. .pvr_mask = 0xfffff000,
  423. .pvr_value = 0x00090000,
  424. .cpu_name = "604e",
  425. .cpu_features = CPU_FTRS_604,
  426. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  427. .icache_bsize = 32,
  428. .dcache_bsize = 32,
  429. .num_pmcs = 4,
  430. .cpu_setup = __setup_cpu_604,
  431. .platform = "ppc604",
  432. },
  433. { /* 604r */
  434. .pvr_mask = 0xffff0000,
  435. .pvr_value = 0x00090000,
  436. .cpu_name = "604r",
  437. .cpu_features = CPU_FTRS_604,
  438. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  439. .icache_bsize = 32,
  440. .dcache_bsize = 32,
  441. .num_pmcs = 4,
  442. .cpu_setup = __setup_cpu_604,
  443. .platform = "ppc604",
  444. },
  445. { /* 604ev */
  446. .pvr_mask = 0xffff0000,
  447. .pvr_value = 0x000a0000,
  448. .cpu_name = "604ev",
  449. .cpu_features = CPU_FTRS_604,
  450. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  451. .icache_bsize = 32,
  452. .dcache_bsize = 32,
  453. .num_pmcs = 4,
  454. .cpu_setup = __setup_cpu_604,
  455. .platform = "ppc604",
  456. },
  457. { /* 740/750 (0x4202, don't support TAU ?) */
  458. .pvr_mask = 0xffffffff,
  459. .pvr_value = 0x00084202,
  460. .cpu_name = "740/750",
  461. .cpu_features = CPU_FTRS_740_NOTAU,
  462. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  463. .icache_bsize = 32,
  464. .dcache_bsize = 32,
  465. .num_pmcs = 4,
  466. .cpu_setup = __setup_cpu_750,
  467. .platform = "ppc750",
  468. },
  469. { /* 750CX (80100 and 8010x?) */
  470. .pvr_mask = 0xfffffff0,
  471. .pvr_value = 0x00080100,
  472. .cpu_name = "750CX",
  473. .cpu_features = CPU_FTRS_750,
  474. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  475. .icache_bsize = 32,
  476. .dcache_bsize = 32,
  477. .num_pmcs = 4,
  478. .cpu_setup = __setup_cpu_750cx,
  479. .platform = "ppc750",
  480. },
  481. { /* 750CX (82201 and 82202) */
  482. .pvr_mask = 0xfffffff0,
  483. .pvr_value = 0x00082200,
  484. .cpu_name = "750CX",
  485. .cpu_features = CPU_FTRS_750,
  486. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  487. .icache_bsize = 32,
  488. .dcache_bsize = 32,
  489. .num_pmcs = 4,
  490. .cpu_setup = __setup_cpu_750cx,
  491. .platform = "ppc750",
  492. },
  493. { /* 750CXe (82214) */
  494. .pvr_mask = 0xfffffff0,
  495. .pvr_value = 0x00082210,
  496. .cpu_name = "750CXe",
  497. .cpu_features = CPU_FTRS_750,
  498. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  499. .icache_bsize = 32,
  500. .dcache_bsize = 32,
  501. .num_pmcs = 4,
  502. .cpu_setup = __setup_cpu_750cx,
  503. .platform = "ppc750",
  504. },
  505. { /* 750CXe "Gekko" (83214) */
  506. .pvr_mask = 0xffffffff,
  507. .pvr_value = 0x00083214,
  508. .cpu_name = "750CXe",
  509. .cpu_features = CPU_FTRS_750,
  510. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  511. .icache_bsize = 32,
  512. .dcache_bsize = 32,
  513. .num_pmcs = 4,
  514. .cpu_setup = __setup_cpu_750cx,
  515. .platform = "ppc750",
  516. },
  517. { /* 745/755 */
  518. .pvr_mask = 0xfffff000,
  519. .pvr_value = 0x00083000,
  520. .cpu_name = "745/755",
  521. .cpu_features = CPU_FTRS_750,
  522. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  523. .icache_bsize = 32,
  524. .dcache_bsize = 32,
  525. .num_pmcs = 4,
  526. .cpu_setup = __setup_cpu_750,
  527. .platform = "ppc750",
  528. },
  529. { /* 750FX rev 1.x */
  530. .pvr_mask = 0xffffff00,
  531. .pvr_value = 0x70000100,
  532. .cpu_name = "750FX",
  533. .cpu_features = CPU_FTRS_750FX1,
  534. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  535. .icache_bsize = 32,
  536. .dcache_bsize = 32,
  537. .num_pmcs = 4,
  538. .cpu_setup = __setup_cpu_750,
  539. .platform = "ppc750",
  540. },
  541. { /* 750FX rev 2.0 must disable HID0[DPM] */
  542. .pvr_mask = 0xffffffff,
  543. .pvr_value = 0x70000200,
  544. .cpu_name = "750FX",
  545. .cpu_features = CPU_FTRS_750FX2,
  546. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  547. .icache_bsize = 32,
  548. .dcache_bsize = 32,
  549. .num_pmcs = 4,
  550. .cpu_setup = __setup_cpu_750,
  551. .platform = "ppc750",
  552. },
  553. { /* 750FX (All revs except 2.0) */
  554. .pvr_mask = 0xffff0000,
  555. .pvr_value = 0x70000000,
  556. .cpu_name = "750FX",
  557. .cpu_features = CPU_FTRS_750FX,
  558. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  559. .icache_bsize = 32,
  560. .dcache_bsize = 32,
  561. .num_pmcs = 4,
  562. .cpu_setup = __setup_cpu_750fx,
  563. .platform = "ppc750",
  564. },
  565. { /* 750GX */
  566. .pvr_mask = 0xffff0000,
  567. .pvr_value = 0x70020000,
  568. .cpu_name = "750GX",
  569. .cpu_features = CPU_FTRS_750GX,
  570. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  571. .icache_bsize = 32,
  572. .dcache_bsize = 32,
  573. .num_pmcs = 4,
  574. .cpu_setup = __setup_cpu_750fx,
  575. .platform = "ppc750",
  576. },
  577. { /* 740/750 (L2CR bit need fixup for 740) */
  578. .pvr_mask = 0xffff0000,
  579. .pvr_value = 0x00080000,
  580. .cpu_name = "740/750",
  581. .cpu_features = CPU_FTRS_740,
  582. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  583. .icache_bsize = 32,
  584. .dcache_bsize = 32,
  585. .num_pmcs = 4,
  586. .cpu_setup = __setup_cpu_750,
  587. .platform = "ppc750",
  588. },
  589. { /* 7400 rev 1.1 ? (no TAU) */
  590. .pvr_mask = 0xffffffff,
  591. .pvr_value = 0x000c1101,
  592. .cpu_name = "7400 (1.1)",
  593. .cpu_features = CPU_FTRS_7400_NOTAU,
  594. .cpu_user_features = COMMON_USER |
  595. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  596. .icache_bsize = 32,
  597. .dcache_bsize = 32,
  598. .num_pmcs = 4,
  599. .cpu_setup = __setup_cpu_7400,
  600. .platform = "ppc7400",
  601. },
  602. { /* 7400 */
  603. .pvr_mask = 0xffff0000,
  604. .pvr_value = 0x000c0000,
  605. .cpu_name = "7400",
  606. .cpu_features = CPU_FTRS_7400,
  607. .cpu_user_features = COMMON_USER |
  608. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  609. .icache_bsize = 32,
  610. .dcache_bsize = 32,
  611. .num_pmcs = 4,
  612. .cpu_setup = __setup_cpu_7400,
  613. .platform = "ppc7400",
  614. },
  615. { /* 7410 */
  616. .pvr_mask = 0xffff0000,
  617. .pvr_value = 0x800c0000,
  618. .cpu_name = "7410",
  619. .cpu_features = CPU_FTRS_7400,
  620. .cpu_user_features = COMMON_USER |
  621. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  622. .icache_bsize = 32,
  623. .dcache_bsize = 32,
  624. .num_pmcs = 4,
  625. .cpu_setup = __setup_cpu_7410,
  626. .platform = "ppc7400",
  627. },
  628. { /* 7450 2.0 - no doze/nap */
  629. .pvr_mask = 0xffffffff,
  630. .pvr_value = 0x80000200,
  631. .cpu_name = "7450",
  632. .cpu_features = CPU_FTRS_7450_20,
  633. .cpu_user_features = COMMON_USER |
  634. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  635. .icache_bsize = 32,
  636. .dcache_bsize = 32,
  637. .num_pmcs = 6,
  638. .cpu_setup = __setup_cpu_745x,
  639. .oprofile_cpu_type = "ppc/7450",
  640. .oprofile_type = PPC_OPROFILE_G4,
  641. .platform = "ppc7450",
  642. },
  643. { /* 7450 2.1 */
  644. .pvr_mask = 0xffffffff,
  645. .pvr_value = 0x80000201,
  646. .cpu_name = "7450",
  647. .cpu_features = CPU_FTRS_7450_21,
  648. .cpu_user_features = COMMON_USER |
  649. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  650. .icache_bsize = 32,
  651. .dcache_bsize = 32,
  652. .num_pmcs = 6,
  653. .cpu_setup = __setup_cpu_745x,
  654. .oprofile_cpu_type = "ppc/7450",
  655. .oprofile_type = PPC_OPROFILE_G4,
  656. .platform = "ppc7450",
  657. },
  658. { /* 7450 2.3 and newer */
  659. .pvr_mask = 0xffff0000,
  660. .pvr_value = 0x80000000,
  661. .cpu_name = "7450",
  662. .cpu_features = CPU_FTRS_7450_23,
  663. .cpu_user_features = COMMON_USER |
  664. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  665. .icache_bsize = 32,
  666. .dcache_bsize = 32,
  667. .num_pmcs = 6,
  668. .cpu_setup = __setup_cpu_745x,
  669. .oprofile_cpu_type = "ppc/7450",
  670. .oprofile_type = PPC_OPROFILE_G4,
  671. .platform = "ppc7450",
  672. },
  673. { /* 7455 rev 1.x */
  674. .pvr_mask = 0xffffff00,
  675. .pvr_value = 0x80010100,
  676. .cpu_name = "7455",
  677. .cpu_features = CPU_FTRS_7455_1,
  678. .cpu_user_features = COMMON_USER |
  679. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  680. .icache_bsize = 32,
  681. .dcache_bsize = 32,
  682. .num_pmcs = 6,
  683. .cpu_setup = __setup_cpu_745x,
  684. .oprofile_cpu_type = "ppc/7450",
  685. .oprofile_type = PPC_OPROFILE_G4,
  686. .platform = "ppc7450",
  687. },
  688. { /* 7455 rev 2.0 */
  689. .pvr_mask = 0xffffffff,
  690. .pvr_value = 0x80010200,
  691. .cpu_name = "7455",
  692. .cpu_features = CPU_FTRS_7455_20,
  693. .cpu_user_features = COMMON_USER |
  694. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  695. .icache_bsize = 32,
  696. .dcache_bsize = 32,
  697. .num_pmcs = 6,
  698. .cpu_setup = __setup_cpu_745x,
  699. .oprofile_cpu_type = "ppc/7450",
  700. .oprofile_type = PPC_OPROFILE_G4,
  701. .platform = "ppc7450",
  702. },
  703. { /* 7455 others */
  704. .pvr_mask = 0xffff0000,
  705. .pvr_value = 0x80010000,
  706. .cpu_name = "7455",
  707. .cpu_features = CPU_FTRS_7455,
  708. .cpu_user_features = COMMON_USER |
  709. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  710. .icache_bsize = 32,
  711. .dcache_bsize = 32,
  712. .num_pmcs = 6,
  713. .cpu_setup = __setup_cpu_745x,
  714. .oprofile_cpu_type = "ppc/7450",
  715. .oprofile_type = PPC_OPROFILE_G4,
  716. .platform = "ppc7450",
  717. },
  718. { /* 7447/7457 Rev 1.0 */
  719. .pvr_mask = 0xffffffff,
  720. .pvr_value = 0x80020100,
  721. .cpu_name = "7447/7457",
  722. .cpu_features = CPU_FTRS_7447_10,
  723. .cpu_user_features = COMMON_USER |
  724. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  725. .icache_bsize = 32,
  726. .dcache_bsize = 32,
  727. .num_pmcs = 6,
  728. .cpu_setup = __setup_cpu_745x,
  729. .oprofile_cpu_type = "ppc/7450",
  730. .oprofile_type = PPC_OPROFILE_G4,
  731. .platform = "ppc7450",
  732. },
  733. { /* 7447/7457 Rev 1.1 */
  734. .pvr_mask = 0xffffffff,
  735. .pvr_value = 0x80020101,
  736. .cpu_name = "7447/7457",
  737. .cpu_features = CPU_FTRS_7447_10,
  738. .cpu_user_features = COMMON_USER |
  739. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  740. .icache_bsize = 32,
  741. .dcache_bsize = 32,
  742. .num_pmcs = 6,
  743. .cpu_setup = __setup_cpu_745x,
  744. .oprofile_cpu_type = "ppc/7450",
  745. .oprofile_type = PPC_OPROFILE_G4,
  746. .platform = "ppc7450",
  747. },
  748. { /* 7447/7457 Rev 1.2 and later */
  749. .pvr_mask = 0xffff0000,
  750. .pvr_value = 0x80020000,
  751. .cpu_name = "7447/7457",
  752. .cpu_features = CPU_FTRS_7447,
  753. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  754. .icache_bsize = 32,
  755. .dcache_bsize = 32,
  756. .num_pmcs = 6,
  757. .cpu_setup = __setup_cpu_745x,
  758. .oprofile_cpu_type = "ppc/7450",
  759. .oprofile_type = PPC_OPROFILE_G4,
  760. .platform = "ppc7450",
  761. },
  762. { /* 7447A */
  763. .pvr_mask = 0xffff0000,
  764. .pvr_value = 0x80030000,
  765. .cpu_name = "7447A",
  766. .cpu_features = CPU_FTRS_7447A,
  767. .cpu_user_features = COMMON_USER |
  768. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  769. .icache_bsize = 32,
  770. .dcache_bsize = 32,
  771. .num_pmcs = 6,
  772. .cpu_setup = __setup_cpu_745x,
  773. .oprofile_cpu_type = "ppc/7450",
  774. .oprofile_type = PPC_OPROFILE_G4,
  775. .platform = "ppc7450",
  776. },
  777. { /* 7448 */
  778. .pvr_mask = 0xffff0000,
  779. .pvr_value = 0x80040000,
  780. .cpu_name = "7448",
  781. .cpu_features = CPU_FTRS_7447A,
  782. .cpu_user_features = COMMON_USER |
  783. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  784. .icache_bsize = 32,
  785. .dcache_bsize = 32,
  786. .num_pmcs = 6,
  787. .cpu_setup = __setup_cpu_745x,
  788. .oprofile_cpu_type = "ppc/7450",
  789. .oprofile_type = PPC_OPROFILE_G4,
  790. .platform = "ppc7450",
  791. },
  792. { /* 82xx (8240, 8245, 8260 are all 603e cores) */
  793. .pvr_mask = 0x7fff0000,
  794. .pvr_value = 0x00810000,
  795. .cpu_name = "82xx",
  796. .cpu_features = CPU_FTRS_82XX,
  797. .cpu_user_features = COMMON_USER,
  798. .icache_bsize = 32,
  799. .dcache_bsize = 32,
  800. .cpu_setup = __setup_cpu_603,
  801. .platform = "ppc603",
  802. },
  803. { /* All G2_LE (603e core, plus some) have the same pvr */
  804. .pvr_mask = 0x7fff0000,
  805. .pvr_value = 0x00820000,
  806. .cpu_name = "G2_LE",
  807. .cpu_features = CPU_FTRS_G2_LE,
  808. .cpu_user_features = COMMON_USER,
  809. .icache_bsize = 32,
  810. .dcache_bsize = 32,
  811. .cpu_setup = __setup_cpu_603,
  812. .platform = "ppc603",
  813. },
  814. { /* e300c1 (a 603e core, plus some) on 83xx */
  815. .pvr_mask = 0x7fff0000,
  816. .pvr_value = 0x00830000,
  817. .cpu_name = "e300c1",
  818. .cpu_features = CPU_FTRS_E300,
  819. .cpu_user_features = COMMON_USER,
  820. .icache_bsize = 32,
  821. .dcache_bsize = 32,
  822. .cpu_setup = __setup_cpu_603,
  823. .platform = "ppc603",
  824. },
  825. { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
  826. .pvr_mask = 0x7fff0000,
  827. .pvr_value = 0x00840000,
  828. .cpu_name = "e300c2",
  829. .cpu_features = CPU_FTRS_E300,
  830. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  831. .icache_bsize = 32,
  832. .dcache_bsize = 32,
  833. .cpu_setup = __setup_cpu_603,
  834. .platform = "ppc603",
  835. },
  836. { /* default match, we assume split I/D cache & TB (non-601)... */
  837. .pvr_mask = 0x00000000,
  838. .pvr_value = 0x00000000,
  839. .cpu_name = "(generic PPC)",
  840. .cpu_features = CPU_FTRS_CLASSIC32,
  841. .cpu_user_features = COMMON_USER,
  842. .icache_bsize = 32,
  843. .dcache_bsize = 32,
  844. .platform = "ppc603",
  845. },
  846. #endif /* CLASSIC_PPC */
  847. #ifdef CONFIG_8xx
  848. { /* 8xx */
  849. .pvr_mask = 0xffff0000,
  850. .pvr_value = 0x00500000,
  851. .cpu_name = "8xx",
  852. /* CPU_FTR_MAYBE_CAN_DOZE is possible,
  853. * if the 8xx code is there.... */
  854. .cpu_features = CPU_FTRS_8XX,
  855. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  856. .icache_bsize = 16,
  857. .dcache_bsize = 16,
  858. .platform = "ppc823",
  859. },
  860. #endif /* CONFIG_8xx */
  861. #ifdef CONFIG_40x
  862. { /* 403GC */
  863. .pvr_mask = 0xffffff00,
  864. .pvr_value = 0x00200200,
  865. .cpu_name = "403GC",
  866. .cpu_features = CPU_FTRS_40X,
  867. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  868. .icache_bsize = 16,
  869. .dcache_bsize = 16,
  870. .platform = "ppc403",
  871. },
  872. { /* 403GCX */
  873. .pvr_mask = 0xffffff00,
  874. .pvr_value = 0x00201400,
  875. .cpu_name = "403GCX",
  876. .cpu_features = CPU_FTRS_40X,
  877. .cpu_user_features = PPC_FEATURE_32 |
  878. PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
  879. .icache_bsize = 16,
  880. .dcache_bsize = 16,
  881. .platform = "ppc403",
  882. },
  883. { /* 403G ?? */
  884. .pvr_mask = 0xffff0000,
  885. .pvr_value = 0x00200000,
  886. .cpu_name = "403G ??",
  887. .cpu_features = CPU_FTRS_40X,
  888. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  889. .icache_bsize = 16,
  890. .dcache_bsize = 16,
  891. .platform = "ppc403",
  892. },
  893. { /* 405GP */
  894. .pvr_mask = 0xffff0000,
  895. .pvr_value = 0x40110000,
  896. .cpu_name = "405GP",
  897. .cpu_features = CPU_FTRS_40X,
  898. .cpu_user_features = PPC_FEATURE_32 |
  899. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  900. .icache_bsize = 32,
  901. .dcache_bsize = 32,
  902. .platform = "ppc405",
  903. },
  904. { /* STB 03xxx */
  905. .pvr_mask = 0xffff0000,
  906. .pvr_value = 0x40130000,
  907. .cpu_name = "STB03xxx",
  908. .cpu_features = CPU_FTRS_40X,
  909. .cpu_user_features = PPC_FEATURE_32 |
  910. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  911. .icache_bsize = 32,
  912. .dcache_bsize = 32,
  913. .platform = "ppc405",
  914. },
  915. { /* STB 04xxx */
  916. .pvr_mask = 0xffff0000,
  917. .pvr_value = 0x41810000,
  918. .cpu_name = "STB04xxx",
  919. .cpu_features = CPU_FTRS_40X,
  920. .cpu_user_features = PPC_FEATURE_32 |
  921. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  922. .icache_bsize = 32,
  923. .dcache_bsize = 32,
  924. .platform = "ppc405",
  925. },
  926. { /* NP405L */
  927. .pvr_mask = 0xffff0000,
  928. .pvr_value = 0x41610000,
  929. .cpu_name = "NP405L",
  930. .cpu_features = CPU_FTRS_40X,
  931. .cpu_user_features = PPC_FEATURE_32 |
  932. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  933. .icache_bsize = 32,
  934. .dcache_bsize = 32,
  935. .platform = "ppc405",
  936. },
  937. { /* NP4GS3 */
  938. .pvr_mask = 0xffff0000,
  939. .pvr_value = 0x40B10000,
  940. .cpu_name = "NP4GS3",
  941. .cpu_features = CPU_FTRS_40X,
  942. .cpu_user_features = PPC_FEATURE_32 |
  943. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  944. .icache_bsize = 32,
  945. .dcache_bsize = 32,
  946. .platform = "ppc405",
  947. },
  948. { /* NP405H */
  949. .pvr_mask = 0xffff0000,
  950. .pvr_value = 0x41410000,
  951. .cpu_name = "NP405H",
  952. .cpu_features = CPU_FTRS_40X,
  953. .cpu_user_features = PPC_FEATURE_32 |
  954. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  955. .icache_bsize = 32,
  956. .dcache_bsize = 32,
  957. .platform = "ppc405",
  958. },
  959. { /* 405GPr */
  960. .pvr_mask = 0xffff0000,
  961. .pvr_value = 0x50910000,
  962. .cpu_name = "405GPr",
  963. .cpu_features = CPU_FTRS_40X,
  964. .cpu_user_features = PPC_FEATURE_32 |
  965. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  966. .icache_bsize = 32,
  967. .dcache_bsize = 32,
  968. .platform = "ppc405",
  969. },
  970. { /* STBx25xx */
  971. .pvr_mask = 0xffff0000,
  972. .pvr_value = 0x51510000,
  973. .cpu_name = "STBx25xx",
  974. .cpu_features = CPU_FTRS_40X,
  975. .cpu_user_features = PPC_FEATURE_32 |
  976. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  977. .icache_bsize = 32,
  978. .dcache_bsize = 32,
  979. .platform = "ppc405",
  980. },
  981. { /* 405LP */
  982. .pvr_mask = 0xffff0000,
  983. .pvr_value = 0x41F10000,
  984. .cpu_name = "405LP",
  985. .cpu_features = CPU_FTRS_40X,
  986. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  987. .icache_bsize = 32,
  988. .dcache_bsize = 32,
  989. .platform = "ppc405",
  990. },
  991. { /* Xilinx Virtex-II Pro */
  992. .pvr_mask = 0xfffff000,
  993. .pvr_value = 0x20010000,
  994. .cpu_name = "Virtex-II Pro",
  995. .cpu_features = CPU_FTRS_40X,
  996. .cpu_user_features = PPC_FEATURE_32 |
  997. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  998. .icache_bsize = 32,
  999. .dcache_bsize = 32,
  1000. .platform = "ppc405",
  1001. },
  1002. { /* Xilinx Virtex-4 FX */
  1003. .pvr_mask = 0xfffff000,
  1004. .pvr_value = 0x20011000,
  1005. .cpu_name = "Virtex-4 FX",
  1006. .cpu_features = CPU_FTRS_40X,
  1007. .cpu_user_features = PPC_FEATURE_32 |
  1008. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1009. .icache_bsize = 32,
  1010. .dcache_bsize = 32,
  1011. .platform = "ppc405",
  1012. },
  1013. { /* 405EP */
  1014. .pvr_mask = 0xffff0000,
  1015. .pvr_value = 0x51210000,
  1016. .cpu_name = "405EP",
  1017. .cpu_features = CPU_FTRS_40X,
  1018. .cpu_user_features = PPC_FEATURE_32 |
  1019. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1020. .icache_bsize = 32,
  1021. .dcache_bsize = 32,
  1022. .platform = "ppc405",
  1023. },
  1024. #endif /* CONFIG_40x */
  1025. #ifdef CONFIG_44x
  1026. {
  1027. .pvr_mask = 0xf0000fff,
  1028. .pvr_value = 0x40000850,
  1029. .cpu_name = "440EP Rev. A",
  1030. .cpu_features = CPU_FTRS_44X,
  1031. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1032. .icache_bsize = 32,
  1033. .dcache_bsize = 32,
  1034. .platform = "ppc440",
  1035. },
  1036. {
  1037. .pvr_mask = 0xf0000fff,
  1038. .pvr_value = 0x400008d3,
  1039. .cpu_name = "440EP Rev. B",
  1040. .cpu_features = CPU_FTRS_44X,
  1041. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1042. .icache_bsize = 32,
  1043. .dcache_bsize = 32,
  1044. .platform = "ppc440",
  1045. },
  1046. { /* 440GP Rev. B */
  1047. .pvr_mask = 0xf0000fff,
  1048. .pvr_value = 0x40000440,
  1049. .cpu_name = "440GP Rev. B",
  1050. .cpu_features = CPU_FTRS_44X,
  1051. .cpu_user_features = COMMON_USER_BOOKE,
  1052. .icache_bsize = 32,
  1053. .dcache_bsize = 32,
  1054. .platform = "ppc440gp",
  1055. },
  1056. { /* 440GP Rev. C */
  1057. .pvr_mask = 0xf0000fff,
  1058. .pvr_value = 0x40000481,
  1059. .cpu_name = "440GP Rev. C",
  1060. .cpu_features = CPU_FTRS_44X,
  1061. .cpu_user_features = COMMON_USER_BOOKE,
  1062. .icache_bsize = 32,
  1063. .dcache_bsize = 32,
  1064. .platform = "ppc440gp",
  1065. },
  1066. { /* 440GX Rev. A */
  1067. .pvr_mask = 0xf0000fff,
  1068. .pvr_value = 0x50000850,
  1069. .cpu_name = "440GX Rev. A",
  1070. .cpu_features = CPU_FTRS_44X,
  1071. .cpu_user_features = COMMON_USER_BOOKE,
  1072. .icache_bsize = 32,
  1073. .dcache_bsize = 32,
  1074. .platform = "ppc440",
  1075. },
  1076. { /* 440GX Rev. B */
  1077. .pvr_mask = 0xf0000fff,
  1078. .pvr_value = 0x50000851,
  1079. .cpu_name = "440GX Rev. B",
  1080. .cpu_features = CPU_FTRS_44X,
  1081. .cpu_user_features = COMMON_USER_BOOKE,
  1082. .icache_bsize = 32,
  1083. .dcache_bsize = 32,
  1084. .platform = "ppc440",
  1085. },
  1086. { /* 440GX Rev. C */
  1087. .pvr_mask = 0xf0000fff,
  1088. .pvr_value = 0x50000892,
  1089. .cpu_name = "440GX Rev. C",
  1090. .cpu_features = CPU_FTRS_44X,
  1091. .cpu_user_features = COMMON_USER_BOOKE,
  1092. .icache_bsize = 32,
  1093. .dcache_bsize = 32,
  1094. .platform = "ppc440",
  1095. },
  1096. { /* 440GX Rev. F */
  1097. .pvr_mask = 0xf0000fff,
  1098. .pvr_value = 0x50000894,
  1099. .cpu_name = "440GX Rev. F",
  1100. .cpu_features = CPU_FTRS_44X,
  1101. .cpu_user_features = COMMON_USER_BOOKE,
  1102. .icache_bsize = 32,
  1103. .dcache_bsize = 32,
  1104. .platform = "ppc440",
  1105. },
  1106. { /* 440SP Rev. A */
  1107. .pvr_mask = 0xff000fff,
  1108. .pvr_value = 0x53000891,
  1109. .cpu_name = "440SP Rev. A",
  1110. .cpu_features = CPU_FTRS_44X,
  1111. .cpu_user_features = COMMON_USER_BOOKE,
  1112. .icache_bsize = 32,
  1113. .dcache_bsize = 32,
  1114. .platform = "ppc440",
  1115. },
  1116. { /* 440SPe Rev. A */
  1117. .pvr_mask = 0xff000fff,
  1118. .pvr_value = 0x53000890,
  1119. .cpu_name = "440SPe Rev. A",
  1120. .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
  1121. CPU_FTR_USE_TB,
  1122. .cpu_user_features = COMMON_USER_BOOKE,
  1123. .icache_bsize = 32,
  1124. .dcache_bsize = 32,
  1125. .platform = "ppc440",
  1126. },
  1127. #endif /* CONFIG_44x */
  1128. #ifdef CONFIG_FSL_BOOKE
  1129. { /* e200z5 */
  1130. .pvr_mask = 0xfff00000,
  1131. .pvr_value = 0x81000000,
  1132. .cpu_name = "e200z5",
  1133. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1134. .cpu_features = CPU_FTRS_E200,
  1135. .cpu_user_features = COMMON_USER_BOOKE |
  1136. PPC_FEATURE_HAS_EFP_SINGLE |
  1137. PPC_FEATURE_UNIFIED_CACHE,
  1138. .dcache_bsize = 32,
  1139. .platform = "ppc5554",
  1140. },
  1141. { /* e200z6 */
  1142. .pvr_mask = 0xfff00000,
  1143. .pvr_value = 0x81100000,
  1144. .cpu_name = "e200z6",
  1145. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1146. .cpu_features = CPU_FTRS_E200,
  1147. .cpu_user_features = COMMON_USER_BOOKE |
  1148. PPC_FEATURE_SPE_COMP |
  1149. PPC_FEATURE_HAS_EFP_SINGLE |
  1150. PPC_FEATURE_UNIFIED_CACHE,
  1151. .dcache_bsize = 32,
  1152. .platform = "ppc5554",
  1153. },
  1154. { /* e500 */
  1155. .pvr_mask = 0xffff0000,
  1156. .pvr_value = 0x80200000,
  1157. .cpu_name = "e500",
  1158. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1159. .cpu_features = CPU_FTRS_E500,
  1160. .cpu_user_features = COMMON_USER_BOOKE |
  1161. PPC_FEATURE_SPE_COMP |
  1162. PPC_FEATURE_HAS_EFP_SINGLE,
  1163. .icache_bsize = 32,
  1164. .dcache_bsize = 32,
  1165. .num_pmcs = 4,
  1166. .oprofile_cpu_type = "ppc/e500",
  1167. .oprofile_type = PPC_OPROFILE_BOOKE,
  1168. .platform = "ppc8540",
  1169. },
  1170. { /* e500v2 */
  1171. .pvr_mask = 0xffff0000,
  1172. .pvr_value = 0x80210000,
  1173. .cpu_name = "e500v2",
  1174. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1175. .cpu_features = CPU_FTRS_E500_2,
  1176. .cpu_user_features = COMMON_USER_BOOKE |
  1177. PPC_FEATURE_SPE_COMP |
  1178. PPC_FEATURE_HAS_EFP_SINGLE |
  1179. PPC_FEATURE_HAS_EFP_DOUBLE,
  1180. .icache_bsize = 32,
  1181. .dcache_bsize = 32,
  1182. .num_pmcs = 4,
  1183. .oprofile_cpu_type = "ppc/e500",
  1184. .oprofile_type = PPC_OPROFILE_BOOKE,
  1185. .platform = "ppc8548",
  1186. },
  1187. #endif
  1188. #if !CLASSIC_PPC
  1189. { /* default match */
  1190. .pvr_mask = 0x00000000,
  1191. .pvr_value = 0x00000000,
  1192. .cpu_name = "(generic PPC)",
  1193. .cpu_features = CPU_FTRS_GENERIC_32,
  1194. .cpu_user_features = PPC_FEATURE_32,
  1195. .icache_bsize = 32,
  1196. .dcache_bsize = 32,
  1197. .platform = "powerpc",
  1198. }
  1199. #endif /* !CLASSIC_PPC */
  1200. #endif /* CONFIG_PPC32 */
  1201. };
  1202. struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr)
  1203. {
  1204. struct cpu_spec *s = cpu_specs;
  1205. struct cpu_spec **cur = &cur_cpu_spec;
  1206. int i;
  1207. s = PTRRELOC(s);
  1208. cur = PTRRELOC(cur);
  1209. for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++)
  1210. if ((pvr & s->pvr_mask) == s->pvr_value) {
  1211. *cur = cpu_specs + i;
  1212. #ifdef CONFIG_PPC64
  1213. /* ppc64 expects identify_cpu to also call setup_cpu
  1214. * for that processor. I will consolidate that at a
  1215. * later time, for now, just use our friend #ifdef.
  1216. * we also don't need to PTRRELOC the function pointer
  1217. * on ppc64 as we are running at 0 in real mode.
  1218. */
  1219. if (s->cpu_setup) {
  1220. s->cpu_setup(offset, s);
  1221. }
  1222. #endif /* CONFIG_PPC64 */
  1223. return s;
  1224. }
  1225. BUG();
  1226. return NULL;
  1227. }
  1228. void do_feature_fixups(unsigned long value, void *fixup_start, void *fixup_end)
  1229. {
  1230. struct fixup_entry {
  1231. unsigned long mask;
  1232. unsigned long value;
  1233. long start_off;
  1234. long end_off;
  1235. } *fcur, *fend;
  1236. fcur = fixup_start;
  1237. fend = fixup_end;
  1238. for (; fcur < fend; fcur++) {
  1239. unsigned int *pstart, *pend, *p;
  1240. if ((value & fcur->mask) == fcur->value)
  1241. continue;
  1242. /* These PTRRELOCs will disappear once the new scheme for
  1243. * modules and vdso is implemented
  1244. */
  1245. pstart = ((unsigned int *)fcur) + (fcur->start_off / 4);
  1246. pend = ((unsigned int *)fcur) + (fcur->end_off / 4);
  1247. for (p = pstart; p < pend; p++) {
  1248. *p = 0x60000000u;
  1249. asm volatile ("dcbst 0, %0" : : "r" (p));
  1250. }
  1251. asm volatile ("sync" : : : "memory");
  1252. for (p = pstart; p < pend; p++)
  1253. asm volatile ("icbi 0,%0" : : "r" (p));
  1254. asm volatile ("sync; isync" : : : "memory");
  1255. }
  1256. }