radeon_ttm.c 30 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30. * Dave Airlie
  31. */
  32. #include <ttm/ttm_bo_api.h>
  33. #include <ttm/ttm_bo_driver.h>
  34. #include <ttm/ttm_placement.h>
  35. #include <ttm/ttm_module.h>
  36. #include <ttm/ttm_page_alloc.h>
  37. #include <drm/drmP.h>
  38. #include <drm/radeon_drm.h>
  39. #include <linux/seq_file.h>
  40. #include <linux/slab.h>
  41. #include <linux/swiotlb.h>
  42. #include <linux/swap.h>
  43. #include <linux/pagemap.h>
  44. #include <linux/debugfs.h>
  45. #include "radeon_reg.h"
  46. #include "radeon.h"
  47. #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  48. static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
  49. static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
  50. static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
  51. {
  52. struct radeon_mman *mman;
  53. struct radeon_device *rdev;
  54. mman = container_of(bdev, struct radeon_mman, bdev);
  55. rdev = container_of(mman, struct radeon_device, mman);
  56. return rdev;
  57. }
  58. /*
  59. * Global memory.
  60. */
  61. static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
  62. {
  63. return ttm_mem_global_init(ref->object);
  64. }
  65. static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
  66. {
  67. ttm_mem_global_release(ref->object);
  68. }
  69. static int radeon_ttm_global_init(struct radeon_device *rdev)
  70. {
  71. struct drm_global_reference *global_ref;
  72. int r;
  73. rdev->mman.mem_global_referenced = false;
  74. global_ref = &rdev->mman.mem_global_ref;
  75. global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  76. global_ref->size = sizeof(struct ttm_mem_global);
  77. global_ref->init = &radeon_ttm_mem_global_init;
  78. global_ref->release = &radeon_ttm_mem_global_release;
  79. r = drm_global_item_ref(global_ref);
  80. if (r != 0) {
  81. DRM_ERROR("Failed setting up TTM memory accounting "
  82. "subsystem.\n");
  83. return r;
  84. }
  85. rdev->mman.bo_global_ref.mem_glob =
  86. rdev->mman.mem_global_ref.object;
  87. global_ref = &rdev->mman.bo_global_ref.ref;
  88. global_ref->global_type = DRM_GLOBAL_TTM_BO;
  89. global_ref->size = sizeof(struct ttm_bo_global);
  90. global_ref->init = &ttm_bo_global_init;
  91. global_ref->release = &ttm_bo_global_release;
  92. r = drm_global_item_ref(global_ref);
  93. if (r != 0) {
  94. DRM_ERROR("Failed setting up TTM BO subsystem.\n");
  95. drm_global_item_unref(&rdev->mman.mem_global_ref);
  96. return r;
  97. }
  98. rdev->mman.mem_global_referenced = true;
  99. return 0;
  100. }
  101. static void radeon_ttm_global_fini(struct radeon_device *rdev)
  102. {
  103. if (rdev->mman.mem_global_referenced) {
  104. drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
  105. drm_global_item_unref(&rdev->mman.mem_global_ref);
  106. rdev->mman.mem_global_referenced = false;
  107. }
  108. }
  109. static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
  110. {
  111. return 0;
  112. }
  113. static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  114. struct ttm_mem_type_manager *man)
  115. {
  116. struct radeon_device *rdev;
  117. rdev = radeon_get_rdev(bdev);
  118. switch (type) {
  119. case TTM_PL_SYSTEM:
  120. /* System memory */
  121. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  122. man->available_caching = TTM_PL_MASK_CACHING;
  123. man->default_caching = TTM_PL_FLAG_CACHED;
  124. break;
  125. case TTM_PL_TT:
  126. man->func = &ttm_bo_manager_func;
  127. man->gpu_offset = rdev->mc.gtt_start;
  128. man->available_caching = TTM_PL_MASK_CACHING;
  129. man->default_caching = TTM_PL_FLAG_CACHED;
  130. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
  131. #if __OS_HAS_AGP
  132. if (rdev->flags & RADEON_IS_AGP) {
  133. if (!rdev->ddev->agp) {
  134. DRM_ERROR("AGP is not enabled for memory type %u\n",
  135. (unsigned)type);
  136. return -EINVAL;
  137. }
  138. if (!rdev->ddev->agp->cant_use_aperture)
  139. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  140. man->available_caching = TTM_PL_FLAG_UNCACHED |
  141. TTM_PL_FLAG_WC;
  142. man->default_caching = TTM_PL_FLAG_WC;
  143. }
  144. #endif
  145. break;
  146. case TTM_PL_VRAM:
  147. /* "On-card" video ram */
  148. man->func = &ttm_bo_manager_func;
  149. man->gpu_offset = rdev->mc.vram_start;
  150. man->flags = TTM_MEMTYPE_FLAG_FIXED |
  151. TTM_MEMTYPE_FLAG_MAPPABLE;
  152. man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
  153. man->default_caching = TTM_PL_FLAG_WC;
  154. break;
  155. default:
  156. DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
  157. return -EINVAL;
  158. }
  159. return 0;
  160. }
  161. static void radeon_evict_flags(struct ttm_buffer_object *bo,
  162. struct ttm_placement *placement)
  163. {
  164. static struct ttm_place placements = {
  165. .fpfn = 0,
  166. .lpfn = 0,
  167. .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
  168. };
  169. struct radeon_bo *rbo;
  170. if (!radeon_ttm_bo_is_radeon_bo(bo)) {
  171. placement->placement = &placements;
  172. placement->busy_placement = &placements;
  173. placement->num_placement = 1;
  174. placement->num_busy_placement = 1;
  175. return;
  176. }
  177. rbo = container_of(bo, struct radeon_bo, tbo);
  178. switch (bo->mem.mem_type) {
  179. case TTM_PL_VRAM:
  180. if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
  181. radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
  182. else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size &&
  183. bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) {
  184. unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
  185. int i;
  186. /* Try evicting to the CPU inaccessible part of VRAM
  187. * first, but only set GTT as busy placement, so this
  188. * BO will be evicted to GTT rather than causing other
  189. * BOs to be evicted from VRAM
  190. */
  191. radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM |
  192. RADEON_GEM_DOMAIN_GTT);
  193. rbo->placement.num_busy_placement = 0;
  194. for (i = 0; i < rbo->placement.num_placement; i++) {
  195. if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) {
  196. if (rbo->placements[0].fpfn < fpfn)
  197. rbo->placements[0].fpfn = fpfn;
  198. } else {
  199. rbo->placement.busy_placement =
  200. &rbo->placements[i];
  201. rbo->placement.num_busy_placement = 1;
  202. }
  203. }
  204. } else
  205. radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
  206. break;
  207. case TTM_PL_TT:
  208. default:
  209. radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
  210. }
  211. *placement = rbo->placement;
  212. }
  213. static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
  214. {
  215. struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
  216. return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
  217. }
  218. static void radeon_move_null(struct ttm_buffer_object *bo,
  219. struct ttm_mem_reg *new_mem)
  220. {
  221. struct ttm_mem_reg *old_mem = &bo->mem;
  222. BUG_ON(old_mem->mm_node != NULL);
  223. *old_mem = *new_mem;
  224. new_mem->mm_node = NULL;
  225. }
  226. static int radeon_move_blit(struct ttm_buffer_object *bo,
  227. bool evict, bool no_wait_gpu,
  228. struct ttm_mem_reg *new_mem,
  229. struct ttm_mem_reg *old_mem)
  230. {
  231. struct radeon_device *rdev;
  232. uint64_t old_start, new_start;
  233. struct radeon_fence *fence;
  234. unsigned num_pages;
  235. int r, ridx;
  236. rdev = radeon_get_rdev(bo->bdev);
  237. ridx = radeon_copy_ring_index(rdev);
  238. old_start = old_mem->start << PAGE_SHIFT;
  239. new_start = new_mem->start << PAGE_SHIFT;
  240. switch (old_mem->mem_type) {
  241. case TTM_PL_VRAM:
  242. old_start += rdev->mc.vram_start;
  243. break;
  244. case TTM_PL_TT:
  245. old_start += rdev->mc.gtt_start;
  246. break;
  247. default:
  248. DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
  249. return -EINVAL;
  250. }
  251. switch (new_mem->mem_type) {
  252. case TTM_PL_VRAM:
  253. new_start += rdev->mc.vram_start;
  254. break;
  255. case TTM_PL_TT:
  256. new_start += rdev->mc.gtt_start;
  257. break;
  258. default:
  259. DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
  260. return -EINVAL;
  261. }
  262. if (!rdev->ring[ridx].ready) {
  263. DRM_ERROR("Trying to move memory with ring turned off.\n");
  264. return -EINVAL;
  265. }
  266. BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
  267. num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
  268. fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->resv);
  269. if (IS_ERR(fence))
  270. return PTR_ERR(fence);
  271. r = ttm_bo_move_accel_cleanup(bo, &fence->base,
  272. evict, no_wait_gpu, new_mem);
  273. radeon_fence_unref(&fence);
  274. return r;
  275. }
  276. static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
  277. bool evict, bool interruptible,
  278. bool no_wait_gpu,
  279. struct ttm_mem_reg *new_mem)
  280. {
  281. struct radeon_device *rdev;
  282. struct ttm_mem_reg *old_mem = &bo->mem;
  283. struct ttm_mem_reg tmp_mem;
  284. struct ttm_place placements;
  285. struct ttm_placement placement;
  286. int r;
  287. rdev = radeon_get_rdev(bo->bdev);
  288. tmp_mem = *new_mem;
  289. tmp_mem.mm_node = NULL;
  290. placement.num_placement = 1;
  291. placement.placement = &placements;
  292. placement.num_busy_placement = 1;
  293. placement.busy_placement = &placements;
  294. placements.fpfn = 0;
  295. placements.lpfn = 0;
  296. placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
  297. r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
  298. interruptible, no_wait_gpu);
  299. if (unlikely(r)) {
  300. return r;
  301. }
  302. r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
  303. if (unlikely(r)) {
  304. goto out_cleanup;
  305. }
  306. r = ttm_tt_bind(bo->ttm, &tmp_mem);
  307. if (unlikely(r)) {
  308. goto out_cleanup;
  309. }
  310. r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
  311. if (unlikely(r)) {
  312. goto out_cleanup;
  313. }
  314. r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
  315. out_cleanup:
  316. ttm_bo_mem_put(bo, &tmp_mem);
  317. return r;
  318. }
  319. static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
  320. bool evict, bool interruptible,
  321. bool no_wait_gpu,
  322. struct ttm_mem_reg *new_mem)
  323. {
  324. struct radeon_device *rdev;
  325. struct ttm_mem_reg *old_mem = &bo->mem;
  326. struct ttm_mem_reg tmp_mem;
  327. struct ttm_placement placement;
  328. struct ttm_place placements;
  329. int r;
  330. rdev = radeon_get_rdev(bo->bdev);
  331. tmp_mem = *new_mem;
  332. tmp_mem.mm_node = NULL;
  333. placement.num_placement = 1;
  334. placement.placement = &placements;
  335. placement.num_busy_placement = 1;
  336. placement.busy_placement = &placements;
  337. placements.fpfn = 0;
  338. placements.lpfn = 0;
  339. placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
  340. r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
  341. interruptible, no_wait_gpu);
  342. if (unlikely(r)) {
  343. return r;
  344. }
  345. r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
  346. if (unlikely(r)) {
  347. goto out_cleanup;
  348. }
  349. r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
  350. if (unlikely(r)) {
  351. goto out_cleanup;
  352. }
  353. out_cleanup:
  354. ttm_bo_mem_put(bo, &tmp_mem);
  355. return r;
  356. }
  357. static int radeon_bo_move(struct ttm_buffer_object *bo,
  358. bool evict, bool interruptible,
  359. bool no_wait_gpu,
  360. struct ttm_mem_reg *new_mem)
  361. {
  362. struct radeon_device *rdev;
  363. struct ttm_mem_reg *old_mem = &bo->mem;
  364. int r;
  365. rdev = radeon_get_rdev(bo->bdev);
  366. if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
  367. radeon_move_null(bo, new_mem);
  368. return 0;
  369. }
  370. if ((old_mem->mem_type == TTM_PL_TT &&
  371. new_mem->mem_type == TTM_PL_SYSTEM) ||
  372. (old_mem->mem_type == TTM_PL_SYSTEM &&
  373. new_mem->mem_type == TTM_PL_TT)) {
  374. /* bind is enough */
  375. radeon_move_null(bo, new_mem);
  376. return 0;
  377. }
  378. if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
  379. rdev->asic->copy.copy == NULL) {
  380. /* use memcpy */
  381. goto memcpy;
  382. }
  383. if (old_mem->mem_type == TTM_PL_VRAM &&
  384. new_mem->mem_type == TTM_PL_SYSTEM) {
  385. r = radeon_move_vram_ram(bo, evict, interruptible,
  386. no_wait_gpu, new_mem);
  387. } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
  388. new_mem->mem_type == TTM_PL_VRAM) {
  389. r = radeon_move_ram_vram(bo, evict, interruptible,
  390. no_wait_gpu, new_mem);
  391. } else {
  392. r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
  393. }
  394. if (r) {
  395. memcpy:
  396. r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
  397. if (r) {
  398. return r;
  399. }
  400. }
  401. /* update statistics */
  402. atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved);
  403. return 0;
  404. }
  405. static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
  406. {
  407. struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
  408. struct radeon_device *rdev = radeon_get_rdev(bdev);
  409. mem->bus.addr = NULL;
  410. mem->bus.offset = 0;
  411. mem->bus.size = mem->num_pages << PAGE_SHIFT;
  412. mem->bus.base = 0;
  413. mem->bus.is_iomem = false;
  414. if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
  415. return -EINVAL;
  416. switch (mem->mem_type) {
  417. case TTM_PL_SYSTEM:
  418. /* system memory */
  419. return 0;
  420. case TTM_PL_TT:
  421. #if __OS_HAS_AGP
  422. if (rdev->flags & RADEON_IS_AGP) {
  423. /* RADEON_IS_AGP is set only if AGP is active */
  424. mem->bus.offset = mem->start << PAGE_SHIFT;
  425. mem->bus.base = rdev->mc.agp_base;
  426. mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
  427. }
  428. #endif
  429. break;
  430. case TTM_PL_VRAM:
  431. mem->bus.offset = mem->start << PAGE_SHIFT;
  432. /* check if it's visible */
  433. if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
  434. return -EINVAL;
  435. mem->bus.base = rdev->mc.aper_base;
  436. mem->bus.is_iomem = true;
  437. #ifdef __alpha__
  438. /*
  439. * Alpha: use bus.addr to hold the ioremap() return,
  440. * so we can modify bus.base below.
  441. */
  442. if (mem->placement & TTM_PL_FLAG_WC)
  443. mem->bus.addr =
  444. ioremap_wc(mem->bus.base + mem->bus.offset,
  445. mem->bus.size);
  446. else
  447. mem->bus.addr =
  448. ioremap_nocache(mem->bus.base + mem->bus.offset,
  449. mem->bus.size);
  450. /*
  451. * Alpha: Use just the bus offset plus
  452. * the hose/domain memory base for bus.base.
  453. * It then can be used to build PTEs for VRAM
  454. * access, as done in ttm_bo_vm_fault().
  455. */
  456. mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
  457. rdev->ddev->hose->dense_mem_base;
  458. #endif
  459. break;
  460. default:
  461. return -EINVAL;
  462. }
  463. return 0;
  464. }
  465. static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
  466. {
  467. }
  468. /*
  469. * TTM backend functions.
  470. */
  471. struct radeon_ttm_tt {
  472. struct ttm_dma_tt ttm;
  473. struct radeon_device *rdev;
  474. u64 offset;
  475. uint64_t userptr;
  476. struct mm_struct *usermm;
  477. uint32_t userflags;
  478. };
  479. /* prepare the sg table with the user pages */
  480. static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm)
  481. {
  482. struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
  483. struct radeon_ttm_tt *gtt = (void *)ttm;
  484. unsigned pinned = 0, nents;
  485. int r;
  486. int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
  487. enum dma_data_direction direction = write ?
  488. DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
  489. if (current->mm != gtt->usermm)
  490. return -EPERM;
  491. if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
  492. /* check that we only pin down anonymous memory
  493. to prevent problems with writeback */
  494. unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
  495. struct vm_area_struct *vma;
  496. vma = find_vma(gtt->usermm, gtt->userptr);
  497. if (!vma || vma->vm_file || vma->vm_end < end)
  498. return -EPERM;
  499. }
  500. do {
  501. unsigned num_pages = ttm->num_pages - pinned;
  502. uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
  503. struct page **pages = ttm->pages + pinned;
  504. r = get_user_pages(current, current->mm, userptr, num_pages,
  505. write, 0, pages, NULL);
  506. if (r < 0)
  507. goto release_pages;
  508. pinned += r;
  509. } while (pinned < ttm->num_pages);
  510. r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
  511. ttm->num_pages << PAGE_SHIFT,
  512. GFP_KERNEL);
  513. if (r)
  514. goto release_sg;
  515. r = -ENOMEM;
  516. nents = dma_map_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
  517. if (nents != ttm->sg->nents)
  518. goto release_sg;
  519. drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
  520. gtt->ttm.dma_address, ttm->num_pages);
  521. return 0;
  522. release_sg:
  523. kfree(ttm->sg);
  524. release_pages:
  525. release_pages(ttm->pages, pinned, 0);
  526. return r;
  527. }
  528. static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
  529. {
  530. struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
  531. struct radeon_ttm_tt *gtt = (void *)ttm;
  532. struct scatterlist *sg;
  533. int i;
  534. int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
  535. enum dma_data_direction direction = write ?
  536. DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
  537. /* free the sg table and pages again */
  538. dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
  539. for_each_sg(ttm->sg->sgl, sg, ttm->sg->nents, i) {
  540. struct page *page = sg_page(sg);
  541. if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY))
  542. set_page_dirty(page);
  543. mark_page_accessed(page);
  544. page_cache_release(page);
  545. }
  546. sg_free_table(ttm->sg);
  547. }
  548. static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
  549. struct ttm_mem_reg *bo_mem)
  550. {
  551. struct radeon_ttm_tt *gtt = (void*)ttm;
  552. uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
  553. RADEON_GART_PAGE_WRITE;
  554. int r;
  555. if (gtt->userptr) {
  556. radeon_ttm_tt_pin_userptr(ttm);
  557. flags &= ~RADEON_GART_PAGE_WRITE;
  558. }
  559. gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
  560. if (!ttm->num_pages) {
  561. WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
  562. ttm->num_pages, bo_mem, ttm);
  563. }
  564. if (ttm->caching_state == tt_cached)
  565. flags |= RADEON_GART_PAGE_SNOOP;
  566. r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages,
  567. ttm->pages, gtt->ttm.dma_address, flags);
  568. if (r) {
  569. DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
  570. ttm->num_pages, (unsigned)gtt->offset);
  571. return r;
  572. }
  573. return 0;
  574. }
  575. static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
  576. {
  577. struct radeon_ttm_tt *gtt = (void *)ttm;
  578. radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
  579. if (gtt->userptr)
  580. radeon_ttm_tt_unpin_userptr(ttm);
  581. return 0;
  582. }
  583. static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
  584. {
  585. struct radeon_ttm_tt *gtt = (void *)ttm;
  586. ttm_dma_tt_fini(&gtt->ttm);
  587. kfree(gtt);
  588. }
  589. static struct ttm_backend_func radeon_backend_func = {
  590. .bind = &radeon_ttm_backend_bind,
  591. .unbind = &radeon_ttm_backend_unbind,
  592. .destroy = &radeon_ttm_backend_destroy,
  593. };
  594. static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev,
  595. unsigned long size, uint32_t page_flags,
  596. struct page *dummy_read_page)
  597. {
  598. struct radeon_device *rdev;
  599. struct radeon_ttm_tt *gtt;
  600. rdev = radeon_get_rdev(bdev);
  601. #if __OS_HAS_AGP
  602. if (rdev->flags & RADEON_IS_AGP) {
  603. return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge,
  604. size, page_flags, dummy_read_page);
  605. }
  606. #endif
  607. gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
  608. if (gtt == NULL) {
  609. return NULL;
  610. }
  611. gtt->ttm.ttm.func = &radeon_backend_func;
  612. gtt->rdev = rdev;
  613. if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
  614. kfree(gtt);
  615. return NULL;
  616. }
  617. return &gtt->ttm.ttm;
  618. }
  619. static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm)
  620. {
  621. if (!ttm || ttm->func != &radeon_backend_func)
  622. return NULL;
  623. return (struct radeon_ttm_tt *)ttm;
  624. }
  625. static int radeon_ttm_tt_populate(struct ttm_tt *ttm)
  626. {
  627. struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
  628. struct radeon_device *rdev;
  629. unsigned i;
  630. int r;
  631. bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
  632. if (ttm->state != tt_unpopulated)
  633. return 0;
  634. if (gtt && gtt->userptr) {
  635. ttm->sg = kcalloc(1, sizeof(struct sg_table), GFP_KERNEL);
  636. if (!ttm->sg)
  637. return -ENOMEM;
  638. ttm->page_flags |= TTM_PAGE_FLAG_SG;
  639. ttm->state = tt_unbound;
  640. return 0;
  641. }
  642. if (slave && ttm->sg) {
  643. drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
  644. gtt->ttm.dma_address, ttm->num_pages);
  645. ttm->state = tt_unbound;
  646. return 0;
  647. }
  648. rdev = radeon_get_rdev(ttm->bdev);
  649. #if __OS_HAS_AGP
  650. if (rdev->flags & RADEON_IS_AGP) {
  651. return ttm_agp_tt_populate(ttm);
  652. }
  653. #endif
  654. #ifdef CONFIG_SWIOTLB
  655. if (swiotlb_nr_tbl()) {
  656. return ttm_dma_populate(&gtt->ttm, rdev->dev);
  657. }
  658. #endif
  659. r = ttm_pool_populate(ttm);
  660. if (r) {
  661. return r;
  662. }
  663. for (i = 0; i < ttm->num_pages; i++) {
  664. gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i],
  665. 0, PAGE_SIZE,
  666. PCI_DMA_BIDIRECTIONAL);
  667. if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) {
  668. while (--i) {
  669. pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
  670. PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  671. gtt->ttm.dma_address[i] = 0;
  672. }
  673. ttm_pool_unpopulate(ttm);
  674. return -EFAULT;
  675. }
  676. }
  677. return 0;
  678. }
  679. static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
  680. {
  681. struct radeon_device *rdev;
  682. struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
  683. unsigned i;
  684. bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
  685. if (gtt && gtt->userptr) {
  686. kfree(ttm->sg);
  687. ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
  688. return;
  689. }
  690. if (slave)
  691. return;
  692. rdev = radeon_get_rdev(ttm->bdev);
  693. #if __OS_HAS_AGP
  694. if (rdev->flags & RADEON_IS_AGP) {
  695. ttm_agp_tt_unpopulate(ttm);
  696. return;
  697. }
  698. #endif
  699. #ifdef CONFIG_SWIOTLB
  700. if (swiotlb_nr_tbl()) {
  701. ttm_dma_unpopulate(&gtt->ttm, rdev->dev);
  702. return;
  703. }
  704. #endif
  705. for (i = 0; i < ttm->num_pages; i++) {
  706. if (gtt->ttm.dma_address[i]) {
  707. pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
  708. PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  709. }
  710. }
  711. ttm_pool_unpopulate(ttm);
  712. }
  713. int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
  714. uint32_t flags)
  715. {
  716. struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
  717. if (gtt == NULL)
  718. return -EINVAL;
  719. gtt->userptr = addr;
  720. gtt->usermm = current->mm;
  721. gtt->userflags = flags;
  722. return 0;
  723. }
  724. bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm)
  725. {
  726. struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
  727. if (gtt == NULL)
  728. return false;
  729. return !!gtt->userptr;
  730. }
  731. bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm)
  732. {
  733. struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
  734. if (gtt == NULL)
  735. return false;
  736. return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
  737. }
  738. static struct ttm_bo_driver radeon_bo_driver = {
  739. .ttm_tt_create = &radeon_ttm_tt_create,
  740. .ttm_tt_populate = &radeon_ttm_tt_populate,
  741. .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
  742. .invalidate_caches = &radeon_invalidate_caches,
  743. .init_mem_type = &radeon_init_mem_type,
  744. .evict_flags = &radeon_evict_flags,
  745. .move = &radeon_bo_move,
  746. .verify_access = &radeon_verify_access,
  747. .move_notify = &radeon_bo_move_notify,
  748. .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
  749. .io_mem_reserve = &radeon_ttm_io_mem_reserve,
  750. .io_mem_free = &radeon_ttm_io_mem_free,
  751. };
  752. int radeon_ttm_init(struct radeon_device *rdev)
  753. {
  754. int r;
  755. r = radeon_ttm_global_init(rdev);
  756. if (r) {
  757. return r;
  758. }
  759. /* No others user of address space so set it to 0 */
  760. r = ttm_bo_device_init(&rdev->mman.bdev,
  761. rdev->mman.bo_global_ref.ref.object,
  762. &radeon_bo_driver,
  763. rdev->ddev->anon_inode->i_mapping,
  764. DRM_FILE_PAGE_OFFSET,
  765. rdev->need_dma32);
  766. if (r) {
  767. DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
  768. return r;
  769. }
  770. rdev->mman.initialized = true;
  771. r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
  772. rdev->mc.real_vram_size >> PAGE_SHIFT);
  773. if (r) {
  774. DRM_ERROR("Failed initializing VRAM heap.\n");
  775. return r;
  776. }
  777. /* Change the size here instead of the init above so only lpfn is affected */
  778. radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
  779. r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
  780. RADEON_GEM_DOMAIN_VRAM, 0, NULL,
  781. NULL, &rdev->stollen_vga_memory);
  782. if (r) {
  783. return r;
  784. }
  785. r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
  786. if (r)
  787. return r;
  788. r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
  789. radeon_bo_unreserve(rdev->stollen_vga_memory);
  790. if (r) {
  791. radeon_bo_unref(&rdev->stollen_vga_memory);
  792. return r;
  793. }
  794. DRM_INFO("radeon: %uM of VRAM memory ready\n",
  795. (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
  796. r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
  797. rdev->mc.gtt_size >> PAGE_SHIFT);
  798. if (r) {
  799. DRM_ERROR("Failed initializing GTT heap.\n");
  800. return r;
  801. }
  802. DRM_INFO("radeon: %uM of GTT memory ready.\n",
  803. (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
  804. r = radeon_ttm_debugfs_init(rdev);
  805. if (r) {
  806. DRM_ERROR("Failed to init debugfs\n");
  807. return r;
  808. }
  809. return 0;
  810. }
  811. void radeon_ttm_fini(struct radeon_device *rdev)
  812. {
  813. int r;
  814. if (!rdev->mman.initialized)
  815. return;
  816. radeon_ttm_debugfs_fini(rdev);
  817. if (rdev->stollen_vga_memory) {
  818. r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
  819. if (r == 0) {
  820. radeon_bo_unpin(rdev->stollen_vga_memory);
  821. radeon_bo_unreserve(rdev->stollen_vga_memory);
  822. }
  823. radeon_bo_unref(&rdev->stollen_vga_memory);
  824. }
  825. ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
  826. ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
  827. ttm_bo_device_release(&rdev->mman.bdev);
  828. radeon_gart_fini(rdev);
  829. radeon_ttm_global_fini(rdev);
  830. rdev->mman.initialized = false;
  831. DRM_INFO("radeon: ttm finalized\n");
  832. }
  833. /* this should only be called at bootup or when userspace
  834. * isn't running */
  835. void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
  836. {
  837. struct ttm_mem_type_manager *man;
  838. if (!rdev->mman.initialized)
  839. return;
  840. man = &rdev->mman.bdev.man[TTM_PL_VRAM];
  841. /* this just adjusts TTM size idea, which sets lpfn to the correct value */
  842. man->size = size >> PAGE_SHIFT;
  843. }
  844. static struct vm_operations_struct radeon_ttm_vm_ops;
  845. static const struct vm_operations_struct *ttm_vm_ops = NULL;
  846. static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
  847. {
  848. struct ttm_buffer_object *bo;
  849. struct radeon_device *rdev;
  850. int r;
  851. bo = (struct ttm_buffer_object *)vma->vm_private_data;
  852. if (bo == NULL) {
  853. return VM_FAULT_NOPAGE;
  854. }
  855. rdev = radeon_get_rdev(bo->bdev);
  856. down_read(&rdev->pm.mclk_lock);
  857. r = ttm_vm_ops->fault(vma, vmf);
  858. up_read(&rdev->pm.mclk_lock);
  859. return r;
  860. }
  861. int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
  862. {
  863. struct drm_file *file_priv;
  864. struct radeon_device *rdev;
  865. int r;
  866. if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
  867. return -EINVAL;
  868. }
  869. file_priv = filp->private_data;
  870. rdev = file_priv->minor->dev->dev_private;
  871. if (rdev == NULL) {
  872. return -EINVAL;
  873. }
  874. r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
  875. if (unlikely(r != 0)) {
  876. return r;
  877. }
  878. if (unlikely(ttm_vm_ops == NULL)) {
  879. ttm_vm_ops = vma->vm_ops;
  880. radeon_ttm_vm_ops = *ttm_vm_ops;
  881. radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
  882. }
  883. vma->vm_ops = &radeon_ttm_vm_ops;
  884. return 0;
  885. }
  886. #if defined(CONFIG_DEBUG_FS)
  887. static int radeon_mm_dump_table(struct seq_file *m, void *data)
  888. {
  889. struct drm_info_node *node = (struct drm_info_node *)m->private;
  890. unsigned ttm_pl = *(int *)node->info_ent->data;
  891. struct drm_device *dev = node->minor->dev;
  892. struct radeon_device *rdev = dev->dev_private;
  893. struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv;
  894. int ret;
  895. struct ttm_bo_global *glob = rdev->mman.bdev.glob;
  896. spin_lock(&glob->lru_lock);
  897. ret = drm_mm_dump_table(m, mm);
  898. spin_unlock(&glob->lru_lock);
  899. return ret;
  900. }
  901. static int ttm_pl_vram = TTM_PL_VRAM;
  902. static int ttm_pl_tt = TTM_PL_TT;
  903. static struct drm_info_list radeon_ttm_debugfs_list[] = {
  904. {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram},
  905. {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt},
  906. {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
  907. #ifdef CONFIG_SWIOTLB
  908. {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
  909. #endif
  910. };
  911. static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
  912. {
  913. struct radeon_device *rdev = inode->i_private;
  914. i_size_write(inode, rdev->mc.mc_vram_size);
  915. filep->private_data = inode->i_private;
  916. return 0;
  917. }
  918. static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
  919. size_t size, loff_t *pos)
  920. {
  921. struct radeon_device *rdev = f->private_data;
  922. ssize_t result = 0;
  923. int r;
  924. if (size & 0x3 || *pos & 0x3)
  925. return -EINVAL;
  926. while (size) {
  927. unsigned long flags;
  928. uint32_t value;
  929. if (*pos >= rdev->mc.mc_vram_size)
  930. return result;
  931. spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
  932. WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
  933. if (rdev->family >= CHIP_CEDAR)
  934. WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
  935. value = RREG32(RADEON_MM_DATA);
  936. spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
  937. r = put_user(value, (uint32_t *)buf);
  938. if (r)
  939. return r;
  940. result += 4;
  941. buf += 4;
  942. *pos += 4;
  943. size -= 4;
  944. }
  945. return result;
  946. }
  947. static const struct file_operations radeon_ttm_vram_fops = {
  948. .owner = THIS_MODULE,
  949. .open = radeon_ttm_vram_open,
  950. .read = radeon_ttm_vram_read,
  951. .llseek = default_llseek
  952. };
  953. static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
  954. {
  955. struct radeon_device *rdev = inode->i_private;
  956. i_size_write(inode, rdev->mc.gtt_size);
  957. filep->private_data = inode->i_private;
  958. return 0;
  959. }
  960. static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
  961. size_t size, loff_t *pos)
  962. {
  963. struct radeon_device *rdev = f->private_data;
  964. ssize_t result = 0;
  965. int r;
  966. while (size) {
  967. loff_t p = *pos / PAGE_SIZE;
  968. unsigned off = *pos & ~PAGE_MASK;
  969. size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
  970. struct page *page;
  971. void *ptr;
  972. if (p >= rdev->gart.num_cpu_pages)
  973. return result;
  974. page = rdev->gart.pages[p];
  975. if (page) {
  976. ptr = kmap(page);
  977. ptr += off;
  978. r = copy_to_user(buf, ptr, cur_size);
  979. kunmap(rdev->gart.pages[p]);
  980. } else
  981. r = clear_user(buf, cur_size);
  982. if (r)
  983. return -EFAULT;
  984. result += cur_size;
  985. buf += cur_size;
  986. *pos += cur_size;
  987. size -= cur_size;
  988. }
  989. return result;
  990. }
  991. static const struct file_operations radeon_ttm_gtt_fops = {
  992. .owner = THIS_MODULE,
  993. .open = radeon_ttm_gtt_open,
  994. .read = radeon_ttm_gtt_read,
  995. .llseek = default_llseek
  996. };
  997. #endif
  998. static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
  999. {
  1000. #if defined(CONFIG_DEBUG_FS)
  1001. unsigned count;
  1002. struct drm_minor *minor = rdev->ddev->primary;
  1003. struct dentry *ent, *root = minor->debugfs_root;
  1004. ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root,
  1005. rdev, &radeon_ttm_vram_fops);
  1006. if (IS_ERR(ent))
  1007. return PTR_ERR(ent);
  1008. rdev->mman.vram = ent;
  1009. ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root,
  1010. rdev, &radeon_ttm_gtt_fops);
  1011. if (IS_ERR(ent))
  1012. return PTR_ERR(ent);
  1013. rdev->mman.gtt = ent;
  1014. count = ARRAY_SIZE(radeon_ttm_debugfs_list);
  1015. #ifdef CONFIG_SWIOTLB
  1016. if (!swiotlb_nr_tbl())
  1017. --count;
  1018. #endif
  1019. return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count);
  1020. #else
  1021. return 0;
  1022. #endif
  1023. }
  1024. static void radeon_ttm_debugfs_fini(struct radeon_device *rdev)
  1025. {
  1026. #if defined(CONFIG_DEBUG_FS)
  1027. debugfs_remove(rdev->mman.vram);
  1028. rdev->mman.vram = NULL;
  1029. debugfs_remove(rdev->mman.gtt);
  1030. rdev->mman.gtt = NULL;
  1031. #endif
  1032. }