radeon_drv.c 22 KB

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  1. /**
  2. * \file radeon_drv.c
  3. * ATI Radeon driver
  4. *
  5. * \author Gareth Hughes <gareth@valinux.com>
  6. */
  7. /*
  8. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  9. * All Rights Reserved.
  10. *
  11. * Permission is hereby granted, free of charge, to any person obtaining a
  12. * copy of this software and associated documentation files (the "Software"),
  13. * to deal in the Software without restriction, including without limitation
  14. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  15. * and/or sell copies of the Software, and to permit persons to whom the
  16. * Software is furnished to do so, subject to the following conditions:
  17. *
  18. * The above copyright notice and this permission notice (including the next
  19. * paragraph) shall be included in all copies or substantial portions of the
  20. * Software.
  21. *
  22. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  26. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  27. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  28. * OTHER DEALINGS IN THE SOFTWARE.
  29. */
  30. #include <drm/drmP.h>
  31. #include <drm/radeon_drm.h>
  32. #include "radeon_drv.h"
  33. #include <drm/drm_pciids.h>
  34. #include <linux/console.h>
  35. #include <linux/module.h>
  36. #include <linux/pm_runtime.h>
  37. #include <linux/vga_switcheroo.h>
  38. #include <drm/drm_gem.h>
  39. #include "drm_crtc_helper.h"
  40. #include "radeon_kfd.h"
  41. /*
  42. * KMS wrapper.
  43. * - 2.0.0 - initial interface
  44. * - 2.1.0 - add square tiling interface
  45. * - 2.2.0 - add r6xx/r7xx const buffer support
  46. * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
  47. * - 2.4.0 - add crtc id query
  48. * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
  49. * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
  50. * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
  51. * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
  52. * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
  53. * 2.10.0 - fusion 2D tiling
  54. * 2.11.0 - backend map, initial compute support for the CS checker
  55. * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
  56. * 2.13.0 - virtual memory support, streamout
  57. * 2.14.0 - add evergreen tiling informations
  58. * 2.15.0 - add max_pipes query
  59. * 2.16.0 - fix evergreen 2D tiled surface calculation
  60. * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
  61. * 2.18.0 - r600-eg: allow "invalid" DB formats
  62. * 2.19.0 - r600-eg: MSAA textures
  63. * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
  64. * 2.21.0 - r600-r700: FMASK and CMASK
  65. * 2.22.0 - r600 only: RESOLVE_BOX allowed
  66. * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
  67. * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
  68. * 2.25.0 - eg+: new info request for num SE and num SH
  69. * 2.26.0 - r600-eg: fix htile size computation
  70. * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
  71. * 2.28.0 - r600-eg: Add MEM_WRITE packet support
  72. * 2.29.0 - R500 FP16 color clear registers
  73. * 2.30.0 - fix for FMASK texturing
  74. * 2.31.0 - Add fastfb support for rs690
  75. * 2.32.0 - new info request for rings working
  76. * 2.33.0 - Add SI tiling mode array query
  77. * 2.34.0 - Add CIK tiling mode array query
  78. * 2.35.0 - Add CIK macrotile mode array query
  79. * 2.36.0 - Fix CIK DCE tiling setup
  80. * 2.37.0 - allow GS ring setup on r6xx/r7xx
  81. * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
  82. * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
  83. * 2.39.0 - Add INFO query for number of active CUs
  84. * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
  85. * CS to GPU on >= r600
  86. */
  87. #define KMS_DRIVER_MAJOR 2
  88. #define KMS_DRIVER_MINOR 40
  89. #define KMS_DRIVER_PATCHLEVEL 0
  90. int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
  91. int radeon_driver_unload_kms(struct drm_device *dev);
  92. void radeon_driver_lastclose_kms(struct drm_device *dev);
  93. int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
  94. void radeon_driver_postclose_kms(struct drm_device *dev,
  95. struct drm_file *file_priv);
  96. void radeon_driver_preclose_kms(struct drm_device *dev,
  97. struct drm_file *file_priv);
  98. int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
  99. int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
  100. u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc);
  101. int radeon_enable_vblank_kms(struct drm_device *dev, int crtc);
  102. void radeon_disable_vblank_kms(struct drm_device *dev, int crtc);
  103. int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
  104. int *max_error,
  105. struct timeval *vblank_time,
  106. unsigned flags);
  107. void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
  108. int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
  109. void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
  110. irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
  111. void radeon_gem_object_free(struct drm_gem_object *obj);
  112. int radeon_gem_object_open(struct drm_gem_object *obj,
  113. struct drm_file *file_priv);
  114. void radeon_gem_object_close(struct drm_gem_object *obj,
  115. struct drm_file *file_priv);
  116. struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
  117. struct drm_gem_object *gobj,
  118. int flags);
  119. extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
  120. unsigned int flags,
  121. int *vpos, int *hpos, ktime_t *stime,
  122. ktime_t *etime);
  123. extern bool radeon_is_px(struct drm_device *dev);
  124. extern const struct drm_ioctl_desc radeon_ioctls_kms[];
  125. extern int radeon_max_kms_ioctl;
  126. int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
  127. int radeon_mode_dumb_mmap(struct drm_file *filp,
  128. struct drm_device *dev,
  129. uint32_t handle, uint64_t *offset_p);
  130. int radeon_mode_dumb_create(struct drm_file *file_priv,
  131. struct drm_device *dev,
  132. struct drm_mode_create_dumb *args);
  133. struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
  134. struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
  135. struct dma_buf_attachment *,
  136. struct sg_table *sg);
  137. int radeon_gem_prime_pin(struct drm_gem_object *obj);
  138. void radeon_gem_prime_unpin(struct drm_gem_object *obj);
  139. struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *);
  140. void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
  141. void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
  142. extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
  143. unsigned long arg);
  144. #if defined(CONFIG_DEBUG_FS)
  145. int radeon_debugfs_init(struct drm_minor *minor);
  146. void radeon_debugfs_cleanup(struct drm_minor *minor);
  147. #endif
  148. /* atpx handler */
  149. #if defined(CONFIG_VGA_SWITCHEROO)
  150. void radeon_register_atpx_handler(void);
  151. void radeon_unregister_atpx_handler(void);
  152. #else
  153. static inline void radeon_register_atpx_handler(void) {}
  154. static inline void radeon_unregister_atpx_handler(void) {}
  155. #endif
  156. int radeon_no_wb;
  157. int radeon_modeset = -1;
  158. int radeon_dynclks = -1;
  159. int radeon_r4xx_atom = 0;
  160. int radeon_agpmode = 0;
  161. int radeon_vram_limit = 0;
  162. int radeon_gart_size = -1; /* auto */
  163. int radeon_benchmarking = 0;
  164. int radeon_testing = 0;
  165. int radeon_connector_table = 0;
  166. int radeon_tv = 1;
  167. int radeon_audio = -1;
  168. int radeon_disp_priority = 0;
  169. int radeon_hw_i2c = 0;
  170. int radeon_pcie_gen2 = -1;
  171. int radeon_msi = -1;
  172. int radeon_lockup_timeout = 10000;
  173. int radeon_fastfb = 0;
  174. int radeon_dpm = -1;
  175. int radeon_aspm = -1;
  176. int radeon_runtime_pm = -1;
  177. int radeon_hard_reset = 0;
  178. int radeon_vm_size = 8;
  179. int radeon_vm_block_size = -1;
  180. int radeon_deep_color = 0;
  181. int radeon_use_pflipirq = 2;
  182. int radeon_bapm = -1;
  183. int radeon_backlight = -1;
  184. MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
  185. module_param_named(no_wb, radeon_no_wb, int, 0444);
  186. MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
  187. module_param_named(modeset, radeon_modeset, int, 0400);
  188. MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
  189. module_param_named(dynclks, radeon_dynclks, int, 0444);
  190. MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
  191. module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
  192. MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
  193. module_param_named(vramlimit, radeon_vram_limit, int, 0600);
  194. MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
  195. module_param_named(agpmode, radeon_agpmode, int, 0444);
  196. MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
  197. module_param_named(gartsize, radeon_gart_size, int, 0600);
  198. MODULE_PARM_DESC(benchmark, "Run benchmark");
  199. module_param_named(benchmark, radeon_benchmarking, int, 0444);
  200. MODULE_PARM_DESC(test, "Run tests");
  201. module_param_named(test, radeon_testing, int, 0444);
  202. MODULE_PARM_DESC(connector_table, "Force connector table");
  203. module_param_named(connector_table, radeon_connector_table, int, 0444);
  204. MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
  205. module_param_named(tv, radeon_tv, int, 0444);
  206. MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
  207. module_param_named(audio, radeon_audio, int, 0444);
  208. MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
  209. module_param_named(disp_priority, radeon_disp_priority, int, 0444);
  210. MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
  211. module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
  212. MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
  213. module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
  214. MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
  215. module_param_named(msi, radeon_msi, int, 0444);
  216. MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)");
  217. module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
  218. MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
  219. module_param_named(fastfb, radeon_fastfb, int, 0444);
  220. MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
  221. module_param_named(dpm, radeon_dpm, int, 0444);
  222. MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
  223. module_param_named(aspm, radeon_aspm, int, 0444);
  224. MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
  225. module_param_named(runpm, radeon_runtime_pm, int, 0444);
  226. MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
  227. module_param_named(hard_reset, radeon_hard_reset, int, 0444);
  228. MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
  229. module_param_named(vm_size, radeon_vm_size, int, 0444);
  230. MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
  231. module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
  232. MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
  233. module_param_named(deep_color, radeon_deep_color, int, 0444);
  234. MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
  235. module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
  236. MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
  237. module_param_named(bapm, radeon_bapm, int, 0444);
  238. MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
  239. module_param_named(backlight, radeon_backlight, int, 0444);
  240. static struct pci_device_id pciidlist[] = {
  241. radeon_PCI_IDS
  242. };
  243. MODULE_DEVICE_TABLE(pci, pciidlist);
  244. #ifdef CONFIG_DRM_RADEON_UMS
  245. static int radeon_suspend(struct drm_device *dev, pm_message_t state)
  246. {
  247. drm_radeon_private_t *dev_priv = dev->dev_private;
  248. if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  249. return 0;
  250. /* Disable *all* interrupts */
  251. if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
  252. RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
  253. RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
  254. return 0;
  255. }
  256. static int radeon_resume(struct drm_device *dev)
  257. {
  258. drm_radeon_private_t *dev_priv = dev->dev_private;
  259. if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  260. return 0;
  261. /* Restore interrupt registers */
  262. if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
  263. RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
  264. RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
  265. return 0;
  266. }
  267. static const struct file_operations radeon_driver_old_fops = {
  268. .owner = THIS_MODULE,
  269. .open = drm_open,
  270. .release = drm_release,
  271. .unlocked_ioctl = drm_ioctl,
  272. .mmap = drm_legacy_mmap,
  273. .poll = drm_poll,
  274. .read = drm_read,
  275. #ifdef CONFIG_COMPAT
  276. .compat_ioctl = radeon_compat_ioctl,
  277. #endif
  278. .llseek = noop_llseek,
  279. };
  280. static struct drm_driver driver_old = {
  281. .driver_features =
  282. DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
  283. DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED,
  284. .dev_priv_size = sizeof(drm_radeon_buf_priv_t),
  285. .load = radeon_driver_load,
  286. .firstopen = radeon_driver_firstopen,
  287. .open = radeon_driver_open,
  288. .preclose = radeon_driver_preclose,
  289. .postclose = radeon_driver_postclose,
  290. .lastclose = radeon_driver_lastclose,
  291. .set_busid = drm_pci_set_busid,
  292. .unload = radeon_driver_unload,
  293. .suspend = radeon_suspend,
  294. .resume = radeon_resume,
  295. .get_vblank_counter = radeon_get_vblank_counter,
  296. .enable_vblank = radeon_enable_vblank,
  297. .disable_vblank = radeon_disable_vblank,
  298. .master_create = radeon_master_create,
  299. .master_destroy = radeon_master_destroy,
  300. .irq_preinstall = radeon_driver_irq_preinstall,
  301. .irq_postinstall = radeon_driver_irq_postinstall,
  302. .irq_uninstall = radeon_driver_irq_uninstall,
  303. .irq_handler = radeon_driver_irq_handler,
  304. .ioctls = radeon_ioctls,
  305. .dma_ioctl = radeon_cp_buffers,
  306. .fops = &radeon_driver_old_fops,
  307. .name = DRIVER_NAME,
  308. .desc = DRIVER_DESC,
  309. .date = DRIVER_DATE,
  310. .major = DRIVER_MAJOR,
  311. .minor = DRIVER_MINOR,
  312. .patchlevel = DRIVER_PATCHLEVEL,
  313. };
  314. #endif
  315. static struct drm_driver kms_driver;
  316. static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
  317. {
  318. struct apertures_struct *ap;
  319. bool primary = false;
  320. ap = alloc_apertures(1);
  321. if (!ap)
  322. return -ENOMEM;
  323. ap->ranges[0].base = pci_resource_start(pdev, 0);
  324. ap->ranges[0].size = pci_resource_len(pdev, 0);
  325. #ifdef CONFIG_X86
  326. primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
  327. #endif
  328. remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
  329. kfree(ap);
  330. return 0;
  331. }
  332. static int radeon_pci_probe(struct pci_dev *pdev,
  333. const struct pci_device_id *ent)
  334. {
  335. int ret;
  336. /* Get rid of things like offb */
  337. ret = radeon_kick_out_firmware_fb(pdev);
  338. if (ret)
  339. return ret;
  340. return drm_get_pci_dev(pdev, ent, &kms_driver);
  341. }
  342. static void
  343. radeon_pci_remove(struct pci_dev *pdev)
  344. {
  345. struct drm_device *dev = pci_get_drvdata(pdev);
  346. drm_put_dev(dev);
  347. }
  348. static int radeon_pmops_suspend(struct device *dev)
  349. {
  350. struct pci_dev *pdev = to_pci_dev(dev);
  351. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  352. return radeon_suspend_kms(drm_dev, true, true);
  353. }
  354. static int radeon_pmops_resume(struct device *dev)
  355. {
  356. struct pci_dev *pdev = to_pci_dev(dev);
  357. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  358. return radeon_resume_kms(drm_dev, true, true);
  359. }
  360. static int radeon_pmops_freeze(struct device *dev)
  361. {
  362. struct pci_dev *pdev = to_pci_dev(dev);
  363. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  364. return radeon_suspend_kms(drm_dev, false, true);
  365. }
  366. static int radeon_pmops_thaw(struct device *dev)
  367. {
  368. struct pci_dev *pdev = to_pci_dev(dev);
  369. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  370. return radeon_resume_kms(drm_dev, false, true);
  371. }
  372. static int radeon_pmops_runtime_suspend(struct device *dev)
  373. {
  374. struct pci_dev *pdev = to_pci_dev(dev);
  375. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  376. int ret;
  377. if (!radeon_is_px(drm_dev)) {
  378. pm_runtime_forbid(dev);
  379. return -EBUSY;
  380. }
  381. drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
  382. drm_kms_helper_poll_disable(drm_dev);
  383. vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
  384. ret = radeon_suspend_kms(drm_dev, false, false);
  385. pci_save_state(pdev);
  386. pci_disable_device(pdev);
  387. pci_ignore_hotplug(pdev);
  388. pci_set_power_state(pdev, PCI_D3cold);
  389. drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
  390. return 0;
  391. }
  392. static int radeon_pmops_runtime_resume(struct device *dev)
  393. {
  394. struct pci_dev *pdev = to_pci_dev(dev);
  395. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  396. int ret;
  397. if (!radeon_is_px(drm_dev))
  398. return -EINVAL;
  399. drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
  400. pci_set_power_state(pdev, PCI_D0);
  401. pci_restore_state(pdev);
  402. ret = pci_enable_device(pdev);
  403. if (ret)
  404. return ret;
  405. pci_set_master(pdev);
  406. ret = radeon_resume_kms(drm_dev, false, false);
  407. drm_kms_helper_poll_enable(drm_dev);
  408. vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
  409. drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
  410. return 0;
  411. }
  412. static int radeon_pmops_runtime_idle(struct device *dev)
  413. {
  414. struct pci_dev *pdev = to_pci_dev(dev);
  415. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  416. struct drm_crtc *crtc;
  417. if (!radeon_is_px(drm_dev)) {
  418. pm_runtime_forbid(dev);
  419. return -EBUSY;
  420. }
  421. list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
  422. if (crtc->enabled) {
  423. DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
  424. return -EBUSY;
  425. }
  426. }
  427. pm_runtime_mark_last_busy(dev);
  428. pm_runtime_autosuspend(dev);
  429. /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
  430. return 1;
  431. }
  432. long radeon_drm_ioctl(struct file *filp,
  433. unsigned int cmd, unsigned long arg)
  434. {
  435. struct drm_file *file_priv = filp->private_data;
  436. struct drm_device *dev;
  437. long ret;
  438. dev = file_priv->minor->dev;
  439. ret = pm_runtime_get_sync(dev->dev);
  440. if (ret < 0)
  441. return ret;
  442. ret = drm_ioctl(filp, cmd, arg);
  443. pm_runtime_mark_last_busy(dev->dev);
  444. pm_runtime_put_autosuspend(dev->dev);
  445. return ret;
  446. }
  447. static const struct dev_pm_ops radeon_pm_ops = {
  448. .suspend = radeon_pmops_suspend,
  449. .resume = radeon_pmops_resume,
  450. .freeze = radeon_pmops_freeze,
  451. .thaw = radeon_pmops_thaw,
  452. .poweroff = radeon_pmops_freeze,
  453. .restore = radeon_pmops_resume,
  454. .runtime_suspend = radeon_pmops_runtime_suspend,
  455. .runtime_resume = radeon_pmops_runtime_resume,
  456. .runtime_idle = radeon_pmops_runtime_idle,
  457. };
  458. static const struct file_operations radeon_driver_kms_fops = {
  459. .owner = THIS_MODULE,
  460. .open = drm_open,
  461. .release = drm_release,
  462. .unlocked_ioctl = radeon_drm_ioctl,
  463. .mmap = radeon_mmap,
  464. .poll = drm_poll,
  465. .read = drm_read,
  466. #ifdef CONFIG_COMPAT
  467. .compat_ioctl = radeon_kms_compat_ioctl,
  468. #endif
  469. };
  470. static struct drm_driver kms_driver = {
  471. .driver_features =
  472. DRIVER_USE_AGP |
  473. DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
  474. DRIVER_PRIME | DRIVER_RENDER,
  475. .load = radeon_driver_load_kms,
  476. .open = radeon_driver_open_kms,
  477. .preclose = radeon_driver_preclose_kms,
  478. .postclose = radeon_driver_postclose_kms,
  479. .lastclose = radeon_driver_lastclose_kms,
  480. .set_busid = drm_pci_set_busid,
  481. .unload = radeon_driver_unload_kms,
  482. .get_vblank_counter = radeon_get_vblank_counter_kms,
  483. .enable_vblank = radeon_enable_vblank_kms,
  484. .disable_vblank = radeon_disable_vblank_kms,
  485. .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
  486. .get_scanout_position = radeon_get_crtc_scanoutpos,
  487. #if defined(CONFIG_DEBUG_FS)
  488. .debugfs_init = radeon_debugfs_init,
  489. .debugfs_cleanup = radeon_debugfs_cleanup,
  490. #endif
  491. .irq_preinstall = radeon_driver_irq_preinstall_kms,
  492. .irq_postinstall = radeon_driver_irq_postinstall_kms,
  493. .irq_uninstall = radeon_driver_irq_uninstall_kms,
  494. .irq_handler = radeon_driver_irq_handler_kms,
  495. .ioctls = radeon_ioctls_kms,
  496. .gem_free_object = radeon_gem_object_free,
  497. .gem_open_object = radeon_gem_object_open,
  498. .gem_close_object = radeon_gem_object_close,
  499. .dumb_create = radeon_mode_dumb_create,
  500. .dumb_map_offset = radeon_mode_dumb_mmap,
  501. .dumb_destroy = drm_gem_dumb_destroy,
  502. .fops = &radeon_driver_kms_fops,
  503. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  504. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  505. .gem_prime_export = radeon_gem_prime_export,
  506. .gem_prime_import = drm_gem_prime_import,
  507. .gem_prime_pin = radeon_gem_prime_pin,
  508. .gem_prime_unpin = radeon_gem_prime_unpin,
  509. .gem_prime_res_obj = radeon_gem_prime_res_obj,
  510. .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
  511. .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
  512. .gem_prime_vmap = radeon_gem_prime_vmap,
  513. .gem_prime_vunmap = radeon_gem_prime_vunmap,
  514. .name = DRIVER_NAME,
  515. .desc = DRIVER_DESC,
  516. .date = DRIVER_DATE,
  517. .major = KMS_DRIVER_MAJOR,
  518. .minor = KMS_DRIVER_MINOR,
  519. .patchlevel = KMS_DRIVER_PATCHLEVEL,
  520. };
  521. static struct drm_driver *driver;
  522. static struct pci_driver *pdriver;
  523. #ifdef CONFIG_DRM_RADEON_UMS
  524. static struct pci_driver radeon_pci_driver = {
  525. .name = DRIVER_NAME,
  526. .id_table = pciidlist,
  527. };
  528. #endif
  529. static struct pci_driver radeon_kms_pci_driver = {
  530. .name = DRIVER_NAME,
  531. .id_table = pciidlist,
  532. .probe = radeon_pci_probe,
  533. .remove = radeon_pci_remove,
  534. .driver.pm = &radeon_pm_ops,
  535. };
  536. static int __init radeon_init(void)
  537. {
  538. #ifdef CONFIG_VGA_CONSOLE
  539. if (vgacon_text_force() && radeon_modeset == -1) {
  540. DRM_INFO("VGACON disable radeon kernel modesetting.\n");
  541. radeon_modeset = 0;
  542. }
  543. #endif
  544. /* set to modesetting by default if not nomodeset */
  545. if (radeon_modeset == -1)
  546. radeon_modeset = 1;
  547. if (radeon_modeset == 1) {
  548. DRM_INFO("radeon kernel modesetting enabled.\n");
  549. driver = &kms_driver;
  550. pdriver = &radeon_kms_pci_driver;
  551. driver->driver_features |= DRIVER_MODESET;
  552. driver->num_ioctls = radeon_max_kms_ioctl;
  553. radeon_register_atpx_handler();
  554. } else {
  555. #ifdef CONFIG_DRM_RADEON_UMS
  556. DRM_INFO("radeon userspace modesetting enabled.\n");
  557. driver = &driver_old;
  558. pdriver = &radeon_pci_driver;
  559. driver->driver_features &= ~DRIVER_MODESET;
  560. driver->num_ioctls = radeon_max_ioctl;
  561. #else
  562. DRM_ERROR("No UMS support in radeon module!\n");
  563. return -EINVAL;
  564. #endif
  565. }
  566. radeon_kfd_init();
  567. /* let modprobe override vga console setting */
  568. return drm_pci_init(driver, pdriver);
  569. }
  570. static void __exit radeon_exit(void)
  571. {
  572. radeon_kfd_fini();
  573. drm_pci_exit(driver, pdriver);
  574. radeon_unregister_atpx_handler();
  575. }
  576. module_init(radeon_init);
  577. module_exit(radeon_exit);
  578. MODULE_AUTHOR(DRIVER_AUTHOR);
  579. MODULE_DESCRIPTION(DRIVER_DESC);
  580. MODULE_LICENSE("GPL and additional rights");