intel_runtime_pm.c 41 KB

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  1. /*
  2. * Copyright © 2012-2014 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eugeni Dodonov <eugeni.dodonov@intel.com>
  25. * Daniel Vetter <daniel.vetter@ffwll.ch>
  26. *
  27. */
  28. #include <linux/pm_runtime.h>
  29. #include <linux/vgaarb.h>
  30. #include "i915_drv.h"
  31. #include "intel_drv.h"
  32. #include <drm/i915_powerwell.h>
  33. /**
  34. * DOC: runtime pm
  35. *
  36. * The i915 driver supports dynamic enabling and disabling of entire hardware
  37. * blocks at runtime. This is especially important on the display side where
  38. * software is supposed to control many power gates manually on recent hardware,
  39. * since on the GT side a lot of the power management is done by the hardware.
  40. * But even there some manual control at the device level is required.
  41. *
  42. * Since i915 supports a diverse set of platforms with a unified codebase and
  43. * hardware engineers just love to shuffle functionality around between power
  44. * domains there's a sizeable amount of indirection required. This file provides
  45. * generic functions to the driver for grabbing and releasing references for
  46. * abstract power domains. It then maps those to the actual power wells
  47. * present for a given platform.
  48. */
  49. static struct i915_power_domains *hsw_pwr;
  50. #define for_each_power_well(i, power_well, domain_mask, power_domains) \
  51. for (i = 0; \
  52. i < (power_domains)->power_well_count && \
  53. ((power_well) = &(power_domains)->power_wells[i]); \
  54. i++) \
  55. if ((power_well)->domains & (domain_mask))
  56. #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  57. for (i = (power_domains)->power_well_count - 1; \
  58. i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  59. i--) \
  60. if ((power_well)->domains & (domain_mask))
  61. /*
  62. * We should only use the power well if we explicitly asked the hardware to
  63. * enable it, so check if it's enabled and also check if we've requested it to
  64. * be enabled.
  65. */
  66. static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
  67. struct i915_power_well *power_well)
  68. {
  69. return I915_READ(HSW_PWR_WELL_DRIVER) ==
  70. (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
  71. }
  72. /**
  73. * __intel_display_power_is_enabled - unlocked check for a power domain
  74. * @dev_priv: i915 device instance
  75. * @domain: power domain to check
  76. *
  77. * This is the unlocked version of intel_display_power_is_enabled() and should
  78. * only be used from error capture and recovery code where deadlocks are
  79. * possible.
  80. *
  81. * Returns:
  82. * True when the power domain is enabled, false otherwise.
  83. */
  84. bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
  85. enum intel_display_power_domain domain)
  86. {
  87. struct i915_power_domains *power_domains;
  88. struct i915_power_well *power_well;
  89. bool is_enabled;
  90. int i;
  91. if (dev_priv->pm.suspended)
  92. return false;
  93. power_domains = &dev_priv->power_domains;
  94. is_enabled = true;
  95. for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
  96. if (power_well->always_on)
  97. continue;
  98. if (!power_well->hw_enabled) {
  99. is_enabled = false;
  100. break;
  101. }
  102. }
  103. return is_enabled;
  104. }
  105. /**
  106. * intel_display_power_is_enabled - unlocked check for a power domain
  107. * @dev_priv: i915 device instance
  108. * @domain: power domain to check
  109. *
  110. * This function can be used to check the hw power domain state. It is mostly
  111. * used in hardware state readout functions. Everywhere else code should rely
  112. * upon explicit power domain reference counting to ensure that the hardware
  113. * block is powered up before accessing it.
  114. *
  115. * Callers must hold the relevant modesetting locks to ensure that concurrent
  116. * threads can't disable the power well while the caller tries to read a few
  117. * registers.
  118. *
  119. * Returns:
  120. * True when the power domain is enabled, false otherwise.
  121. */
  122. bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
  123. enum intel_display_power_domain domain)
  124. {
  125. struct i915_power_domains *power_domains;
  126. bool ret;
  127. power_domains = &dev_priv->power_domains;
  128. mutex_lock(&power_domains->lock);
  129. ret = __intel_display_power_is_enabled(dev_priv, domain);
  130. mutex_unlock(&power_domains->lock);
  131. return ret;
  132. }
  133. /**
  134. * intel_display_set_init_power - set the initial power domain state
  135. * @dev_priv: i915 device instance
  136. * @enable: whether to enable or disable the initial power domain state
  137. *
  138. * For simplicity our driver load/unload and system suspend/resume code assumes
  139. * that all power domains are always enabled. This functions controls the state
  140. * of this little hack. While the initial power domain state is enabled runtime
  141. * pm is effectively disabled.
  142. */
  143. void intel_display_set_init_power(struct drm_i915_private *dev_priv,
  144. bool enable)
  145. {
  146. if (dev_priv->power_domains.init_power_on == enable)
  147. return;
  148. if (enable)
  149. intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
  150. else
  151. intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
  152. dev_priv->power_domains.init_power_on = enable;
  153. }
  154. /*
  155. * Starting with Haswell, we have a "Power Down Well" that can be turned off
  156. * when not needed anymore. We have 4 registers that can request the power well
  157. * to be enabled, and it will only be disabled if none of the registers is
  158. * requesting it to be enabled.
  159. */
  160. static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
  161. {
  162. struct drm_device *dev = dev_priv->dev;
  163. /*
  164. * After we re-enable the power well, if we touch VGA register 0x3d5
  165. * we'll get unclaimed register interrupts. This stops after we write
  166. * anything to the VGA MSR register. The vgacon module uses this
  167. * register all the time, so if we unbind our driver and, as a
  168. * consequence, bind vgacon, we'll get stuck in an infinite loop at
  169. * console_unlock(). So make here we touch the VGA MSR register, making
  170. * sure vgacon can keep working normally without triggering interrupts
  171. * and error messages.
  172. */
  173. vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  174. outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
  175. vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  176. if (IS_BROADWELL(dev) || (INTEL_INFO(dev)->gen >= 9))
  177. gen8_irq_power_well_post_enable(dev_priv);
  178. }
  179. static void hsw_set_power_well(struct drm_i915_private *dev_priv,
  180. struct i915_power_well *power_well, bool enable)
  181. {
  182. bool is_enabled, enable_requested;
  183. uint32_t tmp;
  184. tmp = I915_READ(HSW_PWR_WELL_DRIVER);
  185. is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
  186. enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
  187. if (enable) {
  188. if (!enable_requested)
  189. I915_WRITE(HSW_PWR_WELL_DRIVER,
  190. HSW_PWR_WELL_ENABLE_REQUEST);
  191. if (!is_enabled) {
  192. DRM_DEBUG_KMS("Enabling power well\n");
  193. if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
  194. HSW_PWR_WELL_STATE_ENABLED), 20))
  195. DRM_ERROR("Timeout enabling power well\n");
  196. hsw_power_well_post_enable(dev_priv);
  197. }
  198. } else {
  199. if (enable_requested) {
  200. I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
  201. POSTING_READ(HSW_PWR_WELL_DRIVER);
  202. DRM_DEBUG_KMS("Requesting to disable the power well\n");
  203. }
  204. }
  205. }
  206. static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
  207. struct i915_power_well *power_well)
  208. {
  209. hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
  210. /*
  211. * We're taking over the BIOS, so clear any requests made by it since
  212. * the driver is in charge now.
  213. */
  214. if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
  215. I915_WRITE(HSW_PWR_WELL_BIOS, 0);
  216. }
  217. static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
  218. struct i915_power_well *power_well)
  219. {
  220. hsw_set_power_well(dev_priv, power_well, true);
  221. }
  222. static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
  223. struct i915_power_well *power_well)
  224. {
  225. hsw_set_power_well(dev_priv, power_well, false);
  226. }
  227. static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
  228. struct i915_power_well *power_well)
  229. {
  230. }
  231. static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
  232. struct i915_power_well *power_well)
  233. {
  234. return true;
  235. }
  236. static void vlv_set_power_well(struct drm_i915_private *dev_priv,
  237. struct i915_power_well *power_well, bool enable)
  238. {
  239. enum punit_power_well power_well_id = power_well->data;
  240. u32 mask;
  241. u32 state;
  242. u32 ctrl;
  243. mask = PUNIT_PWRGT_MASK(power_well_id);
  244. state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
  245. PUNIT_PWRGT_PWR_GATE(power_well_id);
  246. mutex_lock(&dev_priv->rps.hw_lock);
  247. #define COND \
  248. ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
  249. if (COND)
  250. goto out;
  251. ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
  252. ctrl &= ~mask;
  253. ctrl |= state;
  254. vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
  255. if (wait_for(COND, 100))
  256. DRM_ERROR("timout setting power well state %08x (%08x)\n",
  257. state,
  258. vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
  259. #undef COND
  260. out:
  261. mutex_unlock(&dev_priv->rps.hw_lock);
  262. }
  263. static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
  264. struct i915_power_well *power_well)
  265. {
  266. vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
  267. }
  268. static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
  269. struct i915_power_well *power_well)
  270. {
  271. vlv_set_power_well(dev_priv, power_well, true);
  272. }
  273. static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
  274. struct i915_power_well *power_well)
  275. {
  276. vlv_set_power_well(dev_priv, power_well, false);
  277. }
  278. static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
  279. struct i915_power_well *power_well)
  280. {
  281. int power_well_id = power_well->data;
  282. bool enabled = false;
  283. u32 mask;
  284. u32 state;
  285. u32 ctrl;
  286. mask = PUNIT_PWRGT_MASK(power_well_id);
  287. ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
  288. mutex_lock(&dev_priv->rps.hw_lock);
  289. state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
  290. /*
  291. * We only ever set the power-on and power-gate states, anything
  292. * else is unexpected.
  293. */
  294. WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
  295. state != PUNIT_PWRGT_PWR_GATE(power_well_id));
  296. if (state == ctrl)
  297. enabled = true;
  298. /*
  299. * A transient state at this point would mean some unexpected party
  300. * is poking at the power controls too.
  301. */
  302. ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
  303. WARN_ON(ctrl != state);
  304. mutex_unlock(&dev_priv->rps.hw_lock);
  305. return enabled;
  306. }
  307. static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
  308. struct i915_power_well *power_well)
  309. {
  310. WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
  311. vlv_set_power_well(dev_priv, power_well, true);
  312. spin_lock_irq(&dev_priv->irq_lock);
  313. valleyview_enable_display_irqs(dev_priv);
  314. spin_unlock_irq(&dev_priv->irq_lock);
  315. /*
  316. * During driver initialization/resume we can avoid restoring the
  317. * part of the HW/SW state that will be inited anyway explicitly.
  318. */
  319. if (dev_priv->power_domains.initializing)
  320. return;
  321. intel_hpd_init(dev_priv);
  322. i915_redisable_vga_power_on(dev_priv->dev);
  323. }
  324. static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
  325. struct i915_power_well *power_well)
  326. {
  327. WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
  328. spin_lock_irq(&dev_priv->irq_lock);
  329. valleyview_disable_display_irqs(dev_priv);
  330. spin_unlock_irq(&dev_priv->irq_lock);
  331. vlv_set_power_well(dev_priv, power_well, false);
  332. vlv_power_sequencer_reset(dev_priv);
  333. }
  334. static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
  335. struct i915_power_well *power_well)
  336. {
  337. WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
  338. /*
  339. * Enable the CRI clock source so we can get at the
  340. * display and the reference clock for VGA
  341. * hotplug / manual detection.
  342. */
  343. I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
  344. DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
  345. udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
  346. vlv_set_power_well(dev_priv, power_well, true);
  347. /*
  348. * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
  349. * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
  350. * a. GUnit 0x2110 bit[0] set to 1 (def 0)
  351. * b. The other bits such as sfr settings / modesel may all
  352. * be set to 0.
  353. *
  354. * This should only be done on init and resume from S3 with
  355. * both PLLs disabled, or we risk losing DPIO and PLL
  356. * synchronization.
  357. */
  358. I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
  359. }
  360. static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
  361. struct i915_power_well *power_well)
  362. {
  363. enum pipe pipe;
  364. WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
  365. for_each_pipe(dev_priv, pipe)
  366. assert_pll_disabled(dev_priv, pipe);
  367. /* Assert common reset */
  368. I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
  369. vlv_set_power_well(dev_priv, power_well, false);
  370. }
  371. static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
  372. struct i915_power_well *power_well)
  373. {
  374. enum dpio_phy phy;
  375. WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
  376. power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
  377. /*
  378. * Enable the CRI clock source so we can get at the
  379. * display and the reference clock for VGA
  380. * hotplug / manual detection.
  381. */
  382. if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
  383. phy = DPIO_PHY0;
  384. I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
  385. DPLL_REFA_CLK_ENABLE_VLV);
  386. I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
  387. DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
  388. } else {
  389. phy = DPIO_PHY1;
  390. I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
  391. DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
  392. }
  393. udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
  394. vlv_set_power_well(dev_priv, power_well, true);
  395. /* Poll for phypwrgood signal */
  396. if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
  397. DRM_ERROR("Display PHY %d is not power up\n", phy);
  398. I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) |
  399. PHY_COM_LANE_RESET_DEASSERT(phy));
  400. }
  401. static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
  402. struct i915_power_well *power_well)
  403. {
  404. enum dpio_phy phy;
  405. WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
  406. power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
  407. if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
  408. phy = DPIO_PHY0;
  409. assert_pll_disabled(dev_priv, PIPE_A);
  410. assert_pll_disabled(dev_priv, PIPE_B);
  411. } else {
  412. phy = DPIO_PHY1;
  413. assert_pll_disabled(dev_priv, PIPE_C);
  414. }
  415. I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) &
  416. ~PHY_COM_LANE_RESET_DEASSERT(phy));
  417. vlv_set_power_well(dev_priv, power_well, false);
  418. }
  419. static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
  420. struct i915_power_well *power_well)
  421. {
  422. enum pipe pipe = power_well->data;
  423. bool enabled;
  424. u32 state, ctrl;
  425. mutex_lock(&dev_priv->rps.hw_lock);
  426. state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
  427. /*
  428. * We only ever set the power-on and power-gate states, anything
  429. * else is unexpected.
  430. */
  431. WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
  432. enabled = state == DP_SSS_PWR_ON(pipe);
  433. /*
  434. * A transient state at this point would mean some unexpected party
  435. * is poking at the power controls too.
  436. */
  437. ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
  438. WARN_ON(ctrl << 16 != state);
  439. mutex_unlock(&dev_priv->rps.hw_lock);
  440. return enabled;
  441. }
  442. static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
  443. struct i915_power_well *power_well,
  444. bool enable)
  445. {
  446. enum pipe pipe = power_well->data;
  447. u32 state;
  448. u32 ctrl;
  449. state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
  450. mutex_lock(&dev_priv->rps.hw_lock);
  451. #define COND \
  452. ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
  453. if (COND)
  454. goto out;
  455. ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
  456. ctrl &= ~DP_SSC_MASK(pipe);
  457. ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
  458. vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
  459. if (wait_for(COND, 100))
  460. DRM_ERROR("timout setting power well state %08x (%08x)\n",
  461. state,
  462. vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
  463. #undef COND
  464. out:
  465. mutex_unlock(&dev_priv->rps.hw_lock);
  466. }
  467. static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
  468. struct i915_power_well *power_well)
  469. {
  470. chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
  471. }
  472. static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
  473. struct i915_power_well *power_well)
  474. {
  475. WARN_ON_ONCE(power_well->data != PIPE_A &&
  476. power_well->data != PIPE_B &&
  477. power_well->data != PIPE_C);
  478. chv_set_pipe_power_well(dev_priv, power_well, true);
  479. if (power_well->data == PIPE_A) {
  480. spin_lock_irq(&dev_priv->irq_lock);
  481. valleyview_enable_display_irqs(dev_priv);
  482. spin_unlock_irq(&dev_priv->irq_lock);
  483. /*
  484. * During driver initialization/resume we can avoid restoring the
  485. * part of the HW/SW state that will be inited anyway explicitly.
  486. */
  487. if (dev_priv->power_domains.initializing)
  488. return;
  489. intel_hpd_init(dev_priv);
  490. i915_redisable_vga_power_on(dev_priv->dev);
  491. }
  492. }
  493. static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
  494. struct i915_power_well *power_well)
  495. {
  496. WARN_ON_ONCE(power_well->data != PIPE_A &&
  497. power_well->data != PIPE_B &&
  498. power_well->data != PIPE_C);
  499. if (power_well->data == PIPE_A) {
  500. spin_lock_irq(&dev_priv->irq_lock);
  501. valleyview_disable_display_irqs(dev_priv);
  502. spin_unlock_irq(&dev_priv->irq_lock);
  503. }
  504. chv_set_pipe_power_well(dev_priv, power_well, false);
  505. if (power_well->data == PIPE_A)
  506. vlv_power_sequencer_reset(dev_priv);
  507. }
  508. static void check_power_well_state(struct drm_i915_private *dev_priv,
  509. struct i915_power_well *power_well)
  510. {
  511. bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
  512. if (power_well->always_on || !i915.disable_power_well) {
  513. if (!enabled)
  514. goto mismatch;
  515. return;
  516. }
  517. if (enabled != (power_well->count > 0))
  518. goto mismatch;
  519. return;
  520. mismatch:
  521. WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
  522. power_well->name, power_well->always_on, enabled,
  523. power_well->count, i915.disable_power_well);
  524. }
  525. /**
  526. * intel_display_power_get - grab a power domain reference
  527. * @dev_priv: i915 device instance
  528. * @domain: power domain to reference
  529. *
  530. * This function grabs a power domain reference for @domain and ensures that the
  531. * power domain and all its parents are powered up. Therefore users should only
  532. * grab a reference to the innermost power domain they need.
  533. *
  534. * Any power domain reference obtained by this function must have a symmetric
  535. * call to intel_display_power_put() to release the reference again.
  536. */
  537. void intel_display_power_get(struct drm_i915_private *dev_priv,
  538. enum intel_display_power_domain domain)
  539. {
  540. struct i915_power_domains *power_domains;
  541. struct i915_power_well *power_well;
  542. int i;
  543. intel_runtime_pm_get(dev_priv);
  544. power_domains = &dev_priv->power_domains;
  545. mutex_lock(&power_domains->lock);
  546. for_each_power_well(i, power_well, BIT(domain), power_domains) {
  547. if (!power_well->count++) {
  548. DRM_DEBUG_KMS("enabling %s\n", power_well->name);
  549. power_well->ops->enable(dev_priv, power_well);
  550. power_well->hw_enabled = true;
  551. }
  552. check_power_well_state(dev_priv, power_well);
  553. }
  554. power_domains->domain_use_count[domain]++;
  555. mutex_unlock(&power_domains->lock);
  556. }
  557. /**
  558. * intel_display_power_put - release a power domain reference
  559. * @dev_priv: i915 device instance
  560. * @domain: power domain to reference
  561. *
  562. * This function drops the power domain reference obtained by
  563. * intel_display_power_get() and might power down the corresponding hardware
  564. * block right away if this is the last reference.
  565. */
  566. void intel_display_power_put(struct drm_i915_private *dev_priv,
  567. enum intel_display_power_domain domain)
  568. {
  569. struct i915_power_domains *power_domains;
  570. struct i915_power_well *power_well;
  571. int i;
  572. power_domains = &dev_priv->power_domains;
  573. mutex_lock(&power_domains->lock);
  574. WARN_ON(!power_domains->domain_use_count[domain]);
  575. power_domains->domain_use_count[domain]--;
  576. for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
  577. WARN_ON(!power_well->count);
  578. if (!--power_well->count && i915.disable_power_well) {
  579. DRM_DEBUG_KMS("disabling %s\n", power_well->name);
  580. power_well->hw_enabled = false;
  581. power_well->ops->disable(dev_priv, power_well);
  582. }
  583. check_power_well_state(dev_priv, power_well);
  584. }
  585. mutex_unlock(&power_domains->lock);
  586. intel_runtime_pm_put(dev_priv);
  587. }
  588. #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
  589. #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
  590. BIT(POWER_DOMAIN_PIPE_A) | \
  591. BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
  592. BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
  593. BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
  594. BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
  595. BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
  596. BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
  597. BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
  598. BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
  599. BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
  600. BIT(POWER_DOMAIN_PORT_CRT) | \
  601. BIT(POWER_DOMAIN_PLLS) | \
  602. BIT(POWER_DOMAIN_INIT))
  603. #define HSW_DISPLAY_POWER_DOMAINS ( \
  604. (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
  605. BIT(POWER_DOMAIN_INIT))
  606. #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
  607. HSW_ALWAYS_ON_POWER_DOMAINS | \
  608. BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
  609. #define BDW_DISPLAY_POWER_DOMAINS ( \
  610. (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
  611. BIT(POWER_DOMAIN_INIT))
  612. #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
  613. #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
  614. #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
  615. BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
  616. BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
  617. BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
  618. BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
  619. BIT(POWER_DOMAIN_PORT_CRT) | \
  620. BIT(POWER_DOMAIN_INIT))
  621. #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
  622. BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
  623. BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
  624. BIT(POWER_DOMAIN_INIT))
  625. #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
  626. BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
  627. BIT(POWER_DOMAIN_INIT))
  628. #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
  629. BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
  630. BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
  631. BIT(POWER_DOMAIN_INIT))
  632. #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
  633. BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
  634. BIT(POWER_DOMAIN_INIT))
  635. #define CHV_PIPE_A_POWER_DOMAINS ( \
  636. BIT(POWER_DOMAIN_PIPE_A) | \
  637. BIT(POWER_DOMAIN_INIT))
  638. #define CHV_PIPE_B_POWER_DOMAINS ( \
  639. BIT(POWER_DOMAIN_PIPE_B) | \
  640. BIT(POWER_DOMAIN_INIT))
  641. #define CHV_PIPE_C_POWER_DOMAINS ( \
  642. BIT(POWER_DOMAIN_PIPE_C) | \
  643. BIT(POWER_DOMAIN_INIT))
  644. #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
  645. BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
  646. BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
  647. BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
  648. BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
  649. BIT(POWER_DOMAIN_INIT))
  650. #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
  651. BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
  652. BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
  653. BIT(POWER_DOMAIN_INIT))
  654. #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
  655. BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
  656. BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
  657. BIT(POWER_DOMAIN_INIT))
  658. #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
  659. BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
  660. BIT(POWER_DOMAIN_INIT))
  661. static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
  662. .sync_hw = i9xx_always_on_power_well_noop,
  663. .enable = i9xx_always_on_power_well_noop,
  664. .disable = i9xx_always_on_power_well_noop,
  665. .is_enabled = i9xx_always_on_power_well_enabled,
  666. };
  667. static const struct i915_power_well_ops chv_pipe_power_well_ops = {
  668. .sync_hw = chv_pipe_power_well_sync_hw,
  669. .enable = chv_pipe_power_well_enable,
  670. .disable = chv_pipe_power_well_disable,
  671. .is_enabled = chv_pipe_power_well_enabled,
  672. };
  673. static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
  674. .sync_hw = vlv_power_well_sync_hw,
  675. .enable = chv_dpio_cmn_power_well_enable,
  676. .disable = chv_dpio_cmn_power_well_disable,
  677. .is_enabled = vlv_power_well_enabled,
  678. };
  679. static struct i915_power_well i9xx_always_on_power_well[] = {
  680. {
  681. .name = "always-on",
  682. .always_on = 1,
  683. .domains = POWER_DOMAIN_MASK,
  684. .ops = &i9xx_always_on_power_well_ops,
  685. },
  686. };
  687. static const struct i915_power_well_ops hsw_power_well_ops = {
  688. .sync_hw = hsw_power_well_sync_hw,
  689. .enable = hsw_power_well_enable,
  690. .disable = hsw_power_well_disable,
  691. .is_enabled = hsw_power_well_enabled,
  692. };
  693. static struct i915_power_well hsw_power_wells[] = {
  694. {
  695. .name = "always-on",
  696. .always_on = 1,
  697. .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
  698. .ops = &i9xx_always_on_power_well_ops,
  699. },
  700. {
  701. .name = "display",
  702. .domains = HSW_DISPLAY_POWER_DOMAINS,
  703. .ops = &hsw_power_well_ops,
  704. },
  705. };
  706. static struct i915_power_well bdw_power_wells[] = {
  707. {
  708. .name = "always-on",
  709. .always_on = 1,
  710. .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
  711. .ops = &i9xx_always_on_power_well_ops,
  712. },
  713. {
  714. .name = "display",
  715. .domains = BDW_DISPLAY_POWER_DOMAINS,
  716. .ops = &hsw_power_well_ops,
  717. },
  718. };
  719. static const struct i915_power_well_ops vlv_display_power_well_ops = {
  720. .sync_hw = vlv_power_well_sync_hw,
  721. .enable = vlv_display_power_well_enable,
  722. .disable = vlv_display_power_well_disable,
  723. .is_enabled = vlv_power_well_enabled,
  724. };
  725. static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
  726. .sync_hw = vlv_power_well_sync_hw,
  727. .enable = vlv_dpio_cmn_power_well_enable,
  728. .disable = vlv_dpio_cmn_power_well_disable,
  729. .is_enabled = vlv_power_well_enabled,
  730. };
  731. static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
  732. .sync_hw = vlv_power_well_sync_hw,
  733. .enable = vlv_power_well_enable,
  734. .disable = vlv_power_well_disable,
  735. .is_enabled = vlv_power_well_enabled,
  736. };
  737. static struct i915_power_well vlv_power_wells[] = {
  738. {
  739. .name = "always-on",
  740. .always_on = 1,
  741. .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
  742. .ops = &i9xx_always_on_power_well_ops,
  743. },
  744. {
  745. .name = "display",
  746. .domains = VLV_DISPLAY_POWER_DOMAINS,
  747. .data = PUNIT_POWER_WELL_DISP2D,
  748. .ops = &vlv_display_power_well_ops,
  749. },
  750. {
  751. .name = "dpio-tx-b-01",
  752. .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
  753. VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
  754. VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
  755. VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
  756. .ops = &vlv_dpio_power_well_ops,
  757. .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
  758. },
  759. {
  760. .name = "dpio-tx-b-23",
  761. .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
  762. VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
  763. VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
  764. VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
  765. .ops = &vlv_dpio_power_well_ops,
  766. .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
  767. },
  768. {
  769. .name = "dpio-tx-c-01",
  770. .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
  771. VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
  772. VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
  773. VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
  774. .ops = &vlv_dpio_power_well_ops,
  775. .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
  776. },
  777. {
  778. .name = "dpio-tx-c-23",
  779. .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
  780. VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
  781. VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
  782. VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
  783. .ops = &vlv_dpio_power_well_ops,
  784. .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
  785. },
  786. {
  787. .name = "dpio-common",
  788. .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
  789. .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
  790. .ops = &vlv_dpio_cmn_power_well_ops,
  791. },
  792. };
  793. static struct i915_power_well chv_power_wells[] = {
  794. {
  795. .name = "always-on",
  796. .always_on = 1,
  797. .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
  798. .ops = &i9xx_always_on_power_well_ops,
  799. },
  800. #if 0
  801. {
  802. .name = "display",
  803. .domains = VLV_DISPLAY_POWER_DOMAINS,
  804. .data = PUNIT_POWER_WELL_DISP2D,
  805. .ops = &vlv_display_power_well_ops,
  806. },
  807. #endif
  808. {
  809. .name = "pipe-a",
  810. /*
  811. * FIXME: pipe A power well seems to be the new disp2d well.
  812. * At least all registers seem to be housed there. Figure
  813. * out if this a a temporary situation in pre-production
  814. * hardware or a permanent state of affairs.
  815. */
  816. .domains = CHV_PIPE_A_POWER_DOMAINS | VLV_DISPLAY_POWER_DOMAINS,
  817. .data = PIPE_A,
  818. .ops = &chv_pipe_power_well_ops,
  819. },
  820. #if 0
  821. {
  822. .name = "pipe-b",
  823. .domains = CHV_PIPE_B_POWER_DOMAINS,
  824. .data = PIPE_B,
  825. .ops = &chv_pipe_power_well_ops,
  826. },
  827. {
  828. .name = "pipe-c",
  829. .domains = CHV_PIPE_C_POWER_DOMAINS,
  830. .data = PIPE_C,
  831. .ops = &chv_pipe_power_well_ops,
  832. },
  833. #endif
  834. {
  835. .name = "dpio-common-bc",
  836. /*
  837. * XXX: cmnreset for one PHY seems to disturb the other.
  838. * As a workaround keep both powered on at the same
  839. * time for now.
  840. */
  841. .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
  842. .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
  843. .ops = &chv_dpio_cmn_power_well_ops,
  844. },
  845. {
  846. .name = "dpio-common-d",
  847. /*
  848. * XXX: cmnreset for one PHY seems to disturb the other.
  849. * As a workaround keep both powered on at the same
  850. * time for now.
  851. */
  852. .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
  853. .data = PUNIT_POWER_WELL_DPIO_CMN_D,
  854. .ops = &chv_dpio_cmn_power_well_ops,
  855. },
  856. #if 0
  857. {
  858. .name = "dpio-tx-b-01",
  859. .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
  860. VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
  861. .ops = &vlv_dpio_power_well_ops,
  862. .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
  863. },
  864. {
  865. .name = "dpio-tx-b-23",
  866. .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
  867. VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
  868. .ops = &vlv_dpio_power_well_ops,
  869. .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
  870. },
  871. {
  872. .name = "dpio-tx-c-01",
  873. .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
  874. VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
  875. .ops = &vlv_dpio_power_well_ops,
  876. .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
  877. },
  878. {
  879. .name = "dpio-tx-c-23",
  880. .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
  881. VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
  882. .ops = &vlv_dpio_power_well_ops,
  883. .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
  884. },
  885. {
  886. .name = "dpio-tx-d-01",
  887. .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
  888. CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
  889. .ops = &vlv_dpio_power_well_ops,
  890. .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
  891. },
  892. {
  893. .name = "dpio-tx-d-23",
  894. .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
  895. CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
  896. .ops = &vlv_dpio_power_well_ops,
  897. .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
  898. },
  899. #endif
  900. };
  901. static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
  902. enum punit_power_well power_well_id)
  903. {
  904. struct i915_power_domains *power_domains = &dev_priv->power_domains;
  905. struct i915_power_well *power_well;
  906. int i;
  907. for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
  908. if (power_well->data == power_well_id)
  909. return power_well;
  910. }
  911. return NULL;
  912. }
  913. #define set_power_wells(power_domains, __power_wells) ({ \
  914. (power_domains)->power_wells = (__power_wells); \
  915. (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
  916. })
  917. /**
  918. * intel_power_domains_init - initializes the power domain structures
  919. * @dev_priv: i915 device instance
  920. *
  921. * Initializes the power domain structures for @dev_priv depending upon the
  922. * supported platform.
  923. */
  924. int intel_power_domains_init(struct drm_i915_private *dev_priv)
  925. {
  926. struct i915_power_domains *power_domains = &dev_priv->power_domains;
  927. mutex_init(&power_domains->lock);
  928. /*
  929. * The enabling order will be from lower to higher indexed wells,
  930. * the disabling order is reversed.
  931. */
  932. if (IS_HASWELL(dev_priv->dev)) {
  933. set_power_wells(power_domains, hsw_power_wells);
  934. hsw_pwr = power_domains;
  935. } else if (IS_BROADWELL(dev_priv->dev)) {
  936. set_power_wells(power_domains, bdw_power_wells);
  937. hsw_pwr = power_domains;
  938. } else if (IS_CHERRYVIEW(dev_priv->dev)) {
  939. set_power_wells(power_domains, chv_power_wells);
  940. } else if (IS_VALLEYVIEW(dev_priv->dev)) {
  941. set_power_wells(power_domains, vlv_power_wells);
  942. } else {
  943. set_power_wells(power_domains, i9xx_always_on_power_well);
  944. }
  945. return 0;
  946. }
  947. static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv)
  948. {
  949. struct drm_device *dev = dev_priv->dev;
  950. struct device *device = &dev->pdev->dev;
  951. if (!HAS_RUNTIME_PM(dev))
  952. return;
  953. if (!intel_enable_rc6(dev))
  954. return;
  955. /* Make sure we're not suspended first. */
  956. pm_runtime_get_sync(device);
  957. pm_runtime_disable(device);
  958. }
  959. /**
  960. * intel_power_domains_fini - finalizes the power domain structures
  961. * @dev_priv: i915 device instance
  962. *
  963. * Finalizes the power domain structures for @dev_priv depending upon the
  964. * supported platform. This function also disables runtime pm and ensures that
  965. * the device stays powered up so that the driver can be reloaded.
  966. */
  967. void intel_power_domains_fini(struct drm_i915_private *dev_priv)
  968. {
  969. intel_runtime_pm_disable(dev_priv);
  970. /* The i915.ko module is still not prepared to be loaded when
  971. * the power well is not enabled, so just enable it in case
  972. * we're going to unload/reload. */
  973. intel_display_set_init_power(dev_priv, true);
  974. hsw_pwr = NULL;
  975. }
  976. static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
  977. {
  978. struct i915_power_domains *power_domains = &dev_priv->power_domains;
  979. struct i915_power_well *power_well;
  980. int i;
  981. mutex_lock(&power_domains->lock);
  982. for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
  983. power_well->ops->sync_hw(dev_priv, power_well);
  984. power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
  985. power_well);
  986. }
  987. mutex_unlock(&power_domains->lock);
  988. }
  989. static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
  990. {
  991. struct i915_power_well *cmn =
  992. lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
  993. struct i915_power_well *disp2d =
  994. lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
  995. /* If the display might be already active skip this */
  996. if (cmn->ops->is_enabled(dev_priv, cmn) &&
  997. disp2d->ops->is_enabled(dev_priv, disp2d) &&
  998. I915_READ(DPIO_CTL) & DPIO_CMNRST)
  999. return;
  1000. DRM_DEBUG_KMS("toggling display PHY side reset\n");
  1001. /* cmnlane needs DPLL registers */
  1002. disp2d->ops->enable(dev_priv, disp2d);
  1003. /*
  1004. * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
  1005. * Need to assert and de-assert PHY SB reset by gating the
  1006. * common lane power, then un-gating it.
  1007. * Simply ungating isn't enough to reset the PHY enough to get
  1008. * ports and lanes running.
  1009. */
  1010. cmn->ops->disable(dev_priv, cmn);
  1011. }
  1012. /**
  1013. * intel_power_domains_init_hw - initialize hardware power domain state
  1014. * @dev_priv: i915 device instance
  1015. *
  1016. * This function initializes the hardware power domain state and enables all
  1017. * power domains using intel_display_set_init_power().
  1018. */
  1019. void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
  1020. {
  1021. struct drm_device *dev = dev_priv->dev;
  1022. struct i915_power_domains *power_domains = &dev_priv->power_domains;
  1023. power_domains->initializing = true;
  1024. if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
  1025. mutex_lock(&power_domains->lock);
  1026. vlv_cmnlane_wa(dev_priv);
  1027. mutex_unlock(&power_domains->lock);
  1028. }
  1029. /* For now, we need the power well to be always enabled. */
  1030. intel_display_set_init_power(dev_priv, true);
  1031. intel_power_domains_resume(dev_priv);
  1032. power_domains->initializing = false;
  1033. }
  1034. /**
  1035. * intel_aux_display_runtime_get - grab an auxilliary power domain reference
  1036. * @dev_priv: i915 device instance
  1037. *
  1038. * This function grabs a power domain reference for the auxiliary power domain
  1039. * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its
  1040. * parents are powered up. Therefore users should only grab a reference to the
  1041. * innermost power domain they need.
  1042. *
  1043. * Any power domain reference obtained by this function must have a symmetric
  1044. * call to intel_aux_display_runtime_put() to release the reference again.
  1045. */
  1046. void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
  1047. {
  1048. intel_runtime_pm_get(dev_priv);
  1049. }
  1050. /**
  1051. * intel_aux_display_runtime_put - release an auxilliary power domain reference
  1052. * @dev_priv: i915 device instance
  1053. *
  1054. * This function drops the auxilliary power domain reference obtained by
  1055. * intel_aux_display_runtime_get() and might power down the corresponding
  1056. * hardware block right away if this is the last reference.
  1057. */
  1058. void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
  1059. {
  1060. intel_runtime_pm_put(dev_priv);
  1061. }
  1062. /**
  1063. * intel_runtime_pm_get - grab a runtime pm reference
  1064. * @dev_priv: i915 device instance
  1065. *
  1066. * This function grabs a device-level runtime pm reference (mostly used for GEM
  1067. * code to ensure the GTT or GT is on) and ensures that it is powered up.
  1068. *
  1069. * Any runtime pm reference obtained by this function must have a symmetric
  1070. * call to intel_runtime_pm_put() to release the reference again.
  1071. */
  1072. void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
  1073. {
  1074. struct drm_device *dev = dev_priv->dev;
  1075. struct device *device = &dev->pdev->dev;
  1076. if (!HAS_RUNTIME_PM(dev))
  1077. return;
  1078. pm_runtime_get_sync(device);
  1079. WARN(dev_priv->pm.suspended, "Device still suspended.\n");
  1080. }
  1081. /**
  1082. * intel_runtime_pm_get_noresume - grab a runtime pm reference
  1083. * @dev_priv: i915 device instance
  1084. *
  1085. * This function grabs a device-level runtime pm reference (mostly used for GEM
  1086. * code to ensure the GTT or GT is on).
  1087. *
  1088. * It will _not_ power up the device but instead only check that it's powered
  1089. * on. Therefore it is only valid to call this functions from contexts where
  1090. * the device is known to be powered up and where trying to power it up would
  1091. * result in hilarity and deadlocks. That pretty much means only the system
  1092. * suspend/resume code where this is used to grab runtime pm references for
  1093. * delayed setup down in work items.
  1094. *
  1095. * Any runtime pm reference obtained by this function must have a symmetric
  1096. * call to intel_runtime_pm_put() to release the reference again.
  1097. */
  1098. void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
  1099. {
  1100. struct drm_device *dev = dev_priv->dev;
  1101. struct device *device = &dev->pdev->dev;
  1102. if (!HAS_RUNTIME_PM(dev))
  1103. return;
  1104. WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
  1105. pm_runtime_get_noresume(device);
  1106. }
  1107. /**
  1108. * intel_runtime_pm_put - release a runtime pm reference
  1109. * @dev_priv: i915 device instance
  1110. *
  1111. * This function drops the device-level runtime pm reference obtained by
  1112. * intel_runtime_pm_get() and might power down the corresponding
  1113. * hardware block right away if this is the last reference.
  1114. */
  1115. void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
  1116. {
  1117. struct drm_device *dev = dev_priv->dev;
  1118. struct device *device = &dev->pdev->dev;
  1119. if (!HAS_RUNTIME_PM(dev))
  1120. return;
  1121. pm_runtime_mark_last_busy(device);
  1122. pm_runtime_put_autosuspend(device);
  1123. }
  1124. /**
  1125. * intel_runtime_pm_enable - enable runtime pm
  1126. * @dev_priv: i915 device instance
  1127. *
  1128. * This function enables runtime pm at the end of the driver load sequence.
  1129. *
  1130. * Note that this function does currently not enable runtime pm for the
  1131. * subordinate display power domains. That is only done on the first modeset
  1132. * using intel_display_set_init_power().
  1133. */
  1134. void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
  1135. {
  1136. struct drm_device *dev = dev_priv->dev;
  1137. struct device *device = &dev->pdev->dev;
  1138. if (!HAS_RUNTIME_PM(dev))
  1139. return;
  1140. pm_runtime_set_active(device);
  1141. /*
  1142. * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
  1143. * requirement.
  1144. */
  1145. if (!intel_enable_rc6(dev)) {
  1146. DRM_INFO("RC6 disabled, disabling runtime PM support\n");
  1147. return;
  1148. }
  1149. pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
  1150. pm_runtime_mark_last_busy(device);
  1151. pm_runtime_use_autosuspend(device);
  1152. pm_runtime_put_autosuspend(device);
  1153. }
  1154. /* Display audio driver power well request */
  1155. int i915_request_power_well(void)
  1156. {
  1157. struct drm_i915_private *dev_priv;
  1158. if (!hsw_pwr)
  1159. return -ENODEV;
  1160. dev_priv = container_of(hsw_pwr, struct drm_i915_private,
  1161. power_domains);
  1162. intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
  1163. return 0;
  1164. }
  1165. EXPORT_SYMBOL_GPL(i915_request_power_well);
  1166. /* Display audio driver power well release */
  1167. int i915_release_power_well(void)
  1168. {
  1169. struct drm_i915_private *dev_priv;
  1170. if (!hsw_pwr)
  1171. return -ENODEV;
  1172. dev_priv = container_of(hsw_pwr, struct drm_i915_private,
  1173. power_domains);
  1174. intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
  1175. return 0;
  1176. }
  1177. EXPORT_SYMBOL_GPL(i915_release_power_well);
  1178. /*
  1179. * Private interface for the audio driver to get CDCLK in kHz.
  1180. *
  1181. * Caller must request power well using i915_request_power_well() prior to
  1182. * making the call.
  1183. */
  1184. int i915_get_cdclk_freq(void)
  1185. {
  1186. struct drm_i915_private *dev_priv;
  1187. if (!hsw_pwr)
  1188. return -ENODEV;
  1189. dev_priv = container_of(hsw_pwr, struct drm_i915_private,
  1190. power_domains);
  1191. return intel_ddi_get_cdclk_freq(dev_priv);
  1192. }
  1193. EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);