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arch
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arm
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mach-exynos
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sleep.S

sleep.S 2.0 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
    3. 

  3.  *		http://www.samsung.com
    4. 

  4.  *
    5. 

  5.  * Exynos low-level resume code
    6. 

  6.  *
    7. 

  7.  * This program is free software; you can redistribute it and/or modify
    8. 

  8.  * it under the terms of the GNU General Public License as published by
    9. 

  9.  * the Free Software Foundation; either version 2 of the License, or
    10. 

  10.  * (at your option) any later version.
    11. 

  11.  *
    12. 

  12.  * This program is distributed in the hope that it will be useful,
    13. 

  13.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    14. 

  14.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    15. 

  15.  * GNU General Public License for more details.
    16. 

  16.  */
    17. 

  17. 

  18. #include <linux/linkage.h>
    19. 

  19. #include "smc.h"
    20. 

  20. 

  21. #define CPU_MASK	0xff0ffff0
    22. 

  22. #define CPU_CORTEX_A9	0x410fc090
    23. 

  23. 

  24. 	/*
    25. 

  25. 	 * The following code is located into the .data section. This is to
    26. 

  26. 	 * allow l2x0_regs_phys to be accessed with a relative load while we
    27. 

  27. 	 * can't rely on any MMU translation. We could have put l2x0_regs_phys
    28. 

  28. 	 * in the .text section as well, but some setups might insist on it to
    29. 

  29. 	 * be truly read-only. (Reference from: arch/arm/kernel/sleep.S)
    30. 

  30. 	 */
    31. 

  31. 	.data
    32. 

  32. 	.align
    33. 

  33. 

  34. 	/*
    35. 

  35. 	 * sleep magic, to allow the bootloader to check for an valid
    36. 

  36. 	 * image to resume to. Must be the first word before the
    37. 

  37. 	 * exynos_cpu_resume entry.
    38. 

  38. 	 */
    39. 

  39. 

  40. 	.word	0x2bedf00d
    41. 

  41. 

  42. 	/*
    43. 

  43. 	 * exynos_cpu_resume
    44. 

  44. 	 *
    45. 

  45. 	 * resume code entry for bootloader to call
    46. 

  46. 	 */
    47. 

  47. 

  48. ENTRY(exynos_cpu_resume)
    49. 

  49. #ifdef CONFIG_CACHE_L2X0
    50. 

  50. 	mrc	p15, 0, r0, c0, c0, 0
    51. 

  51. 	ldr	r1, =CPU_MASK
    52. 

  52. 	and	r0, r0, r1
    53. 

  53. 	ldr	r1, =CPU_CORTEX_A9
    54. 

  54. 	cmp	r0, r1
    55. 

  55. 	bleq	l2c310_early_resume
    56. 

  56. #endif
    57. 

  57. 	b	cpu_resume
    58. 

  58. ENDPROC(exynos_cpu_resume)
    59. 

  59. 

  60. 	.align
    61. 

  61. 

  62. ENTRY(exynos_cpu_resume_ns)
    63. 

  63. 	mrc	p15, 0, r0, c0, c0, 0
    64. 

  64. 	ldr	r1, =CPU_MASK
    65. 

  65. 	and	r0, r0, r1
    66. 

  66. 	ldr	r1, =CPU_CORTEX_A9
    67. 

  67. 	cmp	r0, r1
    68. 

  68. 	bne	skip_cp15
    69. 

  69. 

  70. 	adr	r0, cp15_save_power
    71. 

  71. 	ldr	r1, [r0]
    72. 

  72. 	adr	r0, cp15_save_diag
    73. 

  73. 	ldr	r2, [r0]
    74. 

  74. 	mov	r0, #SMC_CMD_C15RESUME
    75. 

  75. 	dsb
    76. 

  76. 	smc	#0
    77. 

  77. skip_cp15:
    78. 

  78. 	b	cpu_resume
    79. 

  79. ENDPROC(exynos_cpu_resume_ns)
    80. 

  80. 	.globl cp15_save_diag
    81. 

  81. cp15_save_diag:
    82. 

  82. 	.long	0	@ cp15 diagnostic
    83. 

  83. 	.globl cp15_save_power
    84. 

  84. cp15_save_power:
    85. 

  85. 	.long	0	@ cp15 power control
    86.