pm.h 3.1 KB

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  1. /*
  2. * AT91 Power Management
  3. *
  4. * Copyright (C) 2005 David Brownell
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. */
  11. #ifndef __ARCH_ARM_MACH_AT91_PM
  12. #define __ARCH_ARM_MACH_AT91_PM
  13. #include <asm/proc-fns.h>
  14. #include <mach/at91_ramc.h>
  15. #ifdef CONFIG_PM
  16. extern void at91_pm_set_standby(void (*at91_standby)(void));
  17. #else
  18. static inline void at91_pm_set_standby(void (*at91_standby)(void)) { }
  19. #endif
  20. /*
  21. * The AT91RM9200 goes into self-refresh mode with this command, and will
  22. * terminate self-refresh automatically on the next SDRAM access.
  23. *
  24. * Self-refresh mode is exited as soon as a memory access is made, but we don't
  25. * know for sure when that happens. However, we need to restore the low-power
  26. * mode if it was enabled before going idle. Restoring low-power mode while
  27. * still in self-refresh is "not recommended", but seems to work.
  28. */
  29. static inline void at91rm9200_standby(void)
  30. {
  31. u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
  32. asm volatile(
  33. "b 1f\n\t"
  34. ".align 5\n\t"
  35. "1: mcr p15, 0, %0, c7, c10, 4\n\t"
  36. " str %0, [%1, %2]\n\t"
  37. " str %3, [%1, %4]\n\t"
  38. " mcr p15, 0, %0, c7, c0, 4\n\t"
  39. " str %5, [%1, %2]"
  40. :
  41. : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR),
  42. "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
  43. "r" (lpr));
  44. }
  45. /* We manage both DDRAM/SDRAM controllers, we need more than one value to
  46. * remember.
  47. */
  48. static inline void at91_ddr_standby(void)
  49. {
  50. /* Those two values allow us to delay self-refresh activation
  51. * to the maximum. */
  52. u32 lpr0, lpr1 = 0;
  53. u32 saved_lpr0, saved_lpr1 = 0;
  54. if (at91_ramc_base[1]) {
  55. saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
  56. lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
  57. lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
  58. }
  59. saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
  60. lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
  61. lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
  62. /* self-refresh mode now */
  63. at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
  64. if (at91_ramc_base[1])
  65. at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
  66. cpu_do_idle();
  67. at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
  68. if (at91_ramc_base[1])
  69. at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
  70. }
  71. /* We manage both DDRAM/SDRAM controllers, we need more than one value to
  72. * remember.
  73. */
  74. static inline void at91sam9_sdram_standby(void)
  75. {
  76. u32 lpr0, lpr1 = 0;
  77. u32 saved_lpr0, saved_lpr1 = 0;
  78. if (at91_ramc_base[1]) {
  79. saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
  80. lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
  81. lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
  82. }
  83. saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
  84. lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
  85. lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
  86. /* self-refresh mode now */
  87. at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
  88. if (at91_ramc_base[1])
  89. at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
  90. cpu_do_idle();
  91. at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
  92. if (at91_ramc_base[1])
  93. at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
  94. }
  95. #endif