exynos_drm_g2d.c 36 KB

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  1. /*
  2. * Copyright (C) 2012 Samsung Electronics Co.Ltd
  3. * Authors: Joonyoung Shim <jy0922.shim@samsung.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundationr
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/clk.h>
  11. #include <linux/err.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/slab.h>
  17. #include <linux/workqueue.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/of.h>
  20. #include <drm/drmP.h>
  21. #include <drm/exynos_drm.h>
  22. #include "exynos_drm_drv.h"
  23. #include "exynos_drm_g2d.h"
  24. #include "exynos_drm_gem.h"
  25. #include "exynos_drm_iommu.h"
  26. #define G2D_HW_MAJOR_VER 4
  27. #define G2D_HW_MINOR_VER 1
  28. /* vaild register range set from user: 0x0104 ~ 0x0880 */
  29. #define G2D_VALID_START 0x0104
  30. #define G2D_VALID_END 0x0880
  31. /* general registers */
  32. #define G2D_SOFT_RESET 0x0000
  33. #define G2D_INTEN 0x0004
  34. #define G2D_INTC_PEND 0x000C
  35. #define G2D_DMA_SFR_BASE_ADDR 0x0080
  36. #define G2D_DMA_COMMAND 0x0084
  37. #define G2D_DMA_STATUS 0x008C
  38. #define G2D_DMA_HOLD_CMD 0x0090
  39. /* command registers */
  40. #define G2D_BITBLT_START 0x0100
  41. /* registers for base address */
  42. #define G2D_SRC_BASE_ADDR 0x0304
  43. #define G2D_SRC_STRIDE 0x0308
  44. #define G2D_SRC_COLOR_MODE 0x030C
  45. #define G2D_SRC_LEFT_TOP 0x0310
  46. #define G2D_SRC_RIGHT_BOTTOM 0x0314
  47. #define G2D_SRC_PLANE2_BASE_ADDR 0x0318
  48. #define G2D_DST_BASE_ADDR 0x0404
  49. #define G2D_DST_STRIDE 0x0408
  50. #define G2D_DST_COLOR_MODE 0x040C
  51. #define G2D_DST_LEFT_TOP 0x0410
  52. #define G2D_DST_RIGHT_BOTTOM 0x0414
  53. #define G2D_DST_PLANE2_BASE_ADDR 0x0418
  54. #define G2D_PAT_BASE_ADDR 0x0500
  55. #define G2D_MSK_BASE_ADDR 0x0520
  56. /* G2D_SOFT_RESET */
  57. #define G2D_SFRCLEAR (1 << 1)
  58. #define G2D_R (1 << 0)
  59. /* G2D_INTEN */
  60. #define G2D_INTEN_ACF (1 << 3)
  61. #define G2D_INTEN_UCF (1 << 2)
  62. #define G2D_INTEN_GCF (1 << 1)
  63. #define G2D_INTEN_SCF (1 << 0)
  64. /* G2D_INTC_PEND */
  65. #define G2D_INTP_ACMD_FIN (1 << 3)
  66. #define G2D_INTP_UCMD_FIN (1 << 2)
  67. #define G2D_INTP_GCMD_FIN (1 << 1)
  68. #define G2D_INTP_SCMD_FIN (1 << 0)
  69. /* G2D_DMA_COMMAND */
  70. #define G2D_DMA_HALT (1 << 2)
  71. #define G2D_DMA_CONTINUE (1 << 1)
  72. #define G2D_DMA_START (1 << 0)
  73. /* G2D_DMA_STATUS */
  74. #define G2D_DMA_LIST_DONE_COUNT (0xFF << 17)
  75. #define G2D_DMA_BITBLT_DONE_COUNT (0xFFFF << 1)
  76. #define G2D_DMA_DONE (1 << 0)
  77. #define G2D_DMA_LIST_DONE_COUNT_OFFSET 17
  78. /* G2D_DMA_HOLD_CMD */
  79. #define G2D_USER_HOLD (1 << 2)
  80. #define G2D_LIST_HOLD (1 << 1)
  81. #define G2D_BITBLT_HOLD (1 << 0)
  82. /* G2D_BITBLT_START */
  83. #define G2D_START_CASESEL (1 << 2)
  84. #define G2D_START_NHOLT (1 << 1)
  85. #define G2D_START_BITBLT (1 << 0)
  86. /* buffer color format */
  87. #define G2D_FMT_XRGB8888 0
  88. #define G2D_FMT_ARGB8888 1
  89. #define G2D_FMT_RGB565 2
  90. #define G2D_FMT_XRGB1555 3
  91. #define G2D_FMT_ARGB1555 4
  92. #define G2D_FMT_XRGB4444 5
  93. #define G2D_FMT_ARGB4444 6
  94. #define G2D_FMT_PACKED_RGB888 7
  95. #define G2D_FMT_A8 11
  96. #define G2D_FMT_L8 12
  97. /* buffer valid length */
  98. #define G2D_LEN_MIN 1
  99. #define G2D_LEN_MAX 8000
  100. #define G2D_CMDLIST_SIZE (PAGE_SIZE / 4)
  101. #define G2D_CMDLIST_NUM 64
  102. #define G2D_CMDLIST_POOL_SIZE (G2D_CMDLIST_SIZE * G2D_CMDLIST_NUM)
  103. #define G2D_CMDLIST_DATA_NUM (G2D_CMDLIST_SIZE / sizeof(u32) - 2)
  104. /* maximum buffer pool size of userptr is 64MB as default */
  105. #define MAX_POOL (64 * 1024 * 1024)
  106. enum {
  107. BUF_TYPE_GEM = 1,
  108. BUF_TYPE_USERPTR,
  109. };
  110. enum g2d_reg_type {
  111. REG_TYPE_NONE = -1,
  112. REG_TYPE_SRC,
  113. REG_TYPE_SRC_PLANE2,
  114. REG_TYPE_DST,
  115. REG_TYPE_DST_PLANE2,
  116. REG_TYPE_PAT,
  117. REG_TYPE_MSK,
  118. MAX_REG_TYPE_NR
  119. };
  120. /* cmdlist data structure */
  121. struct g2d_cmdlist {
  122. u32 head;
  123. unsigned long data[G2D_CMDLIST_DATA_NUM];
  124. u32 last; /* last data offset */
  125. };
  126. /*
  127. * A structure of buffer description
  128. *
  129. * @format: color format
  130. * @stride: buffer stride/pitch in bytes
  131. * @left_x: the x coordinates of left top corner
  132. * @top_y: the y coordinates of left top corner
  133. * @right_x: the x coordinates of right bottom corner
  134. * @bottom_y: the y coordinates of right bottom corner
  135. *
  136. */
  137. struct g2d_buf_desc {
  138. unsigned int format;
  139. unsigned int stride;
  140. unsigned int left_x;
  141. unsigned int top_y;
  142. unsigned int right_x;
  143. unsigned int bottom_y;
  144. };
  145. /*
  146. * A structure of buffer information
  147. *
  148. * @map_nr: manages the number of mapped buffers
  149. * @reg_types: stores regitster type in the order of requested command
  150. * @handles: stores buffer handle in its reg_type position
  151. * @types: stores buffer type in its reg_type position
  152. * @descs: stores buffer description in its reg_type position
  153. *
  154. */
  155. struct g2d_buf_info {
  156. unsigned int map_nr;
  157. enum g2d_reg_type reg_types[MAX_REG_TYPE_NR];
  158. unsigned long handles[MAX_REG_TYPE_NR];
  159. unsigned int types[MAX_REG_TYPE_NR];
  160. struct g2d_buf_desc descs[MAX_REG_TYPE_NR];
  161. };
  162. struct drm_exynos_pending_g2d_event {
  163. struct drm_pending_event base;
  164. struct drm_exynos_g2d_event event;
  165. };
  166. struct g2d_cmdlist_userptr {
  167. struct list_head list;
  168. dma_addr_t dma_addr;
  169. unsigned long userptr;
  170. unsigned long size;
  171. struct frame_vector *vec;
  172. struct sg_table *sgt;
  173. atomic_t refcount;
  174. bool in_pool;
  175. bool out_of_list;
  176. };
  177. struct g2d_cmdlist_node {
  178. struct list_head list;
  179. struct g2d_cmdlist *cmdlist;
  180. dma_addr_t dma_addr;
  181. struct g2d_buf_info buf_info;
  182. struct drm_exynos_pending_g2d_event *event;
  183. };
  184. struct g2d_runqueue_node {
  185. struct list_head list;
  186. struct list_head run_cmdlist;
  187. struct list_head event_list;
  188. struct drm_file *filp;
  189. pid_t pid;
  190. struct completion complete;
  191. int async;
  192. };
  193. struct g2d_data {
  194. struct device *dev;
  195. struct clk *gate_clk;
  196. void __iomem *regs;
  197. int irq;
  198. struct workqueue_struct *g2d_workq;
  199. struct work_struct runqueue_work;
  200. struct exynos_drm_subdrv subdrv;
  201. bool suspended;
  202. /* cmdlist */
  203. struct g2d_cmdlist_node *cmdlist_node;
  204. struct list_head free_cmdlist;
  205. struct mutex cmdlist_mutex;
  206. dma_addr_t cmdlist_pool;
  207. void *cmdlist_pool_virt;
  208. unsigned long cmdlist_dma_attrs;
  209. /* runqueue*/
  210. struct g2d_runqueue_node *runqueue_node;
  211. struct list_head runqueue;
  212. struct mutex runqueue_mutex;
  213. struct kmem_cache *runqueue_slab;
  214. unsigned long current_pool;
  215. unsigned long max_pool;
  216. };
  217. static int g2d_init_cmdlist(struct g2d_data *g2d)
  218. {
  219. struct device *dev = g2d->dev;
  220. struct g2d_cmdlist_node *node = g2d->cmdlist_node;
  221. struct exynos_drm_subdrv *subdrv = &g2d->subdrv;
  222. int nr;
  223. int ret;
  224. struct g2d_buf_info *buf_info;
  225. g2d->cmdlist_dma_attrs = DMA_ATTR_WRITE_COMBINE;
  226. g2d->cmdlist_pool_virt = dma_alloc_attrs(to_dma_dev(subdrv->drm_dev),
  227. G2D_CMDLIST_POOL_SIZE,
  228. &g2d->cmdlist_pool, GFP_KERNEL,
  229. g2d->cmdlist_dma_attrs);
  230. if (!g2d->cmdlist_pool_virt) {
  231. dev_err(dev, "failed to allocate dma memory\n");
  232. return -ENOMEM;
  233. }
  234. node = kcalloc(G2D_CMDLIST_NUM, sizeof(*node), GFP_KERNEL);
  235. if (!node) {
  236. dev_err(dev, "failed to allocate memory\n");
  237. ret = -ENOMEM;
  238. goto err;
  239. }
  240. for (nr = 0; nr < G2D_CMDLIST_NUM; nr++) {
  241. unsigned int i;
  242. node[nr].cmdlist =
  243. g2d->cmdlist_pool_virt + nr * G2D_CMDLIST_SIZE;
  244. node[nr].dma_addr =
  245. g2d->cmdlist_pool + nr * G2D_CMDLIST_SIZE;
  246. buf_info = &node[nr].buf_info;
  247. for (i = 0; i < MAX_REG_TYPE_NR; i++)
  248. buf_info->reg_types[i] = REG_TYPE_NONE;
  249. list_add_tail(&node[nr].list, &g2d->free_cmdlist);
  250. }
  251. return 0;
  252. err:
  253. dma_free_attrs(to_dma_dev(subdrv->drm_dev), G2D_CMDLIST_POOL_SIZE,
  254. g2d->cmdlist_pool_virt,
  255. g2d->cmdlist_pool, g2d->cmdlist_dma_attrs);
  256. return ret;
  257. }
  258. static void g2d_fini_cmdlist(struct g2d_data *g2d)
  259. {
  260. struct exynos_drm_subdrv *subdrv = &g2d->subdrv;
  261. kfree(g2d->cmdlist_node);
  262. if (g2d->cmdlist_pool_virt && g2d->cmdlist_pool) {
  263. dma_free_attrs(to_dma_dev(subdrv->drm_dev),
  264. G2D_CMDLIST_POOL_SIZE,
  265. g2d->cmdlist_pool_virt,
  266. g2d->cmdlist_pool, g2d->cmdlist_dma_attrs);
  267. }
  268. }
  269. static struct g2d_cmdlist_node *g2d_get_cmdlist(struct g2d_data *g2d)
  270. {
  271. struct device *dev = g2d->dev;
  272. struct g2d_cmdlist_node *node;
  273. mutex_lock(&g2d->cmdlist_mutex);
  274. if (list_empty(&g2d->free_cmdlist)) {
  275. dev_err(dev, "there is no free cmdlist\n");
  276. mutex_unlock(&g2d->cmdlist_mutex);
  277. return NULL;
  278. }
  279. node = list_first_entry(&g2d->free_cmdlist, struct g2d_cmdlist_node,
  280. list);
  281. list_del_init(&node->list);
  282. mutex_unlock(&g2d->cmdlist_mutex);
  283. return node;
  284. }
  285. static void g2d_put_cmdlist(struct g2d_data *g2d, struct g2d_cmdlist_node *node)
  286. {
  287. mutex_lock(&g2d->cmdlist_mutex);
  288. list_move_tail(&node->list, &g2d->free_cmdlist);
  289. mutex_unlock(&g2d->cmdlist_mutex);
  290. }
  291. static void g2d_add_cmdlist_to_inuse(struct exynos_drm_g2d_private *g2d_priv,
  292. struct g2d_cmdlist_node *node)
  293. {
  294. struct g2d_cmdlist_node *lnode;
  295. if (list_empty(&g2d_priv->inuse_cmdlist))
  296. goto add_to_list;
  297. /* this links to base address of new cmdlist */
  298. lnode = list_entry(g2d_priv->inuse_cmdlist.prev,
  299. struct g2d_cmdlist_node, list);
  300. lnode->cmdlist->data[lnode->cmdlist->last] = node->dma_addr;
  301. add_to_list:
  302. list_add_tail(&node->list, &g2d_priv->inuse_cmdlist);
  303. if (node->event)
  304. list_add_tail(&node->event->base.link, &g2d_priv->event_list);
  305. }
  306. static void g2d_userptr_put_dma_addr(struct drm_device *drm_dev,
  307. unsigned long obj,
  308. bool force)
  309. {
  310. struct g2d_cmdlist_userptr *g2d_userptr =
  311. (struct g2d_cmdlist_userptr *)obj;
  312. struct page **pages;
  313. if (!obj)
  314. return;
  315. if (force)
  316. goto out;
  317. atomic_dec(&g2d_userptr->refcount);
  318. if (atomic_read(&g2d_userptr->refcount) > 0)
  319. return;
  320. if (g2d_userptr->in_pool)
  321. return;
  322. out:
  323. dma_unmap_sg(to_dma_dev(drm_dev), g2d_userptr->sgt->sgl,
  324. g2d_userptr->sgt->nents, DMA_BIDIRECTIONAL);
  325. pages = frame_vector_pages(g2d_userptr->vec);
  326. if (!IS_ERR(pages)) {
  327. int i;
  328. for (i = 0; i < frame_vector_count(g2d_userptr->vec); i++)
  329. set_page_dirty_lock(pages[i]);
  330. }
  331. put_vaddr_frames(g2d_userptr->vec);
  332. frame_vector_destroy(g2d_userptr->vec);
  333. if (!g2d_userptr->out_of_list)
  334. list_del_init(&g2d_userptr->list);
  335. sg_free_table(g2d_userptr->sgt);
  336. kfree(g2d_userptr->sgt);
  337. kfree(g2d_userptr);
  338. }
  339. static dma_addr_t *g2d_userptr_get_dma_addr(struct drm_device *drm_dev,
  340. unsigned long userptr,
  341. unsigned long size,
  342. struct drm_file *filp,
  343. unsigned long *obj)
  344. {
  345. struct drm_exynos_file_private *file_priv = filp->driver_priv;
  346. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  347. struct g2d_cmdlist_userptr *g2d_userptr;
  348. struct g2d_data *g2d;
  349. struct sg_table *sgt;
  350. unsigned long start, end;
  351. unsigned int npages, offset;
  352. int ret;
  353. if (!size) {
  354. DRM_ERROR("invalid userptr size.\n");
  355. return ERR_PTR(-EINVAL);
  356. }
  357. g2d = dev_get_drvdata(g2d_priv->dev);
  358. /* check if userptr already exists in userptr_list. */
  359. list_for_each_entry(g2d_userptr, &g2d_priv->userptr_list, list) {
  360. if (g2d_userptr->userptr == userptr) {
  361. /*
  362. * also check size because there could be same address
  363. * and different size.
  364. */
  365. if (g2d_userptr->size == size) {
  366. atomic_inc(&g2d_userptr->refcount);
  367. *obj = (unsigned long)g2d_userptr;
  368. return &g2d_userptr->dma_addr;
  369. }
  370. /*
  371. * at this moment, maybe g2d dma is accessing this
  372. * g2d_userptr memory region so just remove this
  373. * g2d_userptr object from userptr_list not to be
  374. * referred again and also except it the userptr
  375. * pool to be released after the dma access completion.
  376. */
  377. g2d_userptr->out_of_list = true;
  378. g2d_userptr->in_pool = false;
  379. list_del_init(&g2d_userptr->list);
  380. break;
  381. }
  382. }
  383. g2d_userptr = kzalloc(sizeof(*g2d_userptr), GFP_KERNEL);
  384. if (!g2d_userptr)
  385. return ERR_PTR(-ENOMEM);
  386. atomic_set(&g2d_userptr->refcount, 1);
  387. g2d_userptr->size = size;
  388. start = userptr & PAGE_MASK;
  389. offset = userptr & ~PAGE_MASK;
  390. end = PAGE_ALIGN(userptr + size);
  391. npages = (end - start) >> PAGE_SHIFT;
  392. g2d_userptr->vec = frame_vector_create(npages);
  393. if (!g2d_userptr->vec) {
  394. ret = -ENOMEM;
  395. goto err_free;
  396. }
  397. ret = get_vaddr_frames(start, npages, true, true, g2d_userptr->vec);
  398. if (ret != npages) {
  399. DRM_ERROR("failed to get user pages from userptr.\n");
  400. if (ret < 0)
  401. goto err_destroy_framevec;
  402. ret = -EFAULT;
  403. goto err_put_framevec;
  404. }
  405. if (frame_vector_to_pages(g2d_userptr->vec) < 0) {
  406. ret = -EFAULT;
  407. goto err_put_framevec;
  408. }
  409. sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
  410. if (!sgt) {
  411. ret = -ENOMEM;
  412. goto err_put_framevec;
  413. }
  414. ret = sg_alloc_table_from_pages(sgt,
  415. frame_vector_pages(g2d_userptr->vec),
  416. npages, offset, size, GFP_KERNEL);
  417. if (ret < 0) {
  418. DRM_ERROR("failed to get sgt from pages.\n");
  419. goto err_free_sgt;
  420. }
  421. g2d_userptr->sgt = sgt;
  422. if (!dma_map_sg(to_dma_dev(drm_dev), sgt->sgl, sgt->nents,
  423. DMA_BIDIRECTIONAL)) {
  424. DRM_ERROR("failed to map sgt with dma region.\n");
  425. ret = -ENOMEM;
  426. goto err_sg_free_table;
  427. }
  428. g2d_userptr->dma_addr = sgt->sgl[0].dma_address;
  429. g2d_userptr->userptr = userptr;
  430. list_add_tail(&g2d_userptr->list, &g2d_priv->userptr_list);
  431. if (g2d->current_pool + (npages << PAGE_SHIFT) < g2d->max_pool) {
  432. g2d->current_pool += npages << PAGE_SHIFT;
  433. g2d_userptr->in_pool = true;
  434. }
  435. *obj = (unsigned long)g2d_userptr;
  436. return &g2d_userptr->dma_addr;
  437. err_sg_free_table:
  438. sg_free_table(sgt);
  439. err_free_sgt:
  440. kfree(sgt);
  441. err_put_framevec:
  442. put_vaddr_frames(g2d_userptr->vec);
  443. err_destroy_framevec:
  444. frame_vector_destroy(g2d_userptr->vec);
  445. err_free:
  446. kfree(g2d_userptr);
  447. return ERR_PTR(ret);
  448. }
  449. static void g2d_userptr_free_all(struct drm_device *drm_dev,
  450. struct g2d_data *g2d,
  451. struct drm_file *filp)
  452. {
  453. struct drm_exynos_file_private *file_priv = filp->driver_priv;
  454. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  455. struct g2d_cmdlist_userptr *g2d_userptr, *n;
  456. list_for_each_entry_safe(g2d_userptr, n, &g2d_priv->userptr_list, list)
  457. if (g2d_userptr->in_pool)
  458. g2d_userptr_put_dma_addr(drm_dev,
  459. (unsigned long)g2d_userptr,
  460. true);
  461. g2d->current_pool = 0;
  462. }
  463. static enum g2d_reg_type g2d_get_reg_type(int reg_offset)
  464. {
  465. enum g2d_reg_type reg_type;
  466. switch (reg_offset) {
  467. case G2D_SRC_BASE_ADDR:
  468. case G2D_SRC_STRIDE:
  469. case G2D_SRC_COLOR_MODE:
  470. case G2D_SRC_LEFT_TOP:
  471. case G2D_SRC_RIGHT_BOTTOM:
  472. reg_type = REG_TYPE_SRC;
  473. break;
  474. case G2D_SRC_PLANE2_BASE_ADDR:
  475. reg_type = REG_TYPE_SRC_PLANE2;
  476. break;
  477. case G2D_DST_BASE_ADDR:
  478. case G2D_DST_STRIDE:
  479. case G2D_DST_COLOR_MODE:
  480. case G2D_DST_LEFT_TOP:
  481. case G2D_DST_RIGHT_BOTTOM:
  482. reg_type = REG_TYPE_DST;
  483. break;
  484. case G2D_DST_PLANE2_BASE_ADDR:
  485. reg_type = REG_TYPE_DST_PLANE2;
  486. break;
  487. case G2D_PAT_BASE_ADDR:
  488. reg_type = REG_TYPE_PAT;
  489. break;
  490. case G2D_MSK_BASE_ADDR:
  491. reg_type = REG_TYPE_MSK;
  492. break;
  493. default:
  494. reg_type = REG_TYPE_NONE;
  495. DRM_ERROR("Unknown register offset![%d]\n", reg_offset);
  496. break;
  497. }
  498. return reg_type;
  499. }
  500. static unsigned long g2d_get_buf_bpp(unsigned int format)
  501. {
  502. unsigned long bpp;
  503. switch (format) {
  504. case G2D_FMT_XRGB8888:
  505. case G2D_FMT_ARGB8888:
  506. bpp = 4;
  507. break;
  508. case G2D_FMT_RGB565:
  509. case G2D_FMT_XRGB1555:
  510. case G2D_FMT_ARGB1555:
  511. case G2D_FMT_XRGB4444:
  512. case G2D_FMT_ARGB4444:
  513. bpp = 2;
  514. break;
  515. case G2D_FMT_PACKED_RGB888:
  516. bpp = 3;
  517. break;
  518. default:
  519. bpp = 1;
  520. break;
  521. }
  522. return bpp;
  523. }
  524. static bool g2d_check_buf_desc_is_valid(struct g2d_buf_desc *buf_desc,
  525. enum g2d_reg_type reg_type,
  526. unsigned long size)
  527. {
  528. int width, height;
  529. unsigned long bpp, last_pos;
  530. /*
  531. * check source and destination buffers only.
  532. * so the others are always valid.
  533. */
  534. if (reg_type != REG_TYPE_SRC && reg_type != REG_TYPE_DST)
  535. return true;
  536. /* This check also makes sure that right_x > left_x. */
  537. width = (int)buf_desc->right_x - (int)buf_desc->left_x;
  538. if (width < G2D_LEN_MIN || width > G2D_LEN_MAX) {
  539. DRM_ERROR("width[%d] is out of range!\n", width);
  540. return false;
  541. }
  542. /* This check also makes sure that bottom_y > top_y. */
  543. height = (int)buf_desc->bottom_y - (int)buf_desc->top_y;
  544. if (height < G2D_LEN_MIN || height > G2D_LEN_MAX) {
  545. DRM_ERROR("height[%d] is out of range!\n", height);
  546. return false;
  547. }
  548. bpp = g2d_get_buf_bpp(buf_desc->format);
  549. /* Compute the position of the last byte that the engine accesses. */
  550. last_pos = ((unsigned long)buf_desc->bottom_y - 1) *
  551. (unsigned long)buf_desc->stride +
  552. (unsigned long)buf_desc->right_x * bpp - 1;
  553. /*
  554. * Since right_x > left_x and bottom_y > top_y we already know
  555. * that the first_pos < last_pos (first_pos being the position
  556. * of the first byte the engine accesses), it just remains to
  557. * check if last_pos is smaller then the buffer size.
  558. */
  559. if (last_pos >= size) {
  560. DRM_ERROR("last engine access position [%lu] "
  561. "is out of range [%lu]!\n", last_pos, size);
  562. return false;
  563. }
  564. return true;
  565. }
  566. static int g2d_map_cmdlist_gem(struct g2d_data *g2d,
  567. struct g2d_cmdlist_node *node,
  568. struct drm_device *drm_dev,
  569. struct drm_file *file)
  570. {
  571. struct g2d_cmdlist *cmdlist = node->cmdlist;
  572. struct g2d_buf_info *buf_info = &node->buf_info;
  573. int offset;
  574. int ret;
  575. int i;
  576. for (i = 0; i < buf_info->map_nr; i++) {
  577. struct g2d_buf_desc *buf_desc;
  578. enum g2d_reg_type reg_type;
  579. int reg_pos;
  580. unsigned long handle;
  581. dma_addr_t *addr;
  582. reg_pos = cmdlist->last - 2 * (i + 1);
  583. offset = cmdlist->data[reg_pos];
  584. handle = cmdlist->data[reg_pos + 1];
  585. reg_type = g2d_get_reg_type(offset);
  586. if (reg_type == REG_TYPE_NONE) {
  587. ret = -EFAULT;
  588. goto err;
  589. }
  590. buf_desc = &buf_info->descs[reg_type];
  591. if (buf_info->types[reg_type] == BUF_TYPE_GEM) {
  592. unsigned long size;
  593. size = exynos_drm_gem_get_size(drm_dev, handle, file);
  594. if (!size) {
  595. ret = -EFAULT;
  596. goto err;
  597. }
  598. if (!g2d_check_buf_desc_is_valid(buf_desc, reg_type,
  599. size)) {
  600. ret = -EFAULT;
  601. goto err;
  602. }
  603. addr = exynos_drm_gem_get_dma_addr(drm_dev, handle,
  604. file);
  605. if (IS_ERR(addr)) {
  606. ret = -EFAULT;
  607. goto err;
  608. }
  609. } else {
  610. struct drm_exynos_g2d_userptr g2d_userptr;
  611. if (copy_from_user(&g2d_userptr, (void __user *)handle,
  612. sizeof(struct drm_exynos_g2d_userptr))) {
  613. ret = -EFAULT;
  614. goto err;
  615. }
  616. if (!g2d_check_buf_desc_is_valid(buf_desc, reg_type,
  617. g2d_userptr.size)) {
  618. ret = -EFAULT;
  619. goto err;
  620. }
  621. addr = g2d_userptr_get_dma_addr(drm_dev,
  622. g2d_userptr.userptr,
  623. g2d_userptr.size,
  624. file,
  625. &handle);
  626. if (IS_ERR(addr)) {
  627. ret = -EFAULT;
  628. goto err;
  629. }
  630. }
  631. cmdlist->data[reg_pos + 1] = *addr;
  632. buf_info->reg_types[i] = reg_type;
  633. buf_info->handles[reg_type] = handle;
  634. }
  635. return 0;
  636. err:
  637. buf_info->map_nr = i;
  638. return ret;
  639. }
  640. static void g2d_unmap_cmdlist_gem(struct g2d_data *g2d,
  641. struct g2d_cmdlist_node *node,
  642. struct drm_file *filp)
  643. {
  644. struct exynos_drm_subdrv *subdrv = &g2d->subdrv;
  645. struct g2d_buf_info *buf_info = &node->buf_info;
  646. int i;
  647. for (i = 0; i < buf_info->map_nr; i++) {
  648. struct g2d_buf_desc *buf_desc;
  649. enum g2d_reg_type reg_type;
  650. unsigned long handle;
  651. reg_type = buf_info->reg_types[i];
  652. buf_desc = &buf_info->descs[reg_type];
  653. handle = buf_info->handles[reg_type];
  654. if (buf_info->types[reg_type] == BUF_TYPE_GEM)
  655. exynos_drm_gem_put_dma_addr(subdrv->drm_dev, handle,
  656. filp);
  657. else
  658. g2d_userptr_put_dma_addr(subdrv->drm_dev, handle,
  659. false);
  660. buf_info->reg_types[i] = REG_TYPE_NONE;
  661. buf_info->handles[reg_type] = 0;
  662. buf_info->types[reg_type] = 0;
  663. memset(buf_desc, 0x00, sizeof(*buf_desc));
  664. }
  665. buf_info->map_nr = 0;
  666. }
  667. static void g2d_dma_start(struct g2d_data *g2d,
  668. struct g2d_runqueue_node *runqueue_node)
  669. {
  670. struct g2d_cmdlist_node *node =
  671. list_first_entry(&runqueue_node->run_cmdlist,
  672. struct g2d_cmdlist_node, list);
  673. int ret;
  674. ret = pm_runtime_get_sync(g2d->dev);
  675. if (ret < 0)
  676. return;
  677. writel_relaxed(node->dma_addr, g2d->regs + G2D_DMA_SFR_BASE_ADDR);
  678. writel_relaxed(G2D_DMA_START, g2d->regs + G2D_DMA_COMMAND);
  679. }
  680. static struct g2d_runqueue_node *g2d_get_runqueue_node(struct g2d_data *g2d)
  681. {
  682. struct g2d_runqueue_node *runqueue_node;
  683. if (list_empty(&g2d->runqueue))
  684. return NULL;
  685. runqueue_node = list_first_entry(&g2d->runqueue,
  686. struct g2d_runqueue_node, list);
  687. list_del_init(&runqueue_node->list);
  688. return runqueue_node;
  689. }
  690. static void g2d_free_runqueue_node(struct g2d_data *g2d,
  691. struct g2d_runqueue_node *runqueue_node)
  692. {
  693. struct g2d_cmdlist_node *node;
  694. if (!runqueue_node)
  695. return;
  696. mutex_lock(&g2d->cmdlist_mutex);
  697. /*
  698. * commands in run_cmdlist have been completed so unmap all gem
  699. * objects in each command node so that they are unreferenced.
  700. */
  701. list_for_each_entry(node, &runqueue_node->run_cmdlist, list)
  702. g2d_unmap_cmdlist_gem(g2d, node, runqueue_node->filp);
  703. list_splice_tail_init(&runqueue_node->run_cmdlist, &g2d->free_cmdlist);
  704. mutex_unlock(&g2d->cmdlist_mutex);
  705. kmem_cache_free(g2d->runqueue_slab, runqueue_node);
  706. }
  707. static void g2d_exec_runqueue(struct g2d_data *g2d)
  708. {
  709. g2d->runqueue_node = g2d_get_runqueue_node(g2d);
  710. if (g2d->runqueue_node)
  711. g2d_dma_start(g2d, g2d->runqueue_node);
  712. }
  713. static void g2d_runqueue_worker(struct work_struct *work)
  714. {
  715. struct g2d_data *g2d = container_of(work, struct g2d_data,
  716. runqueue_work);
  717. mutex_lock(&g2d->runqueue_mutex);
  718. pm_runtime_put_sync(g2d->dev);
  719. complete(&g2d->runqueue_node->complete);
  720. if (g2d->runqueue_node->async)
  721. g2d_free_runqueue_node(g2d, g2d->runqueue_node);
  722. if (g2d->suspended)
  723. g2d->runqueue_node = NULL;
  724. else
  725. g2d_exec_runqueue(g2d);
  726. mutex_unlock(&g2d->runqueue_mutex);
  727. }
  728. static void g2d_finish_event(struct g2d_data *g2d, u32 cmdlist_no)
  729. {
  730. struct drm_device *drm_dev = g2d->subdrv.drm_dev;
  731. struct g2d_runqueue_node *runqueue_node = g2d->runqueue_node;
  732. struct drm_exynos_pending_g2d_event *e;
  733. struct timeval now;
  734. if (list_empty(&runqueue_node->event_list))
  735. return;
  736. e = list_first_entry(&runqueue_node->event_list,
  737. struct drm_exynos_pending_g2d_event, base.link);
  738. do_gettimeofday(&now);
  739. e->event.tv_sec = now.tv_sec;
  740. e->event.tv_usec = now.tv_usec;
  741. e->event.cmdlist_no = cmdlist_no;
  742. drm_send_event(drm_dev, &e->base);
  743. }
  744. static irqreturn_t g2d_irq_handler(int irq, void *dev_id)
  745. {
  746. struct g2d_data *g2d = dev_id;
  747. u32 pending;
  748. pending = readl_relaxed(g2d->regs + G2D_INTC_PEND);
  749. if (pending)
  750. writel_relaxed(pending, g2d->regs + G2D_INTC_PEND);
  751. if (pending & G2D_INTP_GCMD_FIN) {
  752. u32 cmdlist_no = readl_relaxed(g2d->regs + G2D_DMA_STATUS);
  753. cmdlist_no = (cmdlist_no & G2D_DMA_LIST_DONE_COUNT) >>
  754. G2D_DMA_LIST_DONE_COUNT_OFFSET;
  755. g2d_finish_event(g2d, cmdlist_no);
  756. writel_relaxed(0, g2d->regs + G2D_DMA_HOLD_CMD);
  757. if (!(pending & G2D_INTP_ACMD_FIN)) {
  758. writel_relaxed(G2D_DMA_CONTINUE,
  759. g2d->regs + G2D_DMA_COMMAND);
  760. }
  761. }
  762. if (pending & G2D_INTP_ACMD_FIN)
  763. queue_work(g2d->g2d_workq, &g2d->runqueue_work);
  764. return IRQ_HANDLED;
  765. }
  766. static int g2d_check_reg_offset(struct device *dev,
  767. struct g2d_cmdlist_node *node,
  768. int nr, bool for_addr)
  769. {
  770. struct g2d_cmdlist *cmdlist = node->cmdlist;
  771. int reg_offset;
  772. int index;
  773. int i;
  774. for (i = 0; i < nr; i++) {
  775. struct g2d_buf_info *buf_info = &node->buf_info;
  776. struct g2d_buf_desc *buf_desc;
  777. enum g2d_reg_type reg_type;
  778. unsigned long value;
  779. index = cmdlist->last - 2 * (i + 1);
  780. reg_offset = cmdlist->data[index] & ~0xfffff000;
  781. if (reg_offset < G2D_VALID_START || reg_offset > G2D_VALID_END)
  782. goto err;
  783. if (reg_offset % 4)
  784. goto err;
  785. switch (reg_offset) {
  786. case G2D_SRC_BASE_ADDR:
  787. case G2D_SRC_PLANE2_BASE_ADDR:
  788. case G2D_DST_BASE_ADDR:
  789. case G2D_DST_PLANE2_BASE_ADDR:
  790. case G2D_PAT_BASE_ADDR:
  791. case G2D_MSK_BASE_ADDR:
  792. if (!for_addr)
  793. goto err;
  794. reg_type = g2d_get_reg_type(reg_offset);
  795. /* check userptr buffer type. */
  796. if ((cmdlist->data[index] & ~0x7fffffff) >> 31) {
  797. buf_info->types[reg_type] = BUF_TYPE_USERPTR;
  798. cmdlist->data[index] &= ~G2D_BUF_USERPTR;
  799. } else
  800. buf_info->types[reg_type] = BUF_TYPE_GEM;
  801. break;
  802. case G2D_SRC_STRIDE:
  803. case G2D_DST_STRIDE:
  804. if (for_addr)
  805. goto err;
  806. reg_type = g2d_get_reg_type(reg_offset);
  807. buf_desc = &buf_info->descs[reg_type];
  808. buf_desc->stride = cmdlist->data[index + 1];
  809. break;
  810. case G2D_SRC_COLOR_MODE:
  811. case G2D_DST_COLOR_MODE:
  812. if (for_addr)
  813. goto err;
  814. reg_type = g2d_get_reg_type(reg_offset);
  815. buf_desc = &buf_info->descs[reg_type];
  816. value = cmdlist->data[index + 1];
  817. buf_desc->format = value & 0xf;
  818. break;
  819. case G2D_SRC_LEFT_TOP:
  820. case G2D_DST_LEFT_TOP:
  821. if (for_addr)
  822. goto err;
  823. reg_type = g2d_get_reg_type(reg_offset);
  824. buf_desc = &buf_info->descs[reg_type];
  825. value = cmdlist->data[index + 1];
  826. buf_desc->left_x = value & 0x1fff;
  827. buf_desc->top_y = (value & 0x1fff0000) >> 16;
  828. break;
  829. case G2D_SRC_RIGHT_BOTTOM:
  830. case G2D_DST_RIGHT_BOTTOM:
  831. if (for_addr)
  832. goto err;
  833. reg_type = g2d_get_reg_type(reg_offset);
  834. buf_desc = &buf_info->descs[reg_type];
  835. value = cmdlist->data[index + 1];
  836. buf_desc->right_x = value & 0x1fff;
  837. buf_desc->bottom_y = (value & 0x1fff0000) >> 16;
  838. break;
  839. default:
  840. if (for_addr)
  841. goto err;
  842. break;
  843. }
  844. }
  845. return 0;
  846. err:
  847. dev_err(dev, "Bad register offset: 0x%lx\n", cmdlist->data[index]);
  848. return -EINVAL;
  849. }
  850. /* ioctl functions */
  851. int exynos_g2d_get_ver_ioctl(struct drm_device *drm_dev, void *data,
  852. struct drm_file *file)
  853. {
  854. struct drm_exynos_file_private *file_priv = file->driver_priv;
  855. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  856. struct device *dev;
  857. struct g2d_data *g2d;
  858. struct drm_exynos_g2d_get_ver *ver = data;
  859. if (!g2d_priv)
  860. return -ENODEV;
  861. dev = g2d_priv->dev;
  862. if (!dev)
  863. return -ENODEV;
  864. g2d = dev_get_drvdata(dev);
  865. if (!g2d)
  866. return -EFAULT;
  867. ver->major = G2D_HW_MAJOR_VER;
  868. ver->minor = G2D_HW_MINOR_VER;
  869. return 0;
  870. }
  871. int exynos_g2d_set_cmdlist_ioctl(struct drm_device *drm_dev, void *data,
  872. struct drm_file *file)
  873. {
  874. struct drm_exynos_file_private *file_priv = file->driver_priv;
  875. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  876. struct device *dev;
  877. struct g2d_data *g2d;
  878. struct drm_exynos_g2d_set_cmdlist *req = data;
  879. struct drm_exynos_g2d_cmd *cmd;
  880. struct drm_exynos_pending_g2d_event *e;
  881. struct g2d_cmdlist_node *node;
  882. struct g2d_cmdlist *cmdlist;
  883. int size;
  884. int ret;
  885. if (!g2d_priv)
  886. return -ENODEV;
  887. dev = g2d_priv->dev;
  888. if (!dev)
  889. return -ENODEV;
  890. g2d = dev_get_drvdata(dev);
  891. if (!g2d)
  892. return -EFAULT;
  893. node = g2d_get_cmdlist(g2d);
  894. if (!node)
  895. return -ENOMEM;
  896. node->event = NULL;
  897. if (req->event_type != G2D_EVENT_NOT) {
  898. e = kzalloc(sizeof(*node->event), GFP_KERNEL);
  899. if (!e) {
  900. ret = -ENOMEM;
  901. goto err;
  902. }
  903. e->event.base.type = DRM_EXYNOS_G2D_EVENT;
  904. e->event.base.length = sizeof(e->event);
  905. e->event.user_data = req->user_data;
  906. ret = drm_event_reserve_init(drm_dev, file, &e->base, &e->event.base);
  907. if (ret) {
  908. kfree(e);
  909. goto err;
  910. }
  911. node->event = e;
  912. }
  913. cmdlist = node->cmdlist;
  914. cmdlist->last = 0;
  915. /*
  916. * If don't clear SFR registers, the cmdlist is affected by register
  917. * values of previous cmdlist. G2D hw executes SFR clear command and
  918. * a next command at the same time then the next command is ignored and
  919. * is executed rightly from next next command, so needs a dummy command
  920. * to next command of SFR clear command.
  921. */
  922. cmdlist->data[cmdlist->last++] = G2D_SOFT_RESET;
  923. cmdlist->data[cmdlist->last++] = G2D_SFRCLEAR;
  924. cmdlist->data[cmdlist->last++] = G2D_SRC_BASE_ADDR;
  925. cmdlist->data[cmdlist->last++] = 0;
  926. /*
  927. * 'LIST_HOLD' command should be set to the DMA_HOLD_CMD_REG
  928. * and GCF bit should be set to INTEN register if user wants
  929. * G2D interrupt event once current command list execution is
  930. * finished.
  931. * Otherwise only ACF bit should be set to INTEN register so
  932. * that one interrupt is occurred after all command lists
  933. * have been completed.
  934. */
  935. if (node->event) {
  936. cmdlist->data[cmdlist->last++] = G2D_INTEN;
  937. cmdlist->data[cmdlist->last++] = G2D_INTEN_ACF | G2D_INTEN_GCF;
  938. cmdlist->data[cmdlist->last++] = G2D_DMA_HOLD_CMD;
  939. cmdlist->data[cmdlist->last++] = G2D_LIST_HOLD;
  940. } else {
  941. cmdlist->data[cmdlist->last++] = G2D_INTEN;
  942. cmdlist->data[cmdlist->last++] = G2D_INTEN_ACF;
  943. }
  944. /* Check size of cmdlist: last 2 is about G2D_BITBLT_START */
  945. size = cmdlist->last + req->cmd_nr * 2 + req->cmd_buf_nr * 2 + 2;
  946. if (size > G2D_CMDLIST_DATA_NUM) {
  947. dev_err(dev, "cmdlist size is too big\n");
  948. ret = -EINVAL;
  949. goto err_free_event;
  950. }
  951. cmd = (struct drm_exynos_g2d_cmd *)(unsigned long)req->cmd;
  952. if (copy_from_user(cmdlist->data + cmdlist->last,
  953. (void __user *)cmd,
  954. sizeof(*cmd) * req->cmd_nr)) {
  955. ret = -EFAULT;
  956. goto err_free_event;
  957. }
  958. cmdlist->last += req->cmd_nr * 2;
  959. ret = g2d_check_reg_offset(dev, node, req->cmd_nr, false);
  960. if (ret < 0)
  961. goto err_free_event;
  962. node->buf_info.map_nr = req->cmd_buf_nr;
  963. if (req->cmd_buf_nr) {
  964. struct drm_exynos_g2d_cmd *cmd_buf;
  965. cmd_buf = (struct drm_exynos_g2d_cmd *)
  966. (unsigned long)req->cmd_buf;
  967. if (copy_from_user(cmdlist->data + cmdlist->last,
  968. (void __user *)cmd_buf,
  969. sizeof(*cmd_buf) * req->cmd_buf_nr)) {
  970. ret = -EFAULT;
  971. goto err_free_event;
  972. }
  973. cmdlist->last += req->cmd_buf_nr * 2;
  974. ret = g2d_check_reg_offset(dev, node, req->cmd_buf_nr, true);
  975. if (ret < 0)
  976. goto err_free_event;
  977. ret = g2d_map_cmdlist_gem(g2d, node, drm_dev, file);
  978. if (ret < 0)
  979. goto err_unmap;
  980. }
  981. cmdlist->data[cmdlist->last++] = G2D_BITBLT_START;
  982. cmdlist->data[cmdlist->last++] = G2D_START_BITBLT;
  983. /* head */
  984. cmdlist->head = cmdlist->last / 2;
  985. /* tail */
  986. cmdlist->data[cmdlist->last] = 0;
  987. g2d_add_cmdlist_to_inuse(g2d_priv, node);
  988. return 0;
  989. err_unmap:
  990. g2d_unmap_cmdlist_gem(g2d, node, file);
  991. err_free_event:
  992. if (node->event)
  993. drm_event_cancel_free(drm_dev, &node->event->base);
  994. err:
  995. g2d_put_cmdlist(g2d, node);
  996. return ret;
  997. }
  998. int exynos_g2d_exec_ioctl(struct drm_device *drm_dev, void *data,
  999. struct drm_file *file)
  1000. {
  1001. struct drm_exynos_file_private *file_priv = file->driver_priv;
  1002. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  1003. struct device *dev;
  1004. struct g2d_data *g2d;
  1005. struct drm_exynos_g2d_exec *req = data;
  1006. struct g2d_runqueue_node *runqueue_node;
  1007. struct list_head *run_cmdlist;
  1008. struct list_head *event_list;
  1009. if (!g2d_priv)
  1010. return -ENODEV;
  1011. dev = g2d_priv->dev;
  1012. if (!dev)
  1013. return -ENODEV;
  1014. g2d = dev_get_drvdata(dev);
  1015. if (!g2d)
  1016. return -EFAULT;
  1017. runqueue_node = kmem_cache_alloc(g2d->runqueue_slab, GFP_KERNEL);
  1018. if (!runqueue_node) {
  1019. dev_err(dev, "failed to allocate memory\n");
  1020. return -ENOMEM;
  1021. }
  1022. run_cmdlist = &runqueue_node->run_cmdlist;
  1023. event_list = &runqueue_node->event_list;
  1024. INIT_LIST_HEAD(run_cmdlist);
  1025. INIT_LIST_HEAD(event_list);
  1026. init_completion(&runqueue_node->complete);
  1027. runqueue_node->async = req->async;
  1028. list_splice_init(&g2d_priv->inuse_cmdlist, run_cmdlist);
  1029. list_splice_init(&g2d_priv->event_list, event_list);
  1030. if (list_empty(run_cmdlist)) {
  1031. dev_err(dev, "there is no inuse cmdlist\n");
  1032. kmem_cache_free(g2d->runqueue_slab, runqueue_node);
  1033. return -EPERM;
  1034. }
  1035. mutex_lock(&g2d->runqueue_mutex);
  1036. runqueue_node->pid = current->pid;
  1037. runqueue_node->filp = file;
  1038. list_add_tail(&runqueue_node->list, &g2d->runqueue);
  1039. if (!g2d->runqueue_node)
  1040. g2d_exec_runqueue(g2d);
  1041. mutex_unlock(&g2d->runqueue_mutex);
  1042. if (runqueue_node->async)
  1043. goto out;
  1044. wait_for_completion(&runqueue_node->complete);
  1045. g2d_free_runqueue_node(g2d, runqueue_node);
  1046. out:
  1047. return 0;
  1048. }
  1049. static int g2d_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
  1050. {
  1051. struct g2d_data *g2d;
  1052. int ret;
  1053. g2d = dev_get_drvdata(dev);
  1054. if (!g2d)
  1055. return -EFAULT;
  1056. /* allocate dma-aware cmdlist buffer. */
  1057. ret = g2d_init_cmdlist(g2d);
  1058. if (ret < 0) {
  1059. dev_err(dev, "cmdlist init failed\n");
  1060. return ret;
  1061. }
  1062. ret = drm_iommu_attach_device(drm_dev, dev);
  1063. if (ret < 0) {
  1064. dev_err(dev, "failed to enable iommu.\n");
  1065. g2d_fini_cmdlist(g2d);
  1066. }
  1067. return ret;
  1068. }
  1069. static void g2d_subdrv_remove(struct drm_device *drm_dev, struct device *dev)
  1070. {
  1071. drm_iommu_detach_device(drm_dev, dev);
  1072. }
  1073. static int g2d_open(struct drm_device *drm_dev, struct device *dev,
  1074. struct drm_file *file)
  1075. {
  1076. struct drm_exynos_file_private *file_priv = file->driver_priv;
  1077. struct exynos_drm_g2d_private *g2d_priv;
  1078. g2d_priv = kzalloc(sizeof(*g2d_priv), GFP_KERNEL);
  1079. if (!g2d_priv)
  1080. return -ENOMEM;
  1081. g2d_priv->dev = dev;
  1082. file_priv->g2d_priv = g2d_priv;
  1083. INIT_LIST_HEAD(&g2d_priv->inuse_cmdlist);
  1084. INIT_LIST_HEAD(&g2d_priv->event_list);
  1085. INIT_LIST_HEAD(&g2d_priv->userptr_list);
  1086. return 0;
  1087. }
  1088. static void g2d_close(struct drm_device *drm_dev, struct device *dev,
  1089. struct drm_file *file)
  1090. {
  1091. struct drm_exynos_file_private *file_priv = file->driver_priv;
  1092. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  1093. struct g2d_data *g2d;
  1094. struct g2d_cmdlist_node *node, *n;
  1095. if (!dev)
  1096. return;
  1097. g2d = dev_get_drvdata(dev);
  1098. if (!g2d)
  1099. return;
  1100. mutex_lock(&g2d->cmdlist_mutex);
  1101. list_for_each_entry_safe(node, n, &g2d_priv->inuse_cmdlist, list) {
  1102. /*
  1103. * unmap all gem objects not completed.
  1104. *
  1105. * P.S. if current process was terminated forcely then
  1106. * there may be some commands in inuse_cmdlist so unmap
  1107. * them.
  1108. */
  1109. g2d_unmap_cmdlist_gem(g2d, node, file);
  1110. list_move_tail(&node->list, &g2d->free_cmdlist);
  1111. }
  1112. mutex_unlock(&g2d->cmdlist_mutex);
  1113. /* release all g2d_userptr in pool. */
  1114. g2d_userptr_free_all(drm_dev, g2d, file);
  1115. kfree(file_priv->g2d_priv);
  1116. }
  1117. static int g2d_probe(struct platform_device *pdev)
  1118. {
  1119. struct device *dev = &pdev->dev;
  1120. struct resource *res;
  1121. struct g2d_data *g2d;
  1122. struct exynos_drm_subdrv *subdrv;
  1123. int ret;
  1124. g2d = devm_kzalloc(dev, sizeof(*g2d), GFP_KERNEL);
  1125. if (!g2d)
  1126. return -ENOMEM;
  1127. g2d->runqueue_slab = kmem_cache_create("g2d_runqueue_slab",
  1128. sizeof(struct g2d_runqueue_node), 0, 0, NULL);
  1129. if (!g2d->runqueue_slab)
  1130. return -ENOMEM;
  1131. g2d->dev = dev;
  1132. g2d->g2d_workq = create_singlethread_workqueue("g2d");
  1133. if (!g2d->g2d_workq) {
  1134. dev_err(dev, "failed to create workqueue\n");
  1135. ret = -EINVAL;
  1136. goto err_destroy_slab;
  1137. }
  1138. INIT_WORK(&g2d->runqueue_work, g2d_runqueue_worker);
  1139. INIT_LIST_HEAD(&g2d->free_cmdlist);
  1140. INIT_LIST_HEAD(&g2d->runqueue);
  1141. mutex_init(&g2d->cmdlist_mutex);
  1142. mutex_init(&g2d->runqueue_mutex);
  1143. g2d->gate_clk = devm_clk_get(dev, "fimg2d");
  1144. if (IS_ERR(g2d->gate_clk)) {
  1145. dev_err(dev, "failed to get gate clock\n");
  1146. ret = PTR_ERR(g2d->gate_clk);
  1147. goto err_destroy_workqueue;
  1148. }
  1149. pm_runtime_enable(dev);
  1150. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1151. g2d->regs = devm_ioremap_resource(dev, res);
  1152. if (IS_ERR(g2d->regs)) {
  1153. ret = PTR_ERR(g2d->regs);
  1154. goto err_put_clk;
  1155. }
  1156. g2d->irq = platform_get_irq(pdev, 0);
  1157. if (g2d->irq < 0) {
  1158. dev_err(dev, "failed to get irq\n");
  1159. ret = g2d->irq;
  1160. goto err_put_clk;
  1161. }
  1162. ret = devm_request_irq(dev, g2d->irq, g2d_irq_handler, 0,
  1163. "drm_g2d", g2d);
  1164. if (ret < 0) {
  1165. dev_err(dev, "irq request failed\n");
  1166. goto err_put_clk;
  1167. }
  1168. g2d->max_pool = MAX_POOL;
  1169. platform_set_drvdata(pdev, g2d);
  1170. subdrv = &g2d->subdrv;
  1171. subdrv->dev = dev;
  1172. subdrv->probe = g2d_subdrv_probe;
  1173. subdrv->remove = g2d_subdrv_remove;
  1174. subdrv->open = g2d_open;
  1175. subdrv->close = g2d_close;
  1176. ret = exynos_drm_subdrv_register(subdrv);
  1177. if (ret < 0) {
  1178. dev_err(dev, "failed to register drm g2d device\n");
  1179. goto err_put_clk;
  1180. }
  1181. dev_info(dev, "The exynos g2d(ver %d.%d) successfully probed\n",
  1182. G2D_HW_MAJOR_VER, G2D_HW_MINOR_VER);
  1183. return 0;
  1184. err_put_clk:
  1185. pm_runtime_disable(dev);
  1186. err_destroy_workqueue:
  1187. destroy_workqueue(g2d->g2d_workq);
  1188. err_destroy_slab:
  1189. kmem_cache_destroy(g2d->runqueue_slab);
  1190. return ret;
  1191. }
  1192. static int g2d_remove(struct platform_device *pdev)
  1193. {
  1194. struct g2d_data *g2d = platform_get_drvdata(pdev);
  1195. cancel_work_sync(&g2d->runqueue_work);
  1196. exynos_drm_subdrv_unregister(&g2d->subdrv);
  1197. while (g2d->runqueue_node) {
  1198. g2d_free_runqueue_node(g2d, g2d->runqueue_node);
  1199. g2d->runqueue_node = g2d_get_runqueue_node(g2d);
  1200. }
  1201. pm_runtime_disable(&pdev->dev);
  1202. g2d_fini_cmdlist(g2d);
  1203. destroy_workqueue(g2d->g2d_workq);
  1204. kmem_cache_destroy(g2d->runqueue_slab);
  1205. return 0;
  1206. }
  1207. #ifdef CONFIG_PM_SLEEP
  1208. static int g2d_suspend(struct device *dev)
  1209. {
  1210. struct g2d_data *g2d = dev_get_drvdata(dev);
  1211. mutex_lock(&g2d->runqueue_mutex);
  1212. g2d->suspended = true;
  1213. mutex_unlock(&g2d->runqueue_mutex);
  1214. while (g2d->runqueue_node)
  1215. /* FIXME: good range? */
  1216. usleep_range(500, 1000);
  1217. flush_work(&g2d->runqueue_work);
  1218. return 0;
  1219. }
  1220. static int g2d_resume(struct device *dev)
  1221. {
  1222. struct g2d_data *g2d = dev_get_drvdata(dev);
  1223. g2d->suspended = false;
  1224. g2d_exec_runqueue(g2d);
  1225. return 0;
  1226. }
  1227. #endif
  1228. #ifdef CONFIG_PM
  1229. static int g2d_runtime_suspend(struct device *dev)
  1230. {
  1231. struct g2d_data *g2d = dev_get_drvdata(dev);
  1232. clk_disable_unprepare(g2d->gate_clk);
  1233. return 0;
  1234. }
  1235. static int g2d_runtime_resume(struct device *dev)
  1236. {
  1237. struct g2d_data *g2d = dev_get_drvdata(dev);
  1238. int ret;
  1239. ret = clk_prepare_enable(g2d->gate_clk);
  1240. if (ret < 0)
  1241. dev_warn(dev, "failed to enable clock.\n");
  1242. return ret;
  1243. }
  1244. #endif
  1245. static const struct dev_pm_ops g2d_pm_ops = {
  1246. SET_SYSTEM_SLEEP_PM_OPS(g2d_suspend, g2d_resume)
  1247. SET_RUNTIME_PM_OPS(g2d_runtime_suspend, g2d_runtime_resume, NULL)
  1248. };
  1249. static const struct of_device_id exynos_g2d_match[] = {
  1250. { .compatible = "samsung,exynos5250-g2d" },
  1251. { .compatible = "samsung,exynos4212-g2d" },
  1252. {},
  1253. };
  1254. MODULE_DEVICE_TABLE(of, exynos_g2d_match);
  1255. struct platform_driver g2d_driver = {
  1256. .probe = g2d_probe,
  1257. .remove = g2d_remove,
  1258. .driver = {
  1259. .name = "s5p-g2d",
  1260. .owner = THIS_MODULE,
  1261. .pm = &g2d_pm_ops,
  1262. .of_match_table = exynos_g2d_match,
  1263. },
  1264. };