 Peter De-Schrijver
|
633e79650b
clk: tegra: Add sdmmc mux divider clock
|
7 лет назад |
|
Peter De Schrijver
|
cb3ac5947a
clk: tegra: Refactor fractional divider calculation
|
7 лет назад |
 Aapo Vienamo
|
0cbb61a313
clk: tegra: Fix includes required by fence_udelay()
|
7 лет назад |
 Dmitry Osipenko
|
5d797111af
clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20
|
7 лет назад |
|
Peter De Schrijver
|
cbfc8d0a85
clk: tegra: add fence_delay for clock registers
|
7 лет назад |
 Thierry Reding
|
8be95190da
clk: tegra: Add peripheral clock registration helper
|
8 лет назад |
 Alex Frid
|
ac99afe55a
clk: tegra: Re-factor T210 PLLX registration
|
8 лет назад |
|
Thierry Reding
|
39133505ca
clk: tegra: Fix build warnings on Tegra20/Tegra30
|
8 лет назад |
|
Peter De Schrijver
|
e827ba1840
clk: tegra: Add super clock mux/divider
|
8 лет назад |
|
Peter De Schrijver
|
9e8c93edd2
clk: tegra: Fix constness for peripheral clocks
|
8 лет назад |
|
Peter De Schrijver
|
e589376dab
clk: tegra: Fix type for m field
|
8 лет назад |
 Andrew Bresticker
|
15d68e8c2e
clk: tegra: Initialize UTMI PLL when enabling PLLU
|
9 лет назад |
 Rhyland Klein
|
926655f929
clk: tegra: Fix pllre Tegra210 and add pll_re_out1
|
9 лет назад |
|
Thierry Reding
|
1ec7032ad5
clk: tegra: Add fixed factor peripheral clock type
|
10 лет назад |
|
Thierry Reding
|
7e14f22305
clk: tegra: Constify peripheral clock registers
|
10 лет назад |
|
Rhyland Klein
|
6b301a059e
clk: tegra: Add support for Tegra210 clocks
|
10 лет назад |
 Bill Huang
|
139fd30943
clk: tegra: Add Super Gen5 Logic
|
10 лет назад |
|
Bill Huang
|
0ef9db6cf2
clk: tegra: pll: Add logic for SS
|
10 лет назад |
|
Rhyland Klein
|
17e9273a9e
clk: tegra: pll: Add dyn_ramp callback
|
10 лет назад |
|
Bill Huang
|
b985114e2f
clk: tegra: pll: Add Set_default logic
|
10 лет назад |
|
Bill Huang
|
b5512b45d5
clk: tegra: pll: Adjust vco_min if SDM present
|
10 лет назад |
|
Rhyland Klein
|
6929715cf6
clk: tegra: pll: Add support for PLLMB for Tegra210
|
10 лет назад |
|
Rhyland Klein
|
dd322f047d
clk: tegra: pll: Add specialized logic for Tegra210
|
10 лет назад |
|
Bill Huang
|
fde207eb15
clk: tegra: pll: Add code to handle if resets are supported by PLL
|
10 лет назад |
|
Rhyland Klein
|
407254da29
clk: tegra: pll: Add logic for out-of-table rates for T210
|
10 лет назад |
|
Rhyland Klein
|
d907f4b4a1
clk: tegra: pll: Add logic for handling SDM data
|
10 лет назад |
|
Bill Huang
|
56fd27b31f
clk: tegra: pll: Change misc_reg count from 3 to 6
|
10 лет назад |
|
Rhyland Klein
|
6583a6309e
clk: tegra: pll: Add tegra_pll_wait_for_lock to clk header
|
10 лет назад |
|
Thierry Reding
|
385f9adf62
clk: tegra: Constify pdiv-to-hw mappings
|
9 лет назад |
|
Rhyland Klein
|
88d909bedf
clk: tegra: Modify tegra_audio_clk_init to accept more plls
|
10 лет назад |
