 Dmitry Osipenko
|
5d797111af
clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20
|
%!s(int64=7) %!d(string=hai) anos |
|
Dmitry Osipenko
|
c485ad63ab
clk: tegra: Specify VDE clock rate
|
%!s(int64=7) %!d(string=hai) anos |
|
Dmitry Osipenko
|
2dcabf053c
clk: tegra: Mark HCLK, SCLK and EMC as critical
|
%!s(int64=7) %!d(string=hai) anos |
 Thierry Reding
|
1d7e2c8e54
clk: tegra: Use tegra_clk_register_periph_data()
|
%!s(int64=8) %!d(string=hai) anos |
 Peter De Schrijver
|
bfa34832df
clk: tegra: Add CEC clock
|
%!s(int64=8) %!d(string=hai) anos |
 Vince Hsu
|
af7c388a9c
clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2
|
%!s(int64=9) %!d(string=hai) anos |
 Andrew Bresticker
|
15d68e8c2e
clk: tegra: Initialize UTMI PLL when enabling PLLU
|
%!s(int64=9) %!d(string=hai) anos |
|
Thierry Reding
|
07314fc108
clk: tegra: Special-case mipi-cal parent on Tegra114
|
%!s(int64=10) %!d(string=hai) anos |
 Stephen Boyd
|
f6da46a307
clk: tegra: Remove CLK_IS_ROOT
|
%!s(int64=9) %!d(string=hai) anos |
 Danny Huang
|
267b62a969
clk: tegra: pll: Update PLLM handling
|
%!s(int64=10) %!d(string=hai) anos |
 Rhyland Klein
|
86c679a522
clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate
|
%!s(int64=10) %!d(string=hai) anos |
|
Rhyland Klein
|
3706b43629
clk: tegra: pll: Don't unconditionally set LOCK flags
|
%!s(int64=10) %!d(string=hai) anos |
|
Thierry Reding
|
385f9adf62
clk: tegra: Constify pdiv-to-hw mappings
|
%!s(int64=9) %!d(string=hai) anos |
|
Thierry Reding
|
8d99704fde
clk: tegra: Format tables consistently
|
%!s(int64=10) %!d(string=hai) anos |
|
Thierry Reding
|
e52d7c04bb
clk: tegra: Miscellaneous coding style cleanups
|
%!s(int64=10) %!d(string=hai) anos |
|
Thierry Reding
|
c4947e364b
clk: tegra: Fix 26 MHz oscillator frequency
|
%!s(int64=10) %!d(string=hai) anos |
|
Rhyland Klein
|
88d909bedf
clk: tegra: Modify tegra_audio_clk_init to accept more plls
|
%!s(int64=10) %!d(string=hai) anos |
|
Stephen Boyd
|
584ac4e935
clk: tegra: Properly include clk.h
|
%!s(int64=10) %!d(string=hai) anos |
|
Thierry Reding
|
a84724a1c3
clk: tegra: Use generic tegra_osc_clk_init() on Tegra114
|
%!s(int64=10) %!d(string=hai) anos |
|
Thierry Reding
|
6bb18c532d
clk: tegra: Various whitespace cleanups
|
%!s(int64=11) %!d(string=hai) anos |
 Mark Zhang
|
b270491eb9
clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
|
%!s(int64=10) %!d(string=hai) anos |
|
Thierry Reding
|
4f4f85fa0b
clk: tegra: Implement memory-controller clock
|
%!s(int64=11) %!d(string=hai) anos |
|
Peter De Schrijver
|
167d5366c4
clk: tegra: fix vi_sensor clocks on Tegra124
|
%!s(int64=11) %!d(string=hai) anos |
|
Andrew Bresticker
|
4a7f10d67b
clk: tegra: Initialize xusb clocks
|
%!s(int64=11) %!d(string=hai) anos |
|
Andrew Bresticker
|
5c992afcf8
clk: tegra: Fix xusb_hs_src clock hierarchy
|
%!s(int64=11) %!d(string=hai) anos |
|
Andrew Bresticker
|
20e7c323ab
clk: tegra: fix sdmmc clks on Tegra1x4
|
%!s(int64=11) %!d(string=hai) anos |
 Stephen Warren
|
6d5b988e7d
clk: tegra: implement a reset driver
|
%!s(int64=12) %!d(string=hai) anos |
 Thierry Reding
|
39409aa424
clk: tegra: Initialize DSI low-power clocks
|
%!s(int64=12) %!d(string=hai) anos |
 Alexandre Courbot
|
5ab5d4048e
clk: tegra: add FUSE clock device
|
%!s(int64=12) %!d(string=hai) anos |
 Mikko Perttunen
|
77f7173034
clk: tegra114: Initialize clocks needed for HDMI
|
%!s(int64=12) %!d(string=hai) anos |
