 Shawn Lin
|
4b0556a441
clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228
|
%!s(int64=7) %!d(string=hai) anos |
 Elaine Zhang
|
fe53230cf2
clk: rockchip: add rk3228 SCLK_SDIO_SRC clk id
|
%!s(int64=8) %!d(string=hai) anos |
|
Elaine Zhang
|
f18c0994cd
clk: rockchip: mark noc and some special clk as critical on rk3228
|
%!s(int64=8) %!d(string=hai) anos |
|
Elaine Zhang
|
5d2595627e
clk: rockchip: export more rk3228 clocks ids
|
%!s(int64=8) %!d(string=hai) anos |
|
Elaine Zhang
|
f88b8e7365
clk: rockchip: fix up the RK3228 clk cpu setting table
|
%!s(int64=8) %!d(string=hai) anos |
 Xing Zheng
|
6e3732a2be
clk: rockchip: export rk3228 MAC clocks
|
%!s(int64=9) %!d(string=hai) anos |
|
Xing Zheng
|
09f684226d
clk: rockchip: rename rk3228 sclk_macphy_50m to sclk_mac_extclk
|
%!s(int64=9) %!d(string=hai) anos |
|
Xing Zheng
|
a45c072bb4
clk: rockchip: export rk3228 audio clocks
|
%!s(int64=9) %!d(string=hai) anos |
|
Xing Zheng
|
cb87df58bc
clk: rockchip: include rk3228 downstream muxes into fractional dividers
|
%!s(int64=9) %!d(string=hai) anos |
|
Xing Zheng
|
67de7901c4
clk: rockchip: fix incorrect rk3228 clock registers
|
%!s(int64=9) %!d(string=hai) anos |
|
Shawn Lin
|
1d003eb080
clk: rockchip: release io resource when failing to init clk
|
%!s(int64=9) %!d(string=hai) anos |
|
Xing Zheng
|
ef1d9feecc
clk: rockchip: Add support for multiple clock providers
|
%!s(int64=9) %!d(string=hai) anos |
|
Xing Zheng
|
268aebaa24
clk: rockchip: allow varying mux parameters for cpuclk pll-sources
|
%!s(int64=9) %!d(string=hai) anos |
 Yakir Yang
|
bdc7deec2f
clk: rockchip: set the clock ids for RK3228 HDMI
|
%!s(int64=9) %!d(string=hai) anos |
|
Yakir Yang
|
0a9d4ac08e
clk: rockchip: set the clock ids for RK3228 VOP
|
%!s(int64=9) %!d(string=hai) anos |
 Caesar Wang
|
a3cb9aa4ba
clk: rockchip: add the tsadc clocks found on rk3228 SoCs
|
%!s(int64=9) %!d(string=hai) anos |
 Heiko Stuebner
|
36714529f8
clk: rockchip: convert manually created factor clocks to the new type
|
%!s(int64=10) %!d(string=hai) anos |
|
Shawn Lin
|
bb07698fc8
clk: rockchip: fix wrong mmc phase shift for rk3228
|
%!s(int64=9) %!d(string=hai) anos |
|
Heiko Stuebner
|
dfff24bde7
clk: rockchip: only enter pll slow-mode directly before reboots on rk3288
|
%!s(int64=9) %!d(string=hai) anos |
 Jeffy Chen
|
307a2e9ac5
clk: rockchip: add clock controller for rk3228
|
%!s(int64=9) %!d(string=hai) anos |
