Commit History

作者 SHA1 備註 提交日期
  Sergei Shtylyov 0a87bf6cd5 clk: renesas: r8a77980: Add CMT clocks 7 年之前
  Geert Uytterhoeven f3824deb46 clk: renesas: r8a77980: Add RCLK for watchdog timer 7 年之前
  Geert Uytterhoeven 3a251270e6 clk: renesas: r8a77980: Add OSC predivider configuration and clock 7 年之前
  Geert Uytterhoeven 246e232437 clk: renesas: r8a77980: Correct parent clock of PCIEC0 7 年之前
  Sergei Shtylyov ce15783c51 clk: renesas: cpg-mssr: add R8A77980 support 7 年之前