 Rajendra Nayak
|
400d9fda39
clk: qcom: Enable FSM mode for votable alpha PLLs
|
пре 9 година |
 Stephen Boyd
|
ac269395cd
clk: qcom: Convert to clk_hw based provider APIs
|
пре 10 година |
|
Stephen Boyd
|
19aab27308
Merge branch 'clk-determine-rate-struct' into clk-next
|
пре 10 година |
 Boris Brezillon
|
0817b62cc0
clk: change clk_ops' ->determine_rate() prototype
|
пре 10 година |
 Georgi Djakov
|
d4f76de374
clk: qcom: Add support for SR2 PLLs
|
пре 10 година |
 Fengguang Wu
|
d41bd923d3
clk: qcom: fix simple_return.cocci warnings
|
пре 10 година |
 Tomeu Vizoso
|
1c8e600440
clk: Add rate constraints to clocks
|
пре 10 година |
|
Tomeu Vizoso
|
646cafc6aa
clk: Change clk_ops->determine_rate to return a clk_hw as the best parent
|
пре 10 година |
|
Stephen Boyd
|
ae3669ac5c
clk: qcom: Add support for setting rates on PLLs
|
пре 11 година |
|
Stephen Boyd
|
d8c25d3a1a
clk: qcom: pll: Add support for configuring SR PLLs
|
пре 11 година |
|
Stephen Boyd
|
9e2631313c
clk: qcom: Add support for phase locked loops (PLLs)
|
пре 11 година |
