Gabriel Krisman Bertazi
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9c75b18527
drm/i915: reintroduce VLV/CHV PFI programming power domain workaround
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8 年之前 |
Rodrigo Vivi
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d1999e9ef8
drm/i915/cnl: Allow dynamic cdclk changes on CNL
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8 年之前 |
Ville Syrjälä
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d8d4a512a6
drm/i915/cnl: Implement CNL display init/unit sequence
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8 年之前 |
Ville Syrjälä
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ef4f7a689a
drm/i915/cnl: Implement .set_cdclk() for CNL
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8 年之前 |
Ville Syrjälä
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945f2672cc
drm/i915/cnl: Implement .get_display_clock_speed() for CNL
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8 年之前 |
Rodrigo Vivi
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9d81a99713
drm/i915/cnp: Get/set proper Raw clock frequency on CNP.
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8 年之前 |
Ville Syrjälä
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6f38123eca
drm/i915: Fix rawclk readout for g4x
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8 年之前 |
Madhav Chauhan
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97f55ca5b6
drm/i915/glk: limit pixel clock to 99% of cdclk workaround
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8 年之前 |
Pandiyan, Dhinakaran
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8cbeb06dc6
drm/i915: Implement cdclk restrictions based on Azalia BCLK
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8 年之前 |
Pandiyan, Dhinakaran
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78cfa580f8
drm/i915/glk: Apply cdclk workaround for DP audio
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8 年之前 |
Maarten Lankhorst
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e6963ccf5b
drm/i915: Use new atomic iterator macros in cdclk
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8 年之前 |
Paulo Zanoni
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6b9e441df4
drm/i915: remove potentially confusing IS_G4X checks
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8 年之前 |
Ville Syrjälä
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b0587e4d20
drm/i915: Replace the .modeset_commit_cdclk() hook with a more direct .set_cdclk() hook
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8 年之前 |
Ville Syrjälä
|
63ff304425
drm/i915: Nuke the VLV/CHV PFI programming power domain workaround
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8 年之前 |
Ville Syrjälä
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1a5301a58e
drm/i915: Move PFI credit reprogramming into vlv/chv_set_cdclk()
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8 年之前 |
Ville Syrjälä
|
83c5fda74f
drm/i915: Pass the cdclk state to the set_cdclk() functions
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8 年之前 |
Ville Syrjälä
|
3d5dbb10f3
drm/i915: Pass dev_priv to remainder of the cdclk functions
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8 年之前 |
Ville Syrjälä
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bb0f4aab0e
drm/i915: Track full cdclk state for the logical and actual cdclk frequencies
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8 年之前 |
Ville Syrjälä
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49cd97a35d
drm/i915: Start moving the cdclk stuff into a distinct state structure
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8 年之前 |
Ville Syrjälä
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8f0cfa4d2a
drm/i915: Pass computed vco to bxt_set_cdclk()
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8 年之前 |
Ville Syrjälä
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7ff89ca213
drm/i915: Move most cdclk/rawclk related code to intel_cdclk.c
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8 年之前 |