Commit történet

Szerző SHA1 Üzenet Dátum
  Alex Frid 2f924ac33f clk: tegra: Fix T210 PLLRE registration 8 éve
  Alex Frid f7bdb8b78a clk: tegra: Update T210 PLLSS (D2/DP) registration 8 éve
  Alex Frid ac99afe55a clk: tegra: Re-factor T210 PLLX registration 8 éve
  Peter De Schrijver 3dd065e70e clk: tegra: change post IDDQ release delay to 5us 8 éve
  Peter De Schrijver bc7b34a2fb clk: tegra: Init cfg structure in _get_pll_mnp 8 éve
  Peter De Schrijver 04434cfa2b clk: tegra: Enable PLL_SS for Tegra210 8 éve
  Peter De Schrijver 1a7da87727 clk: tegra: fix SS control on PLL enable/disable 8 éve
  Peter De Schrijver e745f992cf clk: tegra: Rework pll_u 8 éve
  Andrew Bresticker 15d68e8c2e clk: tegra: Initialize UTMI PLL when enabling PLLU 9 éve
  Rhyland Klein 926655f929 clk: tegra: Fix pllre Tegra210 and add pll_re_out1 9 éve
  Mark Kuo 442f53fb1b clk: tegra: Fix PLLE SS coefficients 9 éve
  Rhyland Klein fd2963b071 clk: tegra: Fix typos around clearing PLLE bits during enable 9 éve
  Mark Kuo f59b0168d3 clk: tegra: Do not disable PLLE when under hardware control 9 éve
  Andrew Bresticker 3eb61566a6 clk: tegra: pll: Fix potential sleeping-while-atomic 9 éve
  Bill Huang 2d7f61f377 clk: tegra: Read correct IDDQ register in PLL_SS registration 10 éve
  Bill Huang a4ca2b2fe7 clk: tegra: Fix WARN_ON in PLL_RE registration 10 éve
  Andrew Bresticker afff455cf4 clk: tegra: pll: Fix issues with rates for VCO PLLs 10 éve
  Rhyland Klein 6b301a059e clk: tegra: Add support for Tegra210 clocks 10 éve
  Bill Huang 0ef9db6cf2 clk: tegra: pll: Add logic for SS 10 éve
  Rhyland Klein 17e9273a9e clk: tegra: pll: Add dyn_ramp callback 10 éve
  Bill Huang b985114e2f clk: tegra: pll: Add Set_default logic 10 éve
  Bill Huang b5512b45d5 clk: tegra: pll: Adjust vco_min if SDM present 10 éve
  Rhyland Klein 6929715cf6 clk: tegra: pll: Add support for PLLMB for Tegra210 10 éve
  Rhyland Klein dd322f047d clk: tegra: pll: Add specialized logic for Tegra210 10 éve
  Danny Huang 267b62a969 clk: tegra: pll: Update PLLM handling 10 éve
  Rhyland Klein 86c679a522 clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate 10 éve
  Bill Huang fde207eb15 clk: tegra: pll: Add code to handle if resets are supported by PLL 10 éve
  Rhyland Klein 407254da29 clk: tegra: pll: Add logic for out-of-table rates for T210 10 éve
  Rhyland Klein d907f4b4a1 clk: tegra: pll: Add logic for handling SDM data 10 éve
  Rhyland Klein 3706b43629 clk: tegra: pll: Don't unconditionally set LOCK flags 10 éve