 Imre Deak
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f24eeb1912
drm/i915: vlv: sanitize RPS interrupt mask during GPU idling
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%!s(int64=10) %!d(string=hai) anos |
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Imre Deak
|
59d02a1f45
drm/i915: fix HW lockup due to missing RPS IRQ workaround on GEN6
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%!s(int64=10) %!d(string=hai) anos |
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Imre Deak
|
63a3451641
drm/i915: gen9: fix RPS interrupt routing to CPU vs. GT
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%!s(int64=10) %!d(string=hai) anos |
|
Imre Deak
|
dbea3cea69
drm/i915: sanitize RPS resetting during GPU reset
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%!s(int64=10) %!d(string=hai) anos |
 Damien Lespiau
|
98533251b0
drm/i915/bdw: Fix the write setting up the WIZ hashing mode
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%!s(int64=10) %!d(string=hai) anos |
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Imre Deak
|
99990f1b0b
drm/i915: remove the IRQs enabled WARN from intel_disable_gt_powersave
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%!s(int64=10) %!d(string=hai) anos |
|
Imre Deak
|
2837ac4069
drm/i915: vlv: increase timeout when setting idle GPU freq
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%!s(int64=10) %!d(string=hai) anos |
 Tom O'Rourke
|
6985b35218
drm/i915: Update ring freq for full gpu freq range
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%!s(int64=10) %!d(string=hai) anos |
|
Tom O'Rourke
|
c7f3153a61
drm/i915: change initial rps frequency for gen8
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%!s(int64=10) %!d(string=hai) anos |
|
Tom O'Rourke
|
f4ab408c4b
drm/i915: Keep min freq above floor on HSW/BDW
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%!s(int64=10) %!d(string=hai) anos |
|
Tom O'Rourke
|
93ee29203f
drm/i915: Use efficient frequency for HSW/BDW
|
%!s(int64=10) %!d(string=hai) anos |
 Daniel Vetter
|
54499b2a92
Merge tag 'drm-intel-fixes-2014-11-19' into drm-intel-next-queued
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%!s(int64=10) %!d(string=hai) anos |
|
Imre Deak
|
2eb5252e2f
drm/i915: disable rps irqs earlier during suspend/unload
|
%!s(int64=10) %!d(string=hai) anos |
|
Imre Deak
|
d4d70aa596
drm/i915: sanitize rps irq disabling
|
%!s(int64=10) %!d(string=hai) anos |
|
Imre Deak
|
3cc134e3ee
drm/i915: sanitize rps irq enabling
|
%!s(int64=10) %!d(string=hai) anos |
|
Imre Deak
|
e534770add
drm/i915: move rps irq disable one level up
|
%!s(int64=10) %!d(string=hai) anos |
|
Tom O'Rourke
|
151a49d079
drm/i915: Extend pcode mailbox interface
|
%!s(int64=10) %!d(string=hai) anos |
 Ville Syrjälä
|
ab3fb15730
drm/i915: Change CHV SKU400 GPU freq divider to 10
|
%!s(int64=10) %!d(string=hai) anos |
|
Ville Syrjälä
|
80b83b6217
drm/i915: Add missing newline to 'DDR speed' debug messages
|
%!s(int64=10) %!d(string=hai) anos |
|
Ville Syrjälä
|
dd06f88cd0
drm/i915: Refactor vlv/chv GPU frequency divider setup
|
%!s(int64=10) %!d(string=hai) anos |
|
Ville Syrjälä
|
ce611ef81f
drm/i915: Improve PCBR debug information
|
%!s(int64=10) %!d(string=hai) anos |
|
Ville Syrjälä
|
8d40c3ae51
drm/i915: Warn if GPLL isn't used on vlv/chv
|
%!s(int64=10) %!d(string=hai) anos |
|
Ville Syrjälä
|
c8e9627d2a
drm/i915: Add a name for the Punit GPLLENABLE bit
|
%!s(int64=10) %!d(string=hai) anos |
|
Ville Syrjälä
|
9a3b9c7a64
drm/i915: Silence valleyview_set_rps()
|
%!s(int64=10) %!d(string=hai) anos |
|
Daniel Vetter
|
2208d655a9
drm/i915: drop WaSetupGtModeTdRowDispatch:snb
|
%!s(int64=10) %!d(string=hai) anos |
|
Damien Lespiau
|
f5ed50cbff
drm/i915: Let's hope future platforms will use the same WM code as SKL
|
%!s(int64=10) %!d(string=hai) anos |
|
Damien Lespiau
|
dddab346d8
drm/i915: Clear PCODE_DATA1 on SNB+
|
%!s(int64=10) %!d(string=hai) anos |
|
Ville Syrjälä
|
c6e8f39db9
drm/i915: Read the CCK fuse register from CCK
|
%!s(int64=10) %!d(string=hai) anos |
|
Imre Deak
|
b900b94967
drm/i915: move rps irq enable/disable to i915_irq.c
|
%!s(int64=10) %!d(string=hai) anos |
|
Imre Deak
|
20415c5d4e
drm/i915: unify gen6/gen8 rps irq enable/disable
|
%!s(int64=10) %!d(string=hai) anos |
