 Alan Tull
|
7085e2a94f
fpga: manager: change api, don't use drvdata
|
%!s(int64=7) %!d(string=hai) anos |
 Moritz Fischer
|
7f33bbca14
fpga: zynq: Add support for encrypted bitstreams
|
%!s(int64=8) %!d(string=hai) anos |
 Jason Gunthorpe
|
425902f5c8
fpga zynq: Use the scatterlist interface
|
%!s(int64=8) %!d(string=hai) anos |
|
Jason Gunthorpe
|
b496df86ac
fpga zynq: Check the bitstream for validity
|
%!s(int64=8) %!d(string=hai) anos |
|
Jason Gunthorpe
|
6b45e0f24c
fpga zynq: Check for errors after completing DMA
|
%!s(int64=8) %!d(string=hai) anos |
|
Jason Gunthorpe
|
340c0c53ea
fpga zynq: Fix incorrect ISR state on bootup
|
%!s(int64=8) %!d(string=hai) anos |
|
Jason Gunthorpe
|
80baf649c2
fpga zynq: Remove priv->dev
|
%!s(int64=8) %!d(string=hai) anos |
|
Jason Gunthorpe
|
1930c28651
fpga zynq: Add missing \n to messages
|
%!s(int64=8) %!d(string=hai) anos |
 Alan Tull
|
1df2865f8d
fpga-mgr: add fpga image information struct
|
%!s(int64=8) %!d(string=hai) anos |
 Moritz Fischer
|
28f98a12f7
fpga: zynq-fpga: Fix issue with drvdata being overwritten.
|
%!s(int64=9) %!d(string=hai) anos |
|
Moritz Fischer
|
4d10eaff5b
fpga: zynq-fpga: Change fw format to handle bin instead of bit.
|
%!s(int64=9) %!d(string=hai) anos |
|
Moritz Fischer
|
6376931bab
fpga: zynq-fpga: Fix unbalanced clock handling
|
%!s(int64=9) %!d(string=hai) anos |
|
Moritz Fischer
|
37784706bf
fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000
|
%!s(int64=9) %!d(string=hai) anos |
