 Uwe Kleine-König
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692d8328e8
clk: don't use __initconst for non-const arrays
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10 years ago |
 Linus Torvalds
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18a8d49973
Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux
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10 years ago |
 David S. Miller
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95f873f2ff
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
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10 years ago |
 Michael Turquette
|
b80418f3c0
Merge tag 'v3.20-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
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10 years ago |
 Heiko Stuebner
|
e142a4e914
clk: rockchip: add a dummy clock for the watchdog pclk on rk3288
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10 years ago |
 huang lin
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cc6430689e
clk: rockchip: add PVTM clocks on rk3288
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10 years ago |
 Kever Yang
|
f5c3018dd0
clk: rockchip: use the clock ID for usbphy480m_src
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11 years ago |
 Roger Chen
|
7f186025c7
GMAC: modify CRU config for Rockchip RK3288 SoCs integrated GMAC
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10 years ago |
 Doug Anderson
|
a7d9500044
clk: rockchip: rk3288: Make s2r reliable by switching PLLs to slow mode
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10 years ago |
|
Heiko Stuebner
|
9880d4277f
clk: rockchip: fix rk3288 cpuclk core dividers
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10 years ago |
|
Doug Anderson
|
221dfbae2b
clk: rockchip: Add CLK_SET_RATE_PARENT to sclk_uart clocks
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10 years ago |
 Alexandru M Stan
|
89bf26cbc1
clk: rockchip: Add support for the mmc clock phases using the framework
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10 years ago |
 Sonny Rao
|
6d288b169b
clk: rockchip: rk3288 export i2s0_clkout for use in DT
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10 years ago |
 Jeff Chen
|
a72da7c166
clk: rockchip: use clock ID for DMC (memory controller) on rk3288
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10 years ago |
|
Heiko Stuebner
|
dd79c0bea7
clk: rockchip: add ROCKCHIP_PLL_SYNC_RATE flag to some plls
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10 years ago |
|
Heiko Stuebner
|
4f8a7c549f
clk: rockchip: add ability to specify pll-specific flags
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10 years ago |
|
Kever Yang
|
29e9446851
clk: rockchip: fix clock select order for rk3288 usbphy480m_src
|
11 years ago |
|
Kever Yang
|
0132234160
clk: rockchip: fix rk3288 clk_usbphy480m_gate bit location in register
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11 years ago |
 Dmitry Torokhov
|
9aa75e6e09
clk: rockchip: ensure HCLK_VIO2_H2P and PCLK_VIO2_H2P stay enabled
|
11 years ago |
 Chris Zhong
|
33aa59c232
clk: rockchip: rk3288: add suspend and resume
|
11 years ago |
|
Kever Yang
|
78eaf6095c
clk: rockchip: disable unused clocks
|
11 years ago |
|
Kever Yang
|
49ed9ee442
clk: rockchip: change PLL setting for better clock jitter
|
11 years ago |
|
Kever Yang
|
89c107a88d
clk: rockchip: add npll to source of sclk_gpu
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11 years ago |
 Jianqun
|
8f06f5d392
clk: rockchip: rk3288: removing the CLK_SET_RATE_PARENT from i2s_clkout
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11 years ago |
|
Kever Yang
|
cd9b4609a5
clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate
|
11 years ago |
|
Doug Anderson
|
61e309f322
clk: rockchip: Add CLK_SET_RATE_PARENT to aclk_cpu_pre
|
11 years ago |
|
Sonny Rao
|
de7d6c3eeb
clk: rockchip: fix parent for spdif_8ch_frac on rk3288
|
11 years ago |
|
Heiko Stübner
|
6f1294b5a8
clk: rockchip: add restart handler
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11 years ago |
|
Jianqun
|
fc69ed70c1
clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate
|
11 years ago |
|
Heiko Stuebner
|
0e5bdb3f9f
clk: rockchip: switch to using the new cpuclk type for armclk
|
11 years ago |
