 Peter Zijlstra
|
cc1790cf54
perf/x86: Improve HT workaround GP counter constraint
|
10 years ago |
|
Peter Zijlstra
|
b371b59431
perf/x86: Fix event/group validation
|
10 years ago |
|
Peter Zijlstra
|
c857eb56e6
perf/x86: Fix hw_perf_event::flags collision
|
10 years ago |
 Andi Kleen
|
1a78d93750
perf/x86/intel: Streamline LBR MSR handling in PMI
|
10 years ago |
 Stephane Eranian
|
b37609c30e
perf/x86/intel: Make the HT bug workaround conditional on HT enabled
|
10 years ago |
|
Stephane Eranian
|
c02cdbf60b
perf/x86/intel: Limit to half counters when the HT workaround is enabled, to avoid exclusive mode starvation
|
10 years ago |
 Maria Dimakopoulou
|
b63b4b459a
perf/x86/intel: Enforce HT bug workaround with PEBS for SNB/IVB/HSW
|
10 years ago |
|
Maria Dimakopoulou
|
e979121b1b
perf/x86/intel: Implement cross-HT corruption bug workaround
|
10 years ago |
|
Maria Dimakopoulou
|
6f6539cad9
perf/x86/intel: Add cross-HT counter exclusion infrastructure
|
10 years ago |
|
Stephane Eranian
|
79cba82244
perf/x86: Add 'index' param to get_event_constraint() callback
|
10 years ago |
|
Maria Dimakopoulou
|
c5362c0c37
perf/x86: Add 3 new scheduling callbacks
|
10 years ago |
|
Stephane Eranian
|
9041346431
perf/x86: Vectorize cpuc->kfree_on_online
|
10 years ago |
|
Stephane Eranian
|
9a5e3fb52a
perf/x86: Rename x86_pmu::er_flags to 'flags'
|
10 years ago |
 Alexander Shishkin
|
8062382c8d
perf/x86/intel/bts: Add BTS PMU driver
|
10 years ago |
|
Alexander Shishkin
|
52ca9ced3f
perf/x86/intel/pt: Add Intel PT PMU driver
|
10 years ago |
|
Alexander Shishkin
|
4807034248
perf/x86: Mark Intel PT and LBR/BTS as mutually exclusive
|
10 years ago |
|
Andi Kleen
|
294fe0f52a
perf/x86/intel: Add INST_RETIRED.ALL workarounds
|
10 years ago |
|
Peter Zijlstra
|
2c44b1936b
perf/x86/intel: Expose LBR callstack to user space tooling
|
10 years ago |
 Yan, Zheng
|
e18bf52642
perf/x86/intel: Allocate space for storing LBR stack
|
10 years ago |
|
Yan, Zheng
|
e9d7f7cd97
perf/x86/intel: Add basic Haswell LBR call stack support
|
10 years ago |
|
Yan, Zheng
|
2a0ad3b326
perf/x86/intel: Use context switch callback to flush LBR stack
|
10 years ago |
|
Yan, Zheng
|
ba532500c5
perf: Introduce pmu context switch callback
|
10 years ago |
|
Yan, Zheng
|
27ac905b8f
perf/x86/intel: Reduce lbr_sel_map[] size
|
10 years ago |
 Andy Lutomirski
|
7911d3f7af
perf/x86: Only allow rdpmc if a perf_event is mapped
|
10 years ago |
|
Andi Kleen
|
7550ddffe4
perf/x86: Add INTEL_FLAGS_UEVENT_CONSTRAINT
|
11 years ago |
 Ingo Molnar
|
1776b10627
perf/x86/intel: Revert incomplete and undocumented Broadwell client support
|
10 years ago |
|
Andi Kleen
|
c46e665f03
perf/x86: Add INST_RETIRED.ALL workarounds
|
11 years ago |
|
Andi Kleen
|
86a04461a9
perf/x86: Revamp PEBS event selection
|
11 years ago |
 Kan Liang
|
338b522ca4
perf/x86/intel: Protect LBR and extra_regs against KVM lying
|
11 years ago |
|
Peter Zijlstra
|
c347a2f179
perf/x86: Add a few more comments
|
11 years ago |
