 Andrew Bresticker
|
15d68e8c2e
clk: tegra: Initialize UTMI PLL when enabling PLLU
|
9 lat temu |
 Lucas Stach
|
7970973018
clk: tegra: Fix PLL_U post divider and initial rate on Tegra30
|
9 lat temu |
|
Lucas Stach
|
a02cc84a31
clk: tegra: Initialize PLL_C to sane rate on Tegra30
|
9 lat temu |
 Danny Huang
|
267b62a969
clk: tegra: pll: Update PLLM handling
|
10 lat temu |
 Rhyland Klein
|
86c679a522
clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate
|
10 lat temu |
|
Rhyland Klein
|
3706b43629
clk: tegra: pll: Don't unconditionally set LOCK flags
|
10 lat temu |
 Thierry Reding
|
385f9adf62
clk: tegra: Constify pdiv-to-hw mappings
|
9 lat temu |
|
Thierry Reding
|
8d99704fde
clk: tegra: Format tables consistently
|
9 lat temu |
|
Thierry Reding
|
e52d7c04bb
clk: tegra: Miscellaneous coding style cleanups
|
9 lat temu |
|
Thierry Reding
|
c4947e364b
clk: tegra: Fix 26 MHz oscillator frequency
|
9 lat temu |
|
Rhyland Klein
|
88d909bedf
clk: tegra: Modify tegra_audio_clk_init to accept more plls
|
10 lat temu |
 Stephen Boyd
|
584ac4e935
clk: tegra: Properly include clk.h
|
10 lat temu |
 Marcel Ziswiler
|
36b7be6d3e
clk: tegra: Fix hda2codec_2x clock name for Tegra30
|
10 lat temu |
|
Thierry Reding
|
63cc5a4da1
clk: tegra: Model oscillator as clock
|
10 lat temu |
|
Thierry Reding
|
12cf33c0eb
clk: tegra: Use consistent indentation
|
10 lat temu |
|
Thierry Reding
|
4f4f85fa0b
clk: tegra: Implement memory-controller clock
|
11 lat temu |
|
Thierry Reding
|
7232398abc
ARM: tegra: Convert PMC to a driver
|
11 lat temu |
|
Thierry Reding
|
306a7f9139
ARM: tegra: Move includes to include/soc/tegra
|
11 lat temu |
 Stephen Warren
|
a85f06badc
clk: tegra: remove bogus PCIE_XCLK
|
11 lat temu |
|
Stephen Warren
|
6d5b988e7d
clk: tegra: implement a reset driver
|
11 lat temu |
 Alexandre Courbot
|
5ab5d4048e
clk: tegra: add FUSE clock device
|
11 lat temu |
 Thierry Reding
|
c04bf55926
clk: tegra: Properly setup PWM clock on Tegra30
|
12 lat temu |
|
Thierry Reding
|
43e36a9646
clk: tegra: Initialize secondary gr3d clock on Tegra30
|
12 lat temu |
 Peter De Schrijver
|
1bf409159b
clk: tegra: move tegra30 to common infra
|
12 lat temu |
|
Peter De Schrijver
|
76ebc134d4
clk: tegra: move periph clocks to common file
|
12 lat temu |
|
Peter De Schrijver
|
ebe142b2ad
clk: tegra: move fields to tegra_clk_pll_params
|
12 lat temu |
|
Peter De Schrijver
|
343a607cb7
clk: tegra: common periph_clk_enb_refcnt and clks
|
12 lat temu |
|
Peter De Schrijver
|
d5ff89a82a
clk: tegra: simplify periph clock data
|
12 lat temu |
|
Peter De Schrijver
|
252d0d2bb0
clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clks
|
11 lat temu |
 Tuomas Tynkkynen
|
89ac8567b9
clk: tegra30: Don't wait for PLL_U lock bit
|
12 lat temu |
