 Dan Carpenter
|
5c38181ce9
perf/x86/intel: Remove an inconsistent NULL check
|
8 years ago |
 Peter Zijlstra
|
3e2c1a67d6
perf/x86/intel: Clean up LBR state tracking
|
9 years ago |
|
Peter Zijlstra
|
a5dcff628a
perf/x86/intel: Remove redundant test from intel_pmu_lbr_add()
|
9 years ago |
|
Peter Zijlstra
|
c3a61a2c5c
perf/x86/intel: Eliminate dead code in intel_pmu_lbr_del()
|
9 years ago |
|
Peter Zijlstra
|
68f7082ffb
perf/x86: Ensure perf_sched_cb_{inc,dec}() is only called from pmu::{add,del}()
|
9 years ago |
|
Peter Zijlstra
|
aefbc4d04c
perf/x86/intel: Fix rdlbr_to() MSR reading typo
|
9 years ago |
|
Peter Zijlstra
|
d4cf1949f9
perf/x86/intel: Add {rd,wr}lbr_{to,from} wrappers
|
9 years ago |
 David Carrillo-Cisneros
|
71adae99ed
perf/x86/intel: Add MSR_LAST_BRANCH_FROM_x quirk for ctx switch
|
9 years ago |
|
David Carrillo-Cisneros
|
3812bba84f
perf/x86/intel: Fix trivial formatting and style bug
|
9 years ago |
|
David Carrillo-Cisneros
|
19fc9ddd61
perf/x86/intel: Fix MSR_LAST_BRANCH_FROM_x bug when no TSX
|
9 years ago |
|
David Carrillo-Cisneros
|
f09509b939
perf/x86/intel: Print LBR support statement after validation
|
9 years ago |
 Ingo Molnar
|
0b20e59cef
Merge branch 'perf/urgent' into perf/core, to resolve conflict
|
9 years ago |
 Kan Liang
|
cf3beb7c90
perf/x86/intel: Fix incorrect lbr_sel_mask value
|
9 years ago |
|
Kan Liang
|
f21d5adceb
perf/x86/intel: Add LBR filter support for Silvermont and Airmont CPUs
|
9 years ago |
|
Kan Liang
|
8b92c3a78d
perf/x86/intel: Add Goldmont CPU support
|
9 years ago |
|
Ingo Molnar
|
00f5268501
Merge branch 'x86/cleanups' into x86/urgent
|
9 years ago |
 Borislav Petkov
|
27f6d22b03
perf/x86: Move perf_event.h to its new home
|
9 years ago |
|
Borislav Petkov
|
c85cc4497f
perf/x86: Move perf_event_intel_lbr.c ........ => x86/events/intel/lbr.c
|
9 years ago |
