 James Hogan
|
01882b4d5e
MIPS: c-r4k: Split user/kernel flush_icache_range()
|
%!s(int64=9) %!d(string=hai) anos |
 Maciej W. Rozycki
|
3bcb03f3a7
MIPS: tlb-r3k: Move CP0.Wired register initialisation to `tlb_init'
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%!s(int64=10) %!d(string=hai) anos |
 Paul Gortmaker
|
078a55fc82
MIPS: Delete __cpuinit/__CPUINIT usage from MIPS code
|
%!s(int64=12) %!d(string=hai) anos |
 Ralf Baechle
|
7034228792
MIPS: Whitespace cleanup.
|
%!s(int64=12) %!d(string=hai) anos |
 David Howells
|
b81947c646
Disintegrate asm/system.h for MIPS
|
%!s(int64=13) %!d(string=hai) anos |
|
Ralf Baechle
|
d9cdc901af
MIPS: cache: Provide cache flush operations for XFS
|
%!s(int64=14) %!d(string=hai) anos |
 Justin P. Mattock
|
79add62773
update David Miller's old email address
|
%!s(int64=14) %!d(string=hai) anos |
|
Ralf Baechle
|
631330f584
MIPS: Build fix - include <linux/smp.h> into all smp_processor_id() users.
|
%!s(int64=16) %!d(string=hai) anos |
 Atsushi Nemoto
|
3885ec8ca2
[MIPS] TX39xx: Add missing local_flush_icache_range initialization
|
%!s(int64=17) %!d(string=hai) anos |
 Thomas Bogendoerfer
|
e0cee3eea7
[MIPS] Fix WARNING: at kernel/smp.c:290
|
%!s(int64=17) %!d(string=hai) anos |
|
Ralf Baechle
|
9c5a3d729c
[MIPS] Handle aliases in vmalloc correctly.
|
%!s(int64=17) %!d(string=hai) anos |
|
Ralf Baechle
|
234fcd1484
[MIPS] Fix loads of section missmatches
|
%!s(int64=17) %!d(string=hai) anos |
|
Ralf Baechle
|
10cc352907
[MIPS] Allow hardwiring of the CPU type to a single type for optimization.
|
%!s(int64=18) %!d(string=hai) anos |
|
Atsushi Nemoto
|
a5664c4075
[MIPS] TX39: Remove redundant tx39_blast_icache() calls
|
%!s(int64=18) %!d(string=hai) anos |
|
Atsushi Nemoto
|
c59a0f15be
[MIPS] Remove __flush_icache_page
|
%!s(int64=19) %!d(string=hai) anos |
|
Ralf Baechle
|
585fa72493
[MIPS] Retire flush_icache_page from mm use.
|
%!s(int64=19) %!d(string=hai) anos |
|
Ralf Baechle
|
7e3bfc7cfc
[MIPS] Handle IDE PIO cache aliases on SMP.
|
%!s(int64=19) %!d(string=hai) anos |
|
Atsushi Nemoto
|
de62893bc0
[MIPS] local_r4k_flush_cache_page fix
|
%!s(int64=19) %!d(string=hai) anos |
|
Atsushi Nemoto
|
41700e7399
[MIPS] Add protected_blast_icache_range, blast_icache_range, etc.
|
%!s(int64=19) %!d(string=hai) anos |
|
Ralf Baechle
|
02cf211968
Cleanup the mess in cpu_cache_init.
|
%!s(int64=20) %!d(string=hai) anos |
|
Atsushi Nemoto
|
9043f7e95d
Sync c-tx39.c with c-r4k.c.
|
%!s(int64=20) %!d(string=hai) anos |
|
Ralf Baechle
|
1d40cfcd34
Avoid SMP cacheflushes. This is a minor optimization of startup but
|
%!s(int64=20) %!d(string=hai) anos |
|
Ralf Baechle
|
c6e8b58771
Update MIPS to use the 4-level pagetable code thereby getting rid of
|
%!s(int64=20) %!d(string=hai) anos |
 Linus Torvalds
|
1da177e4c3
Linux-2.6.12-rc2
|
%!s(int64=20) %!d(string=hai) anos |
