 Paul Burton
|
1b49260006
MIPS: inst.h: Rename cbcond{0,1}_op to pop{1,3}0_op
|
9 years ago |
|
Paul Burton
|
1c66b79bb3
MIPS: inst.h: Rename b{eq,ne}zcji[al]c_op to pop{6,7}6_op
|
9 years ago |
 James Hogan
|
6f63405cb6
MIPS: uasm: Add r6 MUL encoding
|
9 years ago |
|
James Hogan
|
9f730a60e5
MIPS: uasm: Add MTHI/MTLO instructions
|
9 years ago |
|
James Hogan
|
61c64cf99a
MIPS: uasm: Add DI instruction
|
9 years ago |
|
James Hogan
|
59e3559f48
MIPS: uasm: Add CFCMSA/CTCMSA instructions
|
9 years ago |
|
James Hogan
|
258f3a2ea9
MIPS: KVM: Convert emulation to use asm/inst.h
|
9 years ago |
|
Paul Burton
|
b6d5c4eda7
MIPS: inst: Declare fsel_op for sel.fmt instruction
|
9 years ago |
 Huacai Chen
|
380cd582c0
MIPS: Loongson-3: Fast TLB refill handler
|
9 years ago |
|
James Hogan
|
b2c5963577
MIPS: Move KVM specific opcodes into asm/inst.h
|
9 years ago |
 Maciej W. Rozycki
|
29e2800348
MIPS: inst.h: Fix some instruction descriptions
|
9 years ago |
|
Maciej W. Rozycki
|
69a1e6cbdf
MIPS: math-emu: Correct the emulation of microMIPS ADDIUPC instruction
|
9 years ago |
 Markos Chandras
|
107d34009e
MIPS: inst.h: Add new MIPS R6 FPU opcodes
|
10 years ago |
 Leonid Yegoshin
|
6701ca2df4
MIPS: Declare MSA MI10 instruction formats
|
10 years ago |
|
Markos Chandras
|
28d6f93d20
MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructions
|
10 years ago |
|
Markos Chandras
|
69b9a2fd05
MIPS: Emulate the new MIPS R6 BEQZC and JIC instructions
|
10 years ago |
|
Markos Chandras
|
84fef63012
MIPS: Emulate the new MIPS R6 BALC instruction
|
10 years ago |
|
Markos Chandras
|
10d962d534
MIPS: Emulate the new MIPS R6 BNVC, BNEC and BNEZLAC instructions
|
10 years ago |
|
Markos Chandras
|
c893ce38b2
MIPS: Emulate the new MIPS R6 BOVC, BEQC and BEQZALC instructions
|
10 years ago |
|
Markos Chandras
|
8467ca0122
MIPS: Emulate the new MIPS R6 branch compact (BC) instruction
|
10 years ago |
|
Markos Chandras
|
c8a34581ec
MIPS: Emulate the BC1{EQ,NE}Z FPU instructions
|
10 years ago |
|
Leonid Yegoshin
|
a168b8f1cd
MIPS: mm: Add MIPS R6 instruction encodings
|
10 years ago |
 Steven J. Hill
|
e2965cd000
MIPS: Add MFHC0 and MTHC0 instructions to uasm.
|
10 years ago |
|
Markos Chandras
|
7682f9e818
MIPS: uasm: Add SLT uasm instruction
|
11 years ago |
|
Markos Chandras
|
16d21a812f
MIPS: uasm: Add mflo uasm instruction
|
11 years ago |
|
Markos Chandras
|
a8e897ad00
MIPS: uasm: Add mul uasm instruction
|
11 years ago |
|
Markos Chandras
|
ab9e4fa092
MIPS: uasm: Add wsbh uasm instruction
|
11 years ago |
|
Markos Chandras
|
e8ef868b47
MIPS: uasm: Add sltu uasm instruction
|
11 years ago |
|
Markos Chandras
|
f3ec7a23b6
MIPS: uasm: Add mfhi uasm instruction
|
11 years ago |
|
Markos Chandras
|
4c12a854d8
MIPS: uasm: Add divu uasm instruction
|
11 years ago |
