 Russell King
|
b2c3e38a54
ARM: redo TTBR setup code for LPAE
|
10 years ago |
 Will Deacon
|
2c553ac19e
ARM: 8164/1: mm: clear SCTLR.HA instead of setting it for LPAE
|
11 years ago |
 Konstantin Khlebnikov
|
7e66cbc93f
ARM: 8132/1: LPAE: drop wrong carry flag correction after adding TTBR1_OFFSET
|
11 years ago |
|
Konstantin Khlebnikov
|
7fb00c2fca
ARM: 8114/1: LPAE: load upper bits of early TTBR0/TTBR1
|
11 years ago |
 Steven Capper
|
ded9477984
ARM: 8109/1: mm: Modify pte_write and pmd_write logic for LPAE
|
11 years ago |
|
Russell King
|
6ebbf2ce43
ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+
|
11 years ago |
 Jianguo Wu
|
86f40622af
ARM: 8037/1: mm: support big-endian page tables
|
11 years ago |
|
Will Deacon
|
bf3f0f332f
ARM: 7784/1: mm: ensure SMP alternates assemble to exactly 4 bytes with Thumb-2
|
12 years ago |
 Paul Gortmaker
|
8bd26e3a7e
arm: delete __cpuinit/__CPUINIT usage from all ARM users
|
12 years ago |
 Cyril Chemparathy
|
4756dcbfd3
ARM: LPAE: accomodate >32-bit addresses for page table base
|
13 years ago |
|
Cyril Chemparathy
|
a7fbc0d62a
ARM: LPAE: factor out T1SZ and TTBR1 computations
|
13 years ago |
|
Cyril Chemparathy
|
13f659b0f3
ARM: LPAE: use phys_addr_t in switch_mm()
|
13 years ago |
|
Will Deacon
|
ae8a8b9553
ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead
|
12 years ago |
 Ben Dooks
|
78305c8630
ARM: 7652/1: mm: fix missing use of 'asid' to get asid value from mm->context.id
|
12 years ago |
|
Ben Dooks
|
251019fb97
ARM: 7650/1: mm: replace direct access to mm->context.id with new macro
|
12 years ago |
|
Will Deacon
|
26ffd0d43b
ARM: mm: introduce present, faulting entries for PAGE_NONE
|
13 years ago |
|
Will Deacon
|
dbf62d5006
ARM: mm: introduce L_PTE_VALID for page table entries
|
13 years ago |
 Catalin Marinas
|
1b6ba46b7e
ARM: LPAE: MMU setup for the 3-level page table format
|
13 years ago |
