Historique des commits

Auteur SHA1 Message Date
  Will Deacon 40ee068ec0 ARM: 8465/1: mm: keep reserved ASIDs in sync with mm after multiple rollovers il y a 9 ans
  Will Deacon 8e64806672 ARM: 8299/1: mm: ensure local active ASID is marked as allocated on rollover il y a 10 ans
  Will Deacon a391263cd8 ARM: 8203/1: mm: try to re-use old ASID assignments following a rollover il y a 10 ans
  Will Deacon 5d49750933 ARM: 7926/1: mm: flesh out and fix the comments in the ASID allocator il y a 11 ans
  Will Deacon a7a0410506 ARM: 7925/1: mm: keep track of last ASID allocation to improve bitmap searching il y a 11 ans
  Will Deacon e1a5848e33 ARM: 7924/1: mm: don't bother with reserved ttbr0 when running with LPAE il y a 11 ans
  Will Deacon f0915781bd ARM: tlb: don't perform inner-shareable invalidation for local TLB ops il y a 12 ans
  Fabio Estevam 1f49856bb0 ARM: 7789/1: Do not run dummy_flush_tlb_a15_erratum() on non-Cortex-A15 il y a 12 ans
  Russell King 3c0c01ab74 Merge branch 'devel-stable' into for-next il y a 12 ans
  Marc Zyngier 0d0752bca1 ARM: 7769/1: Cortex-A15: fix erratum 798181 implementation il y a 12 ans
  Marc Zyngier b8e4a4740f ARM: 7768/1: prevent risks of out-of-bound access in ASID allocator il y a 12 ans
  Marc Zyngier ae120d9edf ARM: 7767/1: let the ASID allocator handle suspended animation il y a 12 ans
  Cyril Chemparathy 1fc84ae84b ARM: LPAE: use 64-bit accessors for TTBR registers il y a 13 ans
  Catalin Marinas 93dc68876b ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB operations) il y a 12 ans
  Will Deacon 89c7e4b8bb ARM: 7661/1: mm: perform explicit branch predictor maintenance when required il y a 12 ans
  Will Deacon 8a4e3a9ead ARM: 7659/1: mm: make mm->context.id an atomic64_t variable il y a 12 ans
  Will Deacon 37f47e3d62 ARM: 7658/1: mm: fix race updating mm->context.id on ASID rollover il y a 12 ans
  Ben Dooks 9520a5bece ARM: 7649/1: mm: mm->context.id fix for big-endian il y a 12 ans
  Nicolas Pitre 3e99675af1 ARM: 7582/2: rename kvm_seq to vmalloc_seq so to avoid confusion with KVM il y a 12 ans
  Will Deacon bf51bb82cc ARM: mm: use bitmap operations when allocating new ASIDs il y a 13 ans
  Will Deacon 4b88316083 ARM: mm: avoid taking ASID spinlock on fastpath il y a 13 ans
  Will Deacon b5466f8728 ARM: mm: remove IPI broadcasting on ASID rollover il y a 13 ans
  Will Deacon ae3790b8a9 ARM: 7502/1: contextidr: avoid using bfi instruction during notifier il y a 13 ans
  Will Deacon 575320d625 ARM: 7445/1: mm: update CONTEXTIDR register to contain PID of current process il y a 13 ans
  Catalin Marinas e323969ccd ARM: Remove current_mm per-cpu variable il y a 13 ans
  Catalin Marinas 7fec1b57b8 ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on ASID-capable CPUs il y a 13 ans
  Will Deacon 3c5f7e7b4a ARM: Use TTBR1 instead of reserved context ID il y a 14 ans
  Catalin Marinas 14d8c9512a ARM: LPAE: Add context switching support il y a 13 ans
  Thomas Gleixner bd31b85960 locking, ARM: Annotate low level hw locks as raw il y a 16 ans
  Russell King a0a54d37b4 Revert "ARM: 6944/1: mm: allow ASID 0 to be allocated to tasks" il y a 14 ans