 Imre Deak
|
a72fbc3a14
drm/i915: unify gen6/gen8 pm irq helpers
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%!s(int64=10) %!d(string=hai) anos |
 Arun Siluvery
|
3e470eaaee
drm/i915/chv: Remove pre-production workarounds
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%!s(int64=10) %!d(string=hai) anos |
 Zhe Wang
|
20e4936693
drm/i915/skl: Enable Gen9 RC6
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%!s(int64=10) %!d(string=hai) anos |
 Damien Lespiau
|
d21b795c41
drm/i915/skl: Log the order in which we flush the pipes in the WM code
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%!s(int64=10) %!d(string=hai) anos |
|
Damien Lespiau
|
0e8fb7ba7c
drm/i915/skl: Flush the WM configuration
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%!s(int64=10) %!d(string=hai) anos |
|
Damien Lespiau
|
34bb56af7f
drm/i915/skl: Stage the pipe DDB allocation
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%!s(int64=10) %!d(string=hai) anos |
|
Damien Lespiau
|
5d374d9638
drm/i915/skl: Reduce the indentation level in skl_write_wm_values()
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%!s(int64=10) %!d(string=hai) anos |
|
Damien Lespiau
|
afb024aa65
drm/i915/skl: Correctly align skl_compute_plane_wm() arguments
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%!s(int64=10) %!d(string=hai) anos |
|
Damien Lespiau
|
9414f563f3
drm/i915/skl: Rework when the transition WMs are computed
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%!s(int64=10) %!d(string=hai) anos |
|
Damien Lespiau
|
407b50f31b
drm/i915/skl: Move all the WM compute functions in one place
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%!s(int64=10) %!d(string=hai) anos |
|
Damien Lespiau
|
e6d6617152
drm/i915/skl: Make res_blocks/lines intermediate values 32 bits
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%!s(int64=10) %!d(string=hai) anos |
|
Damien Lespiau
|
21fca258bc
drm/i915/skl: Use a more descriptive parameter name in skl_compute_plane_wm()
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%!s(int64=10) %!d(string=hai) anos |
|
Damien Lespiau
|
16160e3dd3
drm/i915/skl: Make 'end' of the DDB allocation entry exclusive
|
%!s(int64=10) %!d(string=hai) anos |
|
Damien Lespiau
|
08db665203
drm/i915/skl: Check the DDB state at modeset
|
%!s(int64=10) %!d(string=hai) anos |
|
Damien Lespiau
|
a269c5839b
drm/i915/skl: Read back the DDB allocation hw state
|
%!s(int64=10) %!d(string=hai) anos |
|
Damien Lespiau
|
53b0deb4cb
drm/i915/skl: Store the new WM state at the very end of the update
|
%!s(int64=10) %!d(string=hai) anos |
 Vandana Kannan
|
4f94738674
drm/i915/gen9: Disable WM if corresponding latency is 0
|
%!s(int64=10) %!d(string=hai) anos |
|
Vandana Kannan
|
367294be7c
drm/i915/gen9: Add 2us read latency to WM level
|
%!s(int64=10) %!d(string=hai) anos |
 Pradeep Bhat
|
3078999f2a
drm/i915/skl: Read the pipe WM HW state
|
%!s(int64=10) %!d(string=hai) anos |
|
Damien Lespiau
|
8211bd5bdf
drm/i915/skl: Program the DDB allocation
|
%!s(int64=10) %!d(string=hai) anos |
|
Damien Lespiau
|
b9cec07585
drm/i915/skl: Allocate DDB portions for display planes
|
%!s(int64=10) %!d(string=hai) anos |
|
Pradeep Bhat
|
2d41c0b59a
drm/i915/skl: SKL Watermark Computation
|
%!s(int64=10) %!d(string=hai) anos |
|
Pradeep Bhat
|
2ac96d2a6e
drm/i915/skl: Definition of SKL WM param structs for pipe/plane
|
%!s(int64=10) %!d(string=hai) anos |
|
Pradeep Bhat
|
2af30a5c40
drm/i915/skl: Read the Memory Latency Values for WM computation
|
%!s(int64=10) %!d(string=hai) anos |
 Rodrigo Vivi
|
5e56ba4505
drm/i915/chv: Use 16 and 32 for low and high drain latency precision.
|
%!s(int64=11) %!d(string=hai) anos |
|
Rodrigo Vivi
|
101b376d35
drm/i915/bdw: Remove BDW preproduction W/As until C stepping.
|
%!s(int64=11) %!d(string=hai) anos |
|
Rodrigo Vivi
|
58abf1daae
drm/i915: Do not export RC6p and RC6pp if they don't exist
|
%!s(int64=11) %!d(string=hai) anos |
 Daniel Vetter
|
a8cbd45977
Merge branch 'drm-intel-next-fixes' into drm-intel-next
|
%!s(int64=11) %!d(string=hai) anos |
|
Daniel Vetter
|
2aeb7d3a4d
drm/i915: s/pm._irqs_disabled/pm.irqs_enabled/
|
%!s(int64=11) %!d(string=hai) anos |
|
Daniel Vetter
|
9c065a7d5b
drm/i915: Extract intel_runtime_pm.c
|
%!s(int64=11) %!d(string=hai) anos |
