 Matt Roper
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a6d3460e62
drm/i915/gen9: Drop re-allocation of DDB at atomic commit (v2)
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9 years ago |
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Matt Roper
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98d39494d3
drm/i915/gen9: Compute DDB allocation at atomic check time (v4)
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9 years ago |
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Matt Roper
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279e99d76e
drm/i915: Add distrust_bios_wm flag to dev_priv (v2)
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9 years ago |
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Matt Roper
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c107acfeb0
drm/i915/gen9: Allow skl_allocate_pipe_ddb() to operate on in-flight state (v3)
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9 years ago |
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Matt Roper
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86a2100a8b
drm/i915/gen9: Store plane minimum blocks in CRTC wm state (v2)
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9 years ago |
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Matt Roper
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9c74d82621
drm/i915/gen9: Allow calculation of data rate for in-flight state (v2)
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9 years ago |
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Matt Roper
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a1de91e5f3
drm/i915/gen9: Cache plane data rates in CRTC state
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9 years ago |
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Matt Roper
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e7649b5477
drm/i915: Rename s/skl_compute_pipe_wm/skl_build_pipe_wm/
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9 years ago |
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Matt Roper
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e8f1f02e71
drm/i915: Reorganize WM structs/unions in CRTC state
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9 years ago |
 Tvrtko Ursulin
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7e22dbbbae
drm/i915: Replace "INTEL_INFO->gen == x" checks with IS_GENx
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9 years ago |
 Chris Wilson
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dc97997a21
drm/i915: Use drm_i915_private as the native pointer for intel_uncore.c
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9 years ago |
 Ville Syrjälä
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532f7a7f8d
drm/i915: Calculate IPS linetime watermark based on future cdclk
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9 years ago |
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Chris Wilson
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c033666a94
drm/i915: Store a i915 backpointer from engine, and use it
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9 years ago |
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Tvrtko Ursulin
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91d14251bb
drm/i915: Small display interrupt handlers tidy
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9 years ago |
 Imre Deak
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450174fe9c
drm/i915/chv: Tune L3 SQC credits based on actual latencies
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9 years ago |
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Imre Deak
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36579cb63b
drm/i915: Clean up L3 SQC register field definitions
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9 years ago |
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Imre Deak
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48e5d68d28
drm/i915/bdw: Add missing delay during L3 SQC credit programming
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9 years ago |
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Chris Wilson
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73db04cfa8
drm/i915: Move releasing of the GEM request from free to retire/cancel
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9 years ago |
 Akash Goel
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2030d684f7
drm/i915/bxt: Explicitly clear the Turbo control register
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9 years ago |
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Ville Syrjälä
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297b32ec7e
drm/i915: Ignore GTFIFODBG FIFO free entry fields on CHV
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9 years ago |
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Ville Syrjälä
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766078df43
drm/i915: Move vlv_init_display_clock_gating() to the display power well
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9 years ago |
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Ville Syrjälä
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1204d5baa8
drm/i915: Make sure LP1+ watermarks levels are preserved when going from 1 to 2 pipes
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9 years ago |
 Joonas Lahtinen
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2d1fe07340
drm/i915: Do not use {HAS_*, IS_*, INTEL_INFO}(dev_priv->dev)
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9 years ago |
 Kumar, Mahesh
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a280f7dd9f
drm/i915/skl+: Use plane size for relative data rate calculation
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9 years ago |
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Ville Syrjälä
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5fd9f52384
drm/i915: Set GPU freq to idle_freq initially
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9 years ago |
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Ville Syrjälä
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c30fec656d
drm/i915: Use GPLL ref clock to calculate GPU freqs on VLV/CHV
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9 years ago |
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Joonas Lahtinen
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72e96d6450
drm/i915: Refer to GGTT {,VM} consistently
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9 years ago |
 Dave Gordon
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b4ac5afc6b
drm/i915: replace for_each_engine()
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9 years ago |
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Joonas Lahtinen
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62106b4f6b
drm/i915: Rename dev_priv->gtt to dev_priv->ggtt
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9 years ago |
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Imre Deak
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bb400da998
drm/i915: Move load time init of clock gating hooks earlier
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9 years ago |
