 Martin Blumenstingl
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5b33139b1a
clk: meson: meson8b: fix meson8b_cpu_clk parent clock name
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7 years ago |
|
Martin Blumenstingl
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b251e4c88f
clk: meson: meson8b: fix meson8b_fclk_div3_div clock name
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7 years ago |
 Stephen Boyd
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5d1c04dde0
clk: meson: Drop unused local variable and add static
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7 years ago |
 Jerome Brunet
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5b13ef64ee
clk: meson: clean-up clk81 clocks
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7 years ago |
|
Jerome Brunet
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05f814402d
clk: meson: add fdiv clock gates
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7 years ago |
|
Jerome Brunet
|
513b67ac39
clk: meson: add mpll pre-divider
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7 years ago |
|
Jerome Brunet
|
2eab2d7cab
clk: meson: add fractional part of meson8b fixed_pll
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7 years ago |
|
Jerome Brunet
|
251b6fd38b
clk: meson: rework meson8b cpu clock
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7 years ago |
|
Jerome Brunet
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d610b54f77
clk: meson: split divider and gate part of mpll
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7 years ago |
|
Jerome Brunet
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722825dcd5
clk: meson: migrate plls clocks to clk_regmap
|
7 years ago |
|
Jerome Brunet
|
c763e61ae8
clk: meson: migrate mplls clocks to clk_regmap
|
7 years ago |
|
Jerome Brunet
|
2513a28c10
clk: meson: migrate muxes to clk_regmap
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7 years ago |
|
Jerome Brunet
|
f06ddd2852
clk: meson: migrate dividers to clk_regmap
|
7 years ago |
|
Jerome Brunet
|
7f9768a540
clk: meson: migrate gates to clk_regmap
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7 years ago |
|
Jerome Brunet
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161f6e5baa
clk: meson: add regmap to the clock controllers
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7 years ago |
|
Jerome Brunet
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7b174c5ebe
clk: meson: remove obsolete comments
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7 years ago |
|
Jerome Brunet
|
14bd7b9c8d
clk: meson: only one loop index is necessary in probe
|
7 years ago |
|
Jerome Brunet
|
332b32a232
clk: meson: use devm_of_clk_add_hw_provider
|
7 years ago |
 Yixun Lan
|
27aad90548
clk: meson: make the spinlock naming more specific
|
7 years ago |
 Stephen Boyd
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3477a72b41
Merge tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson into clk-next
|
8 years ago |
|
Martin Blumenstingl
|
189621726b
clk: meson: meson8b: register the built-in reset controller
|
8 years ago |
|
Jerome Brunet
|
de2bc4178b
clk: meson: meson8b: fix protection against undefined clks
|
8 years ago |
|
Jerome Brunet
|
1f737ffa13
clk: meson: mpll: fix mpll0 fractional part ignored
|
8 years ago |
|
Martin Blumenstingl
|
855f06a100
clk: meson: meson8b: add compatibles for Meson8 and Meson8m2
|
8 years ago |
|
Martin Blumenstingl
|
be58e49669
clk: meson: meson8b: mark clk81 as critical
|
8 years ago |
|
Jerome Brunet
|
b778f7451a
clk: meson8b: add the mplls clocks 0, 1 and 2
|
8 years ago |
|
Jerome Brunet
|
e988aae54c
clk: meson8b: put dividers and muxes in tables
|
8 years ago |
|
Jerome Brunet
|
f7e3a82609
clk: meson: add missing const qualifiers on gate arrays
|
8 years ago |
|
Jerome Brunet
|
340a84ce1e
clk: meson8b: fix clk81 register address
|
8 years ago |
 Arnd Bergmann
|
0d5aa65e32
clk: meson: fix CLKID_GCLK_VENCI_INT typo
|
9 years ago |
