 Ville Syrjälä
|
5a8fbb7d19
drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enable
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10 years ago |
|
Ville Syrjälä
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770effb19f
drm/i915: Add locking around chv_phy_control_init()
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10 years ago |
 Damien Lespiau
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dcddab3aa0
drm/i915: Extract a intel_power_well_disable() function
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10 years ago |
|
Damien Lespiau
|
e8ca932056
drm/i915: Extract a intel_power_well_enable() function
|
10 years ago |
|
Ville Syrjälä
|
2be7d540fd
drm/i915: Refactor VLV display power well init/deinit
|
10 years ago |
|
Ville Syrjälä
|
8fcd5cd8b3
drm/i915: Simplify CHV pipe A power well code
|
10 years ago |
|
Ville Syrjälä
|
60bfe44f83
drm/i915: Apply OCD to VLV/CHV DPLL defines
|
10 years ago |
|
Ville Syrjälä
|
b8afb9113c
drm/i915: Keep GMCH DPLL VGA mode always disabled
|
10 years ago |
|
Ville Syrjälä
|
fde61e4b80
drm/i915: Throw out WIP CHV power well definitions
|
10 years ago |
|
Ville Syrjälä
|
bc284542da
drm/i915: Use the default 600ns LDO programming sequence delay
|
10 years ago |
 Masanari Iida
|
7e35ab88d8
drm/i915: Fix typo in intel_runtime_pm.c
|
10 years ago |
|
Ville Syrjälä
|
71849b67e7
Revert "drm/i915: Hack to tie both common lanes together on chv"
|
10 years ago |
|
Ville Syrjälä
|
7072246887
drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV
|
10 years ago |
|
Damien Lespiau
|
6222709d60
drm/i915/skl: Make the Misc I/O power well part of the PLLS domain
|
10 years ago |
|
Damien Lespiau
|
aeaa2122af
drm/i915/skl: Add the INIT power domain to the MISC I/O power well
|
10 years ago |
 Suketu Shah
|
93c7cb6c3a
drm/i915/skl: Assert the requirements to enter or exit DC6.
|
10 years ago |
 A.Sunil Kamath
|
74b4f371f5
Implement enable/disable for Display C6 state
|
10 years ago |
|
Suketu Shah
|
f75a198513
drm/i915/skl: Add DC6 Trigger sequence.
|
10 years ago |
|
Suketu Shah
|
5aefb2398a
drm/i915/skl: Assert the requirements to enter or exit DC5.
|
10 years ago |
|
A.Sunil Kamath
|
6b457d31ea
drm/i915/skl: Implement enable/disable for Display C5 state.
|
10 years ago |
|
Suketu Shah
|
dc17430054
drm/i915/skl: Add DC5 Trigger Sequence
|
10 years ago |
|
A.Sunil Kamath
|
664326f8a5
drm/i915/bxt: Implement enable/disable for Display C9 state
|
10 years ago |
 Satheeshakrishna M
|
0b4a2a36d0
drm/i915/bxt: Define BXT power domains
|
11 years ago |
 Geert Uytterhoeven
|
ca2b1403e2
drm/i915: Spelling s/auxilliary/auxiliary/
|
10 years ago |
|
Damien Lespiau
|
1d2b9526a7
drm/i915/skl: Restore the DDI translation tables when enabling PW1
|
10 years ago |
|
Damien Lespiau
|
254003926e
drm/i915: Remove unused condition in hsw_power_well_post_enable()
|
10 years ago |
|
Damien Lespiau
|
d14c034313
drm/i915/skl: Restore pipe interrupt registers after power well enabling
|
10 years ago |
|
Damien Lespiau
|
510e6fdd8f
drm/i915/skl: Mirror what we do on HSW for the power well enable log message
|
10 years ago |
|
Damien Lespiau
|
2a51835f61
drm/i915/skl: Introduce enable_requested and is_enabled in the power well code
|
10 years ago |
|
Damien Lespiau
|
4c6c03be12
drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask
|
10 years ago |
