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Commit History

Autor SHA1 Mensaxe Data
  Thierry Reding 39133505ca clk: tegra: Fix build warnings on Tegra20/Tegra30 %!s(int64=8) %!d(string=hai) anos
  Peter De Schrijver e827ba1840 clk: tegra: Add super clock mux/divider %!s(int64=8) %!d(string=hai) anos
  Peter De Schrijver 9e8c93edd2 clk: tegra: Fix constness for peripheral clocks %!s(int64=8) %!d(string=hai) anos
  Peter De Schrijver e589376dab clk: tegra: Fix type for m field %!s(int64=8) %!d(string=hai) anos
  Andrew Bresticker 15d68e8c2e clk: tegra: Initialize UTMI PLL when enabling PLLU %!s(int64=9) %!d(string=hai) anos
  Rhyland Klein 926655f929 clk: tegra: Fix pllre Tegra210 and add pll_re_out1 %!s(int64=9) %!d(string=hai) anos
  Thierry Reding 1ec7032ad5 clk: tegra: Add fixed factor peripheral clock type %!s(int64=10) %!d(string=hai) anos
  Thierry Reding 7e14f22305 clk: tegra: Constify peripheral clock registers %!s(int64=10) %!d(string=hai) anos
  Rhyland Klein 6b301a059e clk: tegra: Add support for Tegra210 clocks %!s(int64=10) %!d(string=hai) anos
  Bill Huang 139fd30943 clk: tegra: Add Super Gen5 Logic %!s(int64=10) %!d(string=hai) anos
  Bill Huang 0ef9db6cf2 clk: tegra: pll: Add logic for SS %!s(int64=10) %!d(string=hai) anos
  Rhyland Klein 17e9273a9e clk: tegra: pll: Add dyn_ramp callback %!s(int64=10) %!d(string=hai) anos
  Bill Huang b985114e2f clk: tegra: pll: Add Set_default logic %!s(int64=10) %!d(string=hai) anos
  Bill Huang b5512b45d5 clk: tegra: pll: Adjust vco_min if SDM present %!s(int64=10) %!d(string=hai) anos
  Rhyland Klein 6929715cf6 clk: tegra: pll: Add support for PLLMB for Tegra210 %!s(int64=10) %!d(string=hai) anos
  Rhyland Klein dd322f047d clk: tegra: pll: Add specialized logic for Tegra210 %!s(int64=10) %!d(string=hai) anos
  Bill Huang fde207eb15 clk: tegra: pll: Add code to handle if resets are supported by PLL %!s(int64=10) %!d(string=hai) anos
  Rhyland Klein 407254da29 clk: tegra: pll: Add logic for out-of-table rates for T210 %!s(int64=10) %!d(string=hai) anos
  Rhyland Klein d907f4b4a1 clk: tegra: pll: Add logic for handling SDM data %!s(int64=10) %!d(string=hai) anos
  Bill Huang 56fd27b31f clk: tegra: pll: Change misc_reg count from 3 to 6 %!s(int64=10) %!d(string=hai) anos
  Rhyland Klein 6583a6309e clk: tegra: pll: Add tegra_pll_wait_for_lock to clk header %!s(int64=10) %!d(string=hai) anos
  Thierry Reding 385f9adf62 clk: tegra: Constify pdiv-to-hw mappings %!s(int64=9) %!d(string=hai) anos
  Rhyland Klein 88d909bedf clk: tegra: Modify tegra_audio_clk_init to accept more plls %!s(int64=10) %!d(string=hai) anos
  Thierry Reding db592c4e2b clk: tegra: Update struct tegra_clk_pll_params kerneldoc %!s(int64=10) %!d(string=hai) anos
  Rhyland Klein fdc1feadc0 clk: tegra: Fix comments for structure definitions %!s(int64=10) %!d(string=hai) anos
  Mikko Perttunen 66b6f3d074 clk: tegra: Introduce ability for SoC-specific reset control callbacks %!s(int64=10) %!d(string=hai) anos
  Thierry Reding 31b52ba42d clk: tegra: EMC clock driver depends on EMC driver %!s(int64=10) %!d(string=hai) anos
  Mikko Perttunen 2db04f16b5 clk: tegra: Add EMC clock driver %!s(int64=10) %!d(string=hai) anos
  Thierry Reding 63cc5a4da1 clk: tegra: Model oscillator as clock %!s(int64=10) %!d(string=hai) anos
  Thierry Reding 8106462faa clk: tegra: Fix typo tabel -> table %!s(int64=11) %!d(string=hai) anos

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