 Ville Syrjälä
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3be60de9e9
drm/i915: Skip CHV PHY asserts until PHY has been fully reset
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10 лет назад |
 Jesse Barnes
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165ed87c47
drm/i915: fixup runtime PM handling v2
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10 лет назад |
 Animesh Manna
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08aef7caa1
drm/i915/skl: Block disable call for pw1 if dmc firmware is present.
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10 лет назад |
|
Jesse Barnes
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6ff8ab0d0f
drm/i915: make CSR firmware messages less verbose
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10 лет назад |
 Daniel Vetter
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e93c28f393
Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queued
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10 лет назад |
|
Ville Syrjälä
|
30142273a3
drm/i915: Add CHV PHY LDO power sanity checks
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10 лет назад |
|
Ville Syrjälä
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6669e39f95
drm/i915: Add some CHV DPIO lane power state asserts
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10 лет назад |
 Xiong Zhang
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d8e19f99d3
drm/i915/skl: Adding DDI_E power well domain
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10 лет назад |
|
Ville Syrjälä
|
3e28878635
drm/i915: Force CL2 off in CHV x1 PHY
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10 лет назад |
|
Ville Syrjälä
|
ee27921824
drm/i915: Enable DPIO SUS clock gating on CHV
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10 лет назад |
|
Ville Syrjälä
|
b0b3384612
drm/i915: Trick CL2 into life on CHV when using pipe B with port B
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10 лет назад |
|
Ville Syrjälä
|
e0fce78f04
drm/i915: Implement PHY lane power gating for CHV
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10 лет назад |
|
Ville Syrjälä
|
5a8fbb7d19
drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enable
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10 лет назад |
|
Ville Syrjälä
|
770effb19f
drm/i915: Add locking around chv_phy_control_init()
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10 лет назад |
 Damien Lespiau
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dcddab3aa0
drm/i915: Extract a intel_power_well_disable() function
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10 лет назад |
|
Damien Lespiau
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e8ca932056
drm/i915: Extract a intel_power_well_enable() function
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10 лет назад |
|
Ville Syrjälä
|
2be7d540fd
drm/i915: Refactor VLV display power well init/deinit
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10 лет назад |
|
Ville Syrjälä
|
8fcd5cd8b3
drm/i915: Simplify CHV pipe A power well code
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10 лет назад |
|
Ville Syrjälä
|
60bfe44f83
drm/i915: Apply OCD to VLV/CHV DPLL defines
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10 лет назад |
|
Ville Syrjälä
|
b8afb9113c
drm/i915: Keep GMCH DPLL VGA mode always disabled
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10 лет назад |
|
Ville Syrjälä
|
fde61e4b80
drm/i915: Throw out WIP CHV power well definitions
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10 лет назад |
|
Ville Syrjälä
|
bc284542da
drm/i915: Use the default 600ns LDO programming sequence delay
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10 лет назад |
 Masanari Iida
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7e35ab88d8
drm/i915: Fix typo in intel_runtime_pm.c
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10 лет назад |
|
Ville Syrjälä
|
71849b67e7
Revert "drm/i915: Hack to tie both common lanes together on chv"
|
10 лет назад |
|
Ville Syrjälä
|
7072246887
drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV
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10 лет назад |
|
Damien Lespiau
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6222709d60
drm/i915/skl: Make the Misc I/O power well part of the PLLS domain
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10 лет назад |
|
Damien Lespiau
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aeaa2122af
drm/i915/skl: Add the INIT power domain to the MISC I/O power well
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10 лет назад |
 Suketu Shah
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93c7cb6c3a
drm/i915/skl: Assert the requirements to enter or exit DC6.
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10 лет назад |
 A.Sunil Kamath
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74b4f371f5
Implement enable/disable for Display C6 state
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10 лет назад |
|
Suketu Shah
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f75a198513
drm/i915/skl: Add DC6 Trigger sequence.
|
10 лет назад |
