 Jerome Brunet
|
22f65a389f
clk: meson: use SPDX license identifiers consistently
|
7 years ago |
 Martin Blumenstingl
|
b8c1ddadc8
clk: meson: meson8b: add support for the NAND clocks
|
7 years ago |
|
Jerome Brunet
|
05f814402d
clk: meson: add fdiv clock gates
|
7 years ago |
|
Jerome Brunet
|
513b67ac39
clk: meson: add mpll pre-divider
|
7 years ago |
|
Jerome Brunet
|
251b6fd38b
clk: meson: rework meson8b cpu clock
|
7 years ago |
|
Jerome Brunet
|
d610b54f77
clk: meson: split divider and gate part of mpll
|
7 years ago |
|
Martin Blumenstingl
|
189621726b
clk: meson: meson8b: register the built-in reset controller
|
8 years ago |
|
Jerome Brunet
|
31128822ce
clk: meson8b: expose every clock in the bindings
|
8 years ago |
|
Martin Blumenstingl
|
c22f06d3c0
clk: meson8b: export the ethernet gate clock
|
8 years ago |
|
Martin Blumenstingl
|
677f6af5d6
clk: meson8b: export the USB clocks
|
8 years ago |
|
Martin Blumenstingl
|
06eff6a792
clk: meson8b: export the gate clock for the HW random number generator
|
8 years ago |
|
Martin Blumenstingl
|
e2e5f3211f
clk: meson8b: export the SDIO clock
|
8 years ago |
|
Martin Blumenstingl
|
70ad0d0351
clk: meson8b: export the SAR ADC clocks
|
8 years ago |
|
Jerome Brunet
|
b778f7451a
clk: meson8b: add the mplls clocks 0, 1 and 2
|
8 years ago |
 Alexander Müller
|
e31a1900c1
meson: clk: Add support for clock gates
|
9 years ago |
|
Alexander Müller
|
0f32e64b22
clk: meson: Copy meson8b CLKID defines to private header file
|
9 years ago |
|
Alexander Müller
|
e0818a3960
meson: clk: Rename register names according to Amlogic datasheet
|
9 years ago |
|
Alexander Müller
|
d0c175da68
meson: clk: Move register definitions to meson8b.h
|
9 years ago |
