Commit History

Author SHA1 Message Date
  Jerome Brunet 05f814402d clk: meson: add fdiv clock gates 7 years ago
  Jerome Brunet 513b67ac39 clk: meson: add mpll pre-divider 7 years ago
  Jerome Brunet 093c3fac46 clk: meson: axg: add hifi pll clock 7 years ago
  Jerome Brunet d610b54f77 clk: meson: split divider and gate part of mpll 7 years ago
  Qiufang Dai 78b4af312f clk: meson-axg: add clock controller drivers 7 years ago