 Damien Lespiau
|
2f693e28b8
drm/i915: Make turning on/off PW1 and Misc I/O part of the init/fini sequences
|
10 years ago |
 Imre Deak
|
fc17f2274e
drm/i915: fix lookup_power_well for power wells without any domain
|
10 years ago |
|
Imre Deak
|
56fcfd6333
drm/i915: fix the power well ID for always on wells
|
10 years ago |
 Animesh Manna
|
ca1283d502
drm/i915/skl: Removed assert for csr-fw-loading check during disabling dc6
|
10 years ago |
 Daniel Vetter
|
414b7999b8
drm/i915/gen9: Remove csr.state, csr_lock and related code.
|
10 years ago |
|
Daniel Vetter
|
af5fead2d9
drm/i915/gen9: move assert_csr_loaded into intel_rpm.c
|
10 years ago |
 Ville Syrjälä
|
18a04a7369
drm/i915: Kill intel_runtime_pm_disable()
|
10 years ago |
 Rodrigo Vivi
|
ef11bdb3e0
drm/i915/kbl: Introduce Kabylake platform defition.
|
10 years ago |
|
Animesh Manna
|
0a9d2bed55
drm/i915/skl: Making DC6 entry is the last call in suspend flow.
|
10 years ago |
|
Ville Syrjälä
|
3be60de9e9
drm/i915: Skip CHV PHY asserts until PHY has been fully reset
|
10 years ago |
 Jesse Barnes
|
165ed87c47
drm/i915: fixup runtime PM handling v2
|
10 years ago |
|
Animesh Manna
|
08aef7caa1
drm/i915/skl: Block disable call for pw1 if dmc firmware is present.
|
10 years ago |
|
Jesse Barnes
|
6ff8ab0d0f
drm/i915: make CSR firmware messages less verbose
|
10 years ago |
 Daniel Vetter
|
e93c28f393
Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queued
|
10 years ago |
|
Ville Syrjälä
|
30142273a3
drm/i915: Add CHV PHY LDO power sanity checks
|
10 years ago |
|
Ville Syrjälä
|
6669e39f95
drm/i915: Add some CHV DPIO lane power state asserts
|
10 years ago |
 Xiong Zhang
|
d8e19f99d3
drm/i915/skl: Adding DDI_E power well domain
|
10 years ago |
|
Ville Syrjälä
|
3e28878635
drm/i915: Force CL2 off in CHV x1 PHY
|
10 years ago |
|
Ville Syrjälä
|
ee27921824
drm/i915: Enable DPIO SUS clock gating on CHV
|
10 years ago |
|
Ville Syrjälä
|
b0b3384612
drm/i915: Trick CL2 into life on CHV when using pipe B with port B
|
10 years ago |
|
Ville Syrjälä
|
e0fce78f04
drm/i915: Implement PHY lane power gating for CHV
|
10 years ago |
|
Ville Syrjälä
|
5a8fbb7d19
drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enable
|
10 years ago |
|
Ville Syrjälä
|
770effb19f
drm/i915: Add locking around chv_phy_control_init()
|
10 years ago |
|
Damien Lespiau
|
dcddab3aa0
drm/i915: Extract a intel_power_well_disable() function
|
10 years ago |
|
Damien Lespiau
|
e8ca932056
drm/i915: Extract a intel_power_well_enable() function
|
10 years ago |
|
Ville Syrjälä
|
2be7d540fd
drm/i915: Refactor VLV display power well init/deinit
|
10 years ago |
|
Ville Syrjälä
|
8fcd5cd8b3
drm/i915: Simplify CHV pipe A power well code
|
10 years ago |
|
Ville Syrjälä
|
60bfe44f83
drm/i915: Apply OCD to VLV/CHV DPLL defines
|
10 years ago |
|
Ville Syrjälä
|
b8afb9113c
drm/i915: Keep GMCH DPLL VGA mode always disabled
|
10 years ago |
|
Ville Syrjälä
|
fde61e4b80
drm/i915: Throw out WIP CHV power well definitions
|
10 years ago |
