 Will Deacon
|
b6ccb9803e
ARM: 7954/1: mm: remove remaining domain support from ARMv6
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%!s(int64=11) %!d(string=hai) anos |
|
Will Deacon
|
bf3f0f332f
ARM: 7784/1: mm: ensure SMP alternates assemble to exactly 4 bytes with Thumb-2
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%!s(int64=12) %!d(string=hai) anos |
 Paul Gortmaker
|
8bd26e3a7e
arm: delete __cpuinit/__CPUINIT usage from all ARM users
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%!s(int64=12) %!d(string=hai) anos |
|
Will Deacon
|
ae8a8b9553
ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead
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%!s(int64=12) %!d(string=hai) anos |
 Ben Dooks
|
251019fb97
ARM: 7650/1: mm: replace direct access to mm->context.id with new macro
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%!s(int64=12) %!d(string=hai) anos |
|
Will Deacon
|
26ffd0d43b
ARM: mm: introduce present, faulting entries for PAGE_NONE
|
%!s(int64=13) %!d(string=hai) anos |
|
Will Deacon
|
dbf62d5006
ARM: mm: introduce L_PTE_VALID for page table entries
|
%!s(int64=13) %!d(string=hai) anos |
|
Will Deacon
|
0cbbbad631
ARM: mm: don't use the access flag permissions mechanism for classic MMU
|
%!s(int64=13) %!d(string=hai) anos |
|
Will Deacon
|
575320d625
ARM: 7445/1: mm: update CONTEXTIDR register to contain PID of current process
|
%!s(int64=13) %!d(string=hai) anos |
 Catalin Marinas
|
7fec1b57b8
ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on ASID-capable CPUs
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%!s(int64=13) %!d(string=hai) anos |
|
Will Deacon
|
3c5f7e7b4a
ARM: Use TTBR1 instead of reserved context ID
|
%!s(int64=14) %!d(string=hai) anos |
|
Catalin Marinas
|
8d2cd3a38f
ARM: LPAE: Factor out classic-MMU specific code into proc-v7-2level.S
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%!s(int64=13) %!d(string=hai) anos |
