Commit History

作者 SHA1 備註 提交日期
  Alan Tull 084181fe8c fpga: mgr: add devm_fpga_mgr_create 6 年之前
  Alan Tull 7085e2a94f fpga: manager: change api, don't use drvdata 7 年之前
  Moritz Fischer 7f33bbca14 fpga: zynq: Add support for encrypted bitstreams 8 年之前
  Jason Gunthorpe 425902f5c8 fpga zynq: Use the scatterlist interface 8 年之前
  Jason Gunthorpe b496df86ac fpga zynq: Check the bitstream for validity 8 年之前
  Jason Gunthorpe 6b45e0f24c fpga zynq: Check for errors after completing DMA 8 年之前
  Jason Gunthorpe 340c0c53ea fpga zynq: Fix incorrect ISR state on bootup 8 年之前
  Jason Gunthorpe 80baf649c2 fpga zynq: Remove priv->dev 8 年之前
  Jason Gunthorpe 1930c28651 fpga zynq: Add missing \n to messages 8 年之前
  Alan Tull 1df2865f8d fpga-mgr: add fpga image information struct 8 年之前
  Moritz Fischer 28f98a12f7 fpga: zynq-fpga: Fix issue with drvdata being overwritten. 9 年之前
  Moritz Fischer 4d10eaff5b fpga: zynq-fpga: Change fw format to handle bin instead of bit. 9 年之前
  Moritz Fischer 6376931bab fpga: zynq-fpga: Fix unbalanced clock handling 9 年之前
  Moritz Fischer 37784706bf fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000 9 年之前