 Rodrigo Vivi
|
5e56ba4505
drm/i915/chv: Use 16 and 32 for low and high drain latency precision.
|
11 years ago |
|
Rodrigo Vivi
|
101b376d35
drm/i915/bdw: Remove BDW preproduction W/As until C stepping.
|
11 years ago |
|
Rodrigo Vivi
|
58abf1daae
drm/i915: Do not export RC6p and RC6pp if they don't exist
|
11 years ago |
 Daniel Vetter
|
a8cbd45977
Merge branch 'drm-intel-next-fixes' into drm-intel-next
|
11 years ago |
|
Daniel Vetter
|
2aeb7d3a4d
drm/i915: s/pm._irqs_disabled/pm.irqs_enabled/
|
11 years ago |
|
Daniel Vetter
|
9c065a7d5b
drm/i915: Extract intel_runtime_pm.c
|
11 years ago |
|
Daniel Vetter
|
955e36d0b4
Merge branch 'topic/skl-stage1' into drm-intel-next-queued
|
11 years ago |
 Ville Syrjälä
|
67956867aa
drm/i915: Don't spam dmesg with rps messages on vlv/chv
|
11 years ago |
|
Daniel Vetter
|
7526ed79b0
Revert "drm/i915/bdw: BDW Software Turbo"
|
11 years ago |
|
Rodrigo Vivi
|
1d73c2a8f2
drm/i915: Minimize the huge amount of unecessary fbc sw cache clean.
|
11 years ago |
 Damien Lespiau
|
c83155a604
drm/i915/skl: Move gen9 pm initialization into its own branch
|
11 years ago |
|
Damien Lespiau
|
3ca5da4300
drm/i915/skl: Implement WaDisableDgMirrorFixInHalfSliceChicken5:skl
|
11 years ago |
|
Damien Lespiau
|
91e41d1665
drm/i915/skl: Implement Wa4x4STCOptimizationDisable:skl
|
11 years ago |
|
Damien Lespiau
|
acd5c34640
drm/i915/skl: Implement WaDisableSDEUnitClockGating:skl
|
11 years ago |
 Satheeshakrishna M
|
08524a9ffa
drm/i915/skl: Restore pipe B/C interrupts
|
11 years ago |
|
Damien Lespiau
|
da2078cd00
drm/i915/skl: Provide a placeholder for init_clock_gating()
|
12 years ago |
 Paulo Zanoni
|
9adccc6063
drm/i915: add SW tracking to FBC enabling
|
11 years ago |
|
Paulo Zanoni
|
d2dee86cec
drm/i915: extract intel_init_fbc()
|
11 years ago |
|
Rodrigo Vivi
|
342e36c6b0
drm/i915: Avoid reading fbc registers in vain when fbc was never enabled.
|
11 years ago |
|
Rodrigo Vivi
|
01d06e9f96
drm/i915: Only flush fbc on sw when fbc is enabled.
|
11 years ago |
|
Ville Syrjälä
|
d6feb1962d
drm/i915: Limit the watermark to at least 8 entries on gen2/3
|
11 years ago |
|
Ville Syrjälä
|
773538e860
drm/i915: Reset power sequencer pipe tracking when disp2d is off
|
11 years ago |
 Chris Wilson
|
5aef600321
drm/i915: Rename global latency_ns variable
|
11 years ago |
|
Ville Syrjälä
|
1038392b4d
drm/i915: Disable trickle feed for gen2/3
|
11 years ago |
|
Ville Syrjälä
|
9d53910580
drm/i915: Fix gen2 planes B and C max watermark value
|
11 years ago |
|
Ville Syrjälä
|
00e1e623e6
drm/i915: Init some CHV workarounds via LRIs in ring->init_context()
|
11 years ago |
|
Ville Syrjälä
|
1c14762d0c
drm/i915: Warn about odd rps values on CHV
|
11 years ago |
 Daisy Sun
|
c76bb61a71
drm/i915/bdw: BDW Software Turbo
|
11 years ago |
|
Ville Syrjälä
|
2bb25c17bb
drm/i915: Populate mem_freq in init_gt_powerwave()
|
11 years ago |
 Arun Siluvery
|
86d7f23842
drm/i915/bdw: Apply workarounds in render ring init function
|
11 years ago |
