Commit History

Author SHA1 Message Date
  Dinh Nguyen 0691bb1b5a clk: socfpga: add divider registers to the main pll outputs 11 years ago
  Dinh Nguyen 044abbde7b clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk" 11 years ago
  Steffen Trumtrar 97259e99bd clk: socfpga: split clk code 11 years ago