 Michal Simek
|
00f7dc6363
ARM: zynq: Add support for SOC_BUS
|
%!s(int64=12) %!d(string=hai) anos |
|
Michal Simek
|
568800731a
ARM: zynq: Introduce zynq_slcr_unlock()
|
%!s(int64=11) %!d(string=hai) anos |
|
Michal Simek
|
871c6971ec
ARM: zynq: Add and use zynq_slcr_read/write() helper functions
|
%!s(int64=11) %!d(string=hai) anos |
 Steffen Trumtrar
|
7b274efef7
ARM: zynq: Make zynq_slcr_base static
|
%!s(int64=12) %!d(string=hai) anos |
|
Steffen Trumtrar
|
5e21828034
ARM: zynq: Hang iomapped slcr address on device_node
|
%!s(int64=11) %!d(string=hai) anos |
|
Michal Simek
|
016f4dcae8
ARM: zynq: Split slcr in two parts
|
%!s(int64=11) %!d(string=hai) anos |
|
Steffen Trumtrar
|
6f69c7f21c
ARM: zynq: Move clock_init from slcr to common
|
%!s(int64=12) %!d(string=hai) anos |
 Soren Brinkmann
|
3db9e86029
arm: zynq: slcr: Use read-modify-write for register writes
|
%!s(int64=12) %!d(string=hai) anos |
|
Soren Brinkmann
|
b5f177ff30
arm: zynq: slcr: Clean up #defines
|
%!s(int64=12) %!d(string=hai) anos |
|
Soren Brinkmann
|
c323f2a188
arm: zynq: slcr: Remove redundant header #includes
|
%!s(int64=12) %!d(string=hai) anos |
|
Soren Brinkmann
|
30e1e28598
arm: zynq: Migrate platform to clock controller
|
%!s(int64=12) %!d(string=hai) anos |
|
Michal Simek
|
aa7eb2bb4e
arm: zynq: Add smp support
|
%!s(int64=12) %!d(string=hai) anos |
|
Michal Simek
|
96790f0a28
arm: zynq: Add support for system reset
|
%!s(int64=12) %!d(string=hai) anos |
|
Michal Simek
|
64b889b39e
arm: zynq: Move slcr initialization to separate file
|
%!s(int64=12) %!d(string=hai) anos |
