 Ville Syrjälä
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ac9b823655
drm/i915: Introduce a gmbus power domain
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9 years ago |
 Dave Airlie
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816d2206f0
Merge tag 'drm-intel-next-fixes-2015-11-06' of git://anongit.freedesktop.org/drm-intel into drm-next
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9 years ago |
 Imre Deak
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1b0e3a049e
drm/i915/skl: disable display side power well support for now
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9 years ago |
 Dave Airlie
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2dd3a88ac8
Merge tag 'drm-intel-next-2015-10-10' of git://anongit.freedesktop.org/drm-intel into drm-next
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10 years ago |
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Dave Airlie
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48f87dd146
Merge commit '06d1ee32a4d25356a710b49d5e95dbdd68bdf505' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into drm-next
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10 years ago |
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Ville Syrjälä
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3be60de9e9
drm/i915: Skip CHV PHY asserts until PHY has been fully reset
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10 years ago |
 Jesse Barnes
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165ed87c47
drm/i915: fixup runtime PM handling v2
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10 years ago |
 Animesh Manna
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08aef7caa1
drm/i915/skl: Block disable call for pw1 if dmc firmware is present.
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10 years ago |
 Rodrigo Vivi
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bc5f2ab11c
drm/i915/skl: Don't call intel_prepare_ddi when encoder list isn't yet initialized.
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10 years ago |
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Jesse Barnes
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6ff8ab0d0f
drm/i915: make CSR firmware messages less verbose
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10 years ago |
 Daniel Vetter
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e93c28f393
Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queued
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10 years ago |
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Ville Syrjälä
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30142273a3
drm/i915: Add CHV PHY LDO power sanity checks
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10 years ago |
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Ville Syrjälä
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6669e39f95
drm/i915: Add some CHV DPIO lane power state asserts
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10 years ago |
 Xiong Zhang
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d8e19f99d3
drm/i915/skl: Adding DDI_E power well domain
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10 years ago |
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Ville Syrjälä
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3e28878635
drm/i915: Force CL2 off in CHV x1 PHY
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10 years ago |
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Ville Syrjälä
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ee27921824
drm/i915: Enable DPIO SUS clock gating on CHV
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10 years ago |
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Ville Syrjälä
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b0b3384612
drm/i915: Trick CL2 into life on CHV when using pipe B with port B
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10 years ago |
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Ville Syrjälä
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e0fce78f04
drm/i915: Implement PHY lane power gating for CHV
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10 years ago |
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Ville Syrjälä
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5a8fbb7d19
drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enable
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10 years ago |
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Ville Syrjälä
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770effb19f
drm/i915: Add locking around chv_phy_control_init()
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10 years ago |
 Damien Lespiau
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dcddab3aa0
drm/i915: Extract a intel_power_well_disable() function
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10 years ago |
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Damien Lespiau
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e8ca932056
drm/i915: Extract a intel_power_well_enable() function
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10 years ago |
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Ville Syrjälä
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2be7d540fd
drm/i915: Refactor VLV display power well init/deinit
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10 years ago |
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Ville Syrjälä
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8fcd5cd8b3
drm/i915: Simplify CHV pipe A power well code
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10 years ago |
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Ville Syrjälä
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60bfe44f83
drm/i915: Apply OCD to VLV/CHV DPLL defines
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10 years ago |
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Ville Syrjälä
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b8afb9113c
drm/i915: Keep GMCH DPLL VGA mode always disabled
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10 years ago |
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Ville Syrjälä
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fde61e4b80
drm/i915: Throw out WIP CHV power well definitions
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10 years ago |
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Ville Syrjälä
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bc284542da
drm/i915: Use the default 600ns LDO programming sequence delay
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10 years ago |
 Masanari Iida
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7e35ab88d8
drm/i915: Fix typo in intel_runtime_pm.c
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10 years ago |
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Ville Syrjälä
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71849b67e7
Revert "drm/i915: Hack to tie both common lanes together on chv"
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10 years ago |
